1/**
2 * dts file for Hisilicon D03 Development Board
3 *
4 * Copyright (C) 2016 Hisilicon Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15	compatible = "hisilicon,hip06-d03";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	psci {
21		compatible = "arm,psci-0.2";
22		method = "smc";
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu-map {
30			cluster0 {
31				core0 {
32					cpu = <&cpu0>;
33				};
34				core1 {
35					cpu = <&cpu1>;
36				};
37				core2 {
38					cpu = <&cpu2>;
39				};
40				core3 {
41					cpu = <&cpu3>;
42				};
43			};
44			cluster1 {
45				core0 {
46					cpu = <&cpu4>;
47				};
48				core1 {
49					cpu = <&cpu5>;
50				};
51				core2 {
52					cpu = <&cpu6>;
53				};
54				core3 {
55					cpu = <&cpu7>;
56				};
57			};
58			cluster2 {
59				core0 {
60					cpu = <&cpu8>;
61				};
62				core1 {
63					cpu = <&cpu9>;
64				};
65				core2 {
66					cpu = <&cpu10>;
67				};
68				core3 {
69					cpu = <&cpu11>;
70				};
71			};
72			cluster3 {
73				core0 {
74					cpu = <&cpu12>;
75				};
76				core1 {
77					cpu = <&cpu13>;
78				};
79				core2 {
80					cpu = <&cpu14>;
81				};
82				core3 {
83					cpu = <&cpu15>;
84				};
85			};
86		};
87
88		cpu0: cpu@10000 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a57", "arm,armv8";
91			reg = <0x10000>;
92			enable-method = "psci";
93			next-level-cache = <&cluster0_l2>;
94		};
95
96		cpu1: cpu@10001 {
97			device_type = "cpu";
98			compatible = "arm,cortex-a57", "arm,armv8";
99			reg = <0x10001>;
100			enable-method = "psci";
101			next-level-cache = <&cluster0_l2>;
102		};
103
104		cpu2: cpu@10002 {
105			device_type = "cpu";
106			compatible = "arm,cortex-a57", "arm,armv8";
107			reg = <0x10002>;
108			enable-method = "psci";
109			next-level-cache = <&cluster0_l2>;
110		};
111
112		cpu3: cpu@10003 {
113			device_type = "cpu";
114			compatible = "arm,cortex-a57", "arm,armv8";
115			reg = <0x10003>;
116			enable-method = "psci";
117			next-level-cache = <&cluster0_l2>;
118		};
119
120		cpu4: cpu@10100 {
121			device_type = "cpu";
122			compatible = "arm,cortex-a57", "arm,armv8";
123			reg = <0x10100>;
124			enable-method = "psci";
125			next-level-cache = <&cluster1_l2>;
126		};
127
128		cpu5: cpu@10101 {
129			device_type = "cpu";
130			compatible = "arm,cortex-a57", "arm,armv8";
131			reg = <0x10101>;
132			enable-method = "psci";
133			next-level-cache = <&cluster1_l2>;
134		};
135
136		cpu6: cpu@10102 {
137			device_type = "cpu";
138			compatible = "arm,cortex-a57", "arm,armv8";
139			reg = <0x10102>;
140			enable-method = "psci";
141			next-level-cache = <&cluster1_l2>;
142		};
143
144		cpu7: cpu@10103 {
145			device_type = "cpu";
146			compatible = "arm,cortex-a57", "arm,armv8";
147			reg = <0x10103>;
148			enable-method = "psci";
149			next-level-cache = <&cluster1_l2>;
150		};
151
152		cpu8: cpu@10200 {
153			device_type = "cpu";
154			compatible = "arm,cortex-a57", "arm,armv8";
155			reg = <0x10200>;
156			enable-method = "psci";
157			next-level-cache = <&cluster2_l2>;
158		};
159
160		cpu9: cpu@10201 {
161			device_type = "cpu";
162			compatible = "arm,cortex-a57", "arm,armv8";
163			reg = <0x10201>;
164			enable-method = "psci";
165			next-level-cache = <&cluster2_l2>;
166		};
167
168		cpu10: cpu@10202 {
169			device_type = "cpu";
170			compatible = "arm,cortex-a57", "arm,armv8";
171			reg = <0x10202>;
172			enable-method = "psci";
173			next-level-cache = <&cluster2_l2>;
174		};
175
176		cpu11: cpu@10203 {
177			device_type = "cpu";
178			compatible = "arm,cortex-a57", "arm,armv8";
179			reg = <0x10203>;
180			enable-method = "psci";
181			next-level-cache = <&cluster2_l2>;
182		};
183
184		cpu12: cpu@10300 {
185			device_type = "cpu";
186			compatible = "arm,cortex-a57", "arm,armv8";
187			reg = <0x10300>;
188			enable-method = "psci";
189			next-level-cache = <&cluster3_l2>;
190		};
191
192		cpu13: cpu@10301 {
193			device_type = "cpu";
194			compatible = "arm,cortex-a57", "arm,armv8";
195			reg = <0x10301>;
196			enable-method = "psci";
197			next-level-cache = <&cluster3_l2>;
198		};
199
200		cpu14: cpu@10302 {
201			device_type = "cpu";
202			compatible = "arm,cortex-a57", "arm,armv8";
203			reg = <0x10302>;
204			enable-method = "psci";
205			next-level-cache = <&cluster3_l2>;
206		};
207
208		cpu15: cpu@10303 {
209			device_type = "cpu";
210			compatible = "arm,cortex-a57", "arm,armv8";
211			reg = <0x10303>;
212			enable-method = "psci";
213			next-level-cache = <&cluster3_l2>;
214		};
215
216		cluster0_l2: l2-cache0 {
217			compatible = "cache";
218		};
219
220		cluster1_l2: l2-cache1 {
221			compatible = "cache";
222		};
223
224		cluster2_l2: l2-cache2 {
225			compatible = "cache";
226		};
227
228		cluster3_l2: l2-cache3 {
229			compatible = "cache";
230		};
231	};
232
233	gic: interrupt-controller@4d000000 {
234		compatible = "arm,gic-v3";
235		#interrupt-cells = <3>;
236		#address-cells = <2>;
237		#size-cells = <2>;
238		ranges;
239		interrupt-controller;
240		#redistributor-regions = <1>;
241		redistributor-stride = <0x0 0x30000>;
242		reg = <0x0 0x4d000000 0 0x10000>,	/* GICD */
243		      <0x0 0x4d100000 0 0x300000>,	/* GICR */
244		      <0x0 0xfe000000 0 0x10000>,	/* GICC */
245		      <0x0 0xfe010000 0 0x10000>,       /* GICH */
246		      <0x0 0xfe020000 0 0x10000>;       /* GICV */
247		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
248
249		its_dsa: interrupt-controller@c6000000 {
250			compatible = "arm,gic-v3-its";
251			msi-controller;
252			#msi-cells = <1>;
253			reg = <0x0 0xc6000000 0x0 0x40000>;
254		};
255	};
256
257	timer {
258		compatible = "arm,armv8-timer";
259		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
260			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
261			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
262			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
263	};
264
265	pmu {
266		compatible = "arm,cortex-a57-pmu";
267		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
268	};
269
270	mbigen_pcie@a0080000 {
271		compatible = "hisilicon,mbigen-v2";
272		reg = <0x0 0xa0080000 0x0 0x10000>;
273
274		mbigen_usb: intc_usb {
275			msi-parent = <&its_dsa 0x40080>;
276			interrupt-controller;
277			#interrupt-cells = <2>;
278			num-pins = <2>;
279		};
280
281		mbigen_sas1: intc_sas1 {
282			msi-parent = <&its_dsa 0x40000>;
283			interrupt-controller;
284			#interrupt-cells = <2>;
285			num-pins = <128>;
286		};
287
288		mbigen_sas2: intc_sas2 {
289			msi-parent = <&its_dsa 0x40040>;
290			interrupt-controller;
291			#interrupt-cells = <2>;
292			num-pins = <128>;
293		};
294
295		mbigen_pcie0: intc_pcie0 {
296			msi-parent = <&its_dsa 0x40085>;
297			interrupt-controller;
298			#interrupt-cells = <2>;
299			num-pins = <10>;
300		};
301	};
302
303	mbigen_dsa@c0080000 {
304		compatible = "hisilicon,mbigen-v2";
305		reg = <0x0 0xc0080000 0x0 0x10000>;
306
307		mbigen_dsaf0: intc_dsaf0 {
308			msi-parent = <&its_dsa 0x40800>;
309			interrupt-controller;
310			#interrupt-cells = <2>;
311			num-pins = <409>;
312		};
313
314		mbigen_sas0: intc-sas0 {
315			msi-parent = <&its_dsa 0x40900>;
316			interrupt-controller;
317			#interrupt-cells = <2>;
318			num-pins = <128>;
319		};
320	};
321
322	/**
323	 *  HiSilicon erratum 161010801: This describes the limitation
324	 *  of HiSilicon platforms hip06/hip07 to support the SMMUv3
325	 *  mappings for PCIe MSI transactions.
326	 *  PCIe controller on these platforms has to differentiate the
327	 *  MSI payload against other DMA payload and has to modify the
328	 *  MSI payload. This makes it difficult for these platforms to
329	 *  have a SMMU translation for MSI. In order to workaround this,
330	 *  ARM SMMUv3 driver requires a quirk to treat the MSI regions
331	 *  separately. Such a quirk is currently missing for DT based
332	 *  systems. Hence please make sure that the smmu pcie node on
333	 *  hip06 is disabled as this will break the PCIe functionality
334	 *  when iommu-map entry is used along with the PCIe node.
335	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
336	 */
337	smmu0: smmu_pcie {
338		compatible = "arm,smmu-v3";
339		reg = <0x0 0xa0040000 0x0 0x20000>;
340		#iommu-cells = <1>;
341		dma-coherent;
342		smmu-cb-memtype = <0x0 0x1>;
343		hisilicon,broken-prefetch-cmd;
344		status = "disabled";
345	};
346
347	soc {
348		compatible = "simple-bus";
349		#address-cells = <2>;
350		#size-cells = <2>;
351		ranges;
352
353		refclk: refclk {
354			compatible = "fixed-clock";
355			clock-frequency = <50000000>;
356			#clock-cells = <0>;
357		};
358
359		usb_ohci: ohci@a7030000 {
360			compatible = "generic-ohci";
361			reg = <0x0 0xa7030000 0x0 0x10000>;
362			interrupt-parent = <&mbigen_usb>;
363			interrupts = <640 4>;
364			dma-coherent;
365			status = "disabled";
366		};
367
368		usb_ehci: ehci@a7020000 {
369			compatible = "generic-ehci";
370			reg = <0x0 0xa7020000 0x0 0x10000>;
371			interrupt-parent = <&mbigen_usb>;
372			interrupts = <641 4>;
373			dma-coherent;
374			status = "disabled";
375		};
376
377		peri_c_subctrl: sub_ctrl_c@60000000 {
378			compatible = "hisilicon,peri-subctrl","syscon";
379			reg = <0 0x60000000 0x0 0x10000>;
380		};
381
382		dsa_subctrl: dsa_subctrl@c0000000 {
383			compatible = "hisilicon,dsa-subctrl", "syscon";
384			reg = <0x0 0xc0000000 0x0 0x10000>;
385		};
386
387		pcie_subctl: pcie_subctl@a0000000 {
388			compatible = "hisilicon,pcie-sas-subctrl", "syscon";
389			reg = <0x0 0xa0000000 0x0 0x10000>;
390		};
391
392		serdes_ctrl: sds_ctrl@c2200000 {
393			compatible = "syscon";
394			reg = <0 0xc2200000 0x0 0x80000>;
395		};
396
397		mdio@603c0000 {
398			compatible = "hisilicon,hns-mdio";
399			reg = <0x0 0x603c0000 0x0 0x1000>;
400			subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
401			#address-cells = <1>;
402			#size-cells = <0>;
403
404			phy0: ethernet-phy@0 {
405				compatible = "ethernet-phy-ieee802.3-c22";
406				reg = <0>;
407			};
408
409			phy1: ethernet-phy@1 {
410				compatible = "ethernet-phy-ieee802.3-c22";
411				reg = <1>;
412			};
413		};
414
415		dsaf0: dsa@c7000000 {
416			#address-cells = <1>;
417			#size-cells = <0>;
418			compatible = "hisilicon,hns-dsaf-v2";
419			mode = "6port-16rss";
420			reg = <0x0 0xc5000000 0x0 0x890000
421			       0x0 0xc7000000 0x0 0x600000>;
422			reg-names = "ppe-base", "dsaf-base";
423			interrupt-parent = <&mbigen_dsaf0>;
424			subctrl-syscon = <&dsa_subctrl>;
425			reset-field-offset = <0>;
426			interrupts =
427			<576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
428			<581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
429			<586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
430			<591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
431			<596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
432			<960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
433			<965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
434			<970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
435			<975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
436			<980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
437			<985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
438			<990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
439			<995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
440			<1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
441			<1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
442			<1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
443			<1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
444			<1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
445			<1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
446			<1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
447			<1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
448			<1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
449			<1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
450			<1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
451			<1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
452			<1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
453			<1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
454			<1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
455			<1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
456			<1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
457			<1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
458			<1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
459			<1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
460			<1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
461			<1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
462			<1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
463			<1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
464			<1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
465			<1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
466			<1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
467			<1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
468			<1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
469			<1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
470			<1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
471			<1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
472			<1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
473			<1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
474			<1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
475			<1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
476			<1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
477			<1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
478			<1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
479			<1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
480			<1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
481			<1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
482			<1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
483			<1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
484			<1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
485			<1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
486			<1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
487			<1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
488			<1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
489			<1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
490			<1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
491			<1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
492			<1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
493			<1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
494			<1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
495			<1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
496			<1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
497			<1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
498			<1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
499			<1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
500			<1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
501			<1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
502			<1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
503			<1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
504			<1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
505			<1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
506			<1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
507			<1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
508			<1340 1>, <1341 1>, <1342 1>, <1343 1>;
509
510			desc-num = <0x400>;
511			buf-size = <0x1000>;
512			dma-coherent;
513
514			port@0 {
515				reg = <0>;
516				serdes-syscon = <&serdes_ctrl>;
517				port-rst-offset = <0>;
518				port-mode-offset = <0>;
519				media-type = "fiber";
520			};
521
522			port@1 {
523				reg = <1>;
524				serdes-syscon= <&serdes_ctrl>;
525				port-rst-offset = <1>;
526				port-mode-offset = <1>;
527				media-type = "fiber";
528			};
529
530			port@4 {
531				reg = <4>;
532				phy-handle = <&phy0>;
533				serdes-syscon= <&serdes_ctrl>;
534				port-rst-offset = <4>;
535				port-mode-offset = <2>;
536				media-type = "copper";
537			};
538
539			port@5 {
540				reg = <5>;
541				phy-handle = <&phy1>;
542				serdes-syscon= <&serdes_ctrl>;
543				port-rst-offset = <5>;
544				port-mode-offset = <3>;
545				media-type = "copper";
546			};
547		};
548
549		eth0: ethernet-4{
550			compatible = "hisilicon,hns-nic-v2";
551			ae-handle = <&dsaf0>;
552			port-idx-in-ae = <4>;
553			local-mac-address = [00 00 00 00 00 00];
554			status = "disabled";
555			dma-coherent;
556		};
557
558		eth1: ethernet-5{
559			compatible = "hisilicon,hns-nic-v2";
560			ae-handle = <&dsaf0>;
561			port-idx-in-ae = <5>;
562			local-mac-address = [00 00 00 00 00 00];
563			status = "disabled";
564			dma-coherent;
565		};
566
567		eth2: ethernet-0{
568			compatible = "hisilicon,hns-nic-v2";
569			ae-handle = <&dsaf0>;
570			port-idx-in-ae = <0>;
571			local-mac-address = [00 00 00 00 00 00];
572			status = "disabled";
573			dma-coherent;
574		};
575
576		eth3: ethernet-1{
577			compatible = "hisilicon,hns-nic-v2";
578			ae-handle = <&dsaf0>;
579			port-idx-in-ae = <1>;
580			local-mac-address = [00 00 00 00 00 00];
581			status = "disabled";
582			dma-coherent;
583		};
584
585		sas0: sas@c3000000 {
586			compatible = "hisilicon,hip06-sas-v2";
587			reg = <0 0xc3000000 0 0x10000>;
588			sas-addr = [50 01 88 20 16 00 00 00];
589			hisilicon,sas-syscon = <&dsa_subctrl>;
590			ctrl-reset-reg = <0xa60>;
591			ctrl-reset-sts-reg = <0x5a30>;
592			ctrl-clock-ena-reg = <0x338>;
593			clocks = <&refclk 0>;
594			queue-count = <16>;
595			phy-count = <8>;
596			dma-coherent;
597			interrupt-parent = <&mbigen_sas0>;
598			interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
599				     <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
600				     <75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
601				     <80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
602				     <85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
603				     <90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
604				     <95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
605				     <100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
606				     <105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
607				     <110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
608				     <115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
609				     <120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
610				     <125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
611				     <130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
612				     <135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
613				     <140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
614				     <145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
615				     <150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
616				     <155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
617				     <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
618				     <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
619				     <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
620				     <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
621				     <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
622				     <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
623				     <630 1>,<631 1>,<632 1>;
624			status = "disabled";
625		};
626
627		sas1: sas@a2000000 {
628			compatible = "hisilicon,hip06-sas-v2";
629			reg = <0 0xa2000000 0 0x10000>;
630			sas-addr = [50 01 88 20 16 00 00 00];
631			hisilicon,sas-syscon = <&pcie_subctl>;
632			hip06-sas-v2-quirk-amt;
633			ctrl-reset-reg = <0xa18>;
634			ctrl-reset-sts-reg = <0x5a0c>;
635			ctrl-clock-ena-reg = <0x318>;
636			clocks = <&refclk 0>;
637			queue-count = <16>;
638			phy-count = <8>;
639			dma-coherent;
640			interrupt-parent = <&mbigen_sas1>;
641			interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
642				     <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
643				     <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
644				     <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
645				     <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
646				     <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
647				     <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
648				     <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
649				     <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
650				     <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
651				     <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
652				     <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
653				     <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
654				     <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
655				     <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
656				     <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
657				     <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
658				     <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
659				     <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
660				     <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
661				     <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
662				     <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
663				     <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
664				     <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
665				     <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
666				     <605 1>,<606 1>,<607 1>;
667			status = "disabled";
668		};
669
670		sas2: sas@a3000000 {
671			compatible = "hisilicon,hip06-sas-v2";
672			reg = <0 0xa3000000 0 0x10000>;
673			sas-addr = [50 01 88 20 16 00 00 00];
674			hisilicon,sas-syscon = <&pcie_subctl>;
675			ctrl-reset-reg = <0xae0>;
676			ctrl-reset-sts-reg = <0x5a70>;
677			ctrl-clock-ena-reg = <0x3a8>;
678			clocks = <&refclk 0>;
679			queue-count = <16>;
680			phy-count = <9>;
681			dma-coherent;
682			interrupt-parent = <&mbigen_sas2>;
683			interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
684				     <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
685				     <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
686				     <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
687				     <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
688				     <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
689				     <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
690				     <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
691				     <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
692				     <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
693				     <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
694				     <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
695				     <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
696				     <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
697				     <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
698				     <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
699				     <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
700				     <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
701				     <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
702				     <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
703				     <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
704				     <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
705				     <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
706				     <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
707				     <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
708				     <637 1>,<638 1>,<639 1>;
709			status = "disabled";
710		};
711
712		pcie0: pcie@a0090000 {
713			compatible = "hisilicon,hip06-pcie-ecam";
714			reg = <0 0xb0000000 0 0x2000000>,
715			      <0 0xa0090000 0 0x10000>;
716			bus-range = <0  31>;
717			msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
718			msi-map-mask = <0xffff>;
719			#address-cells = <3>;
720			#size-cells = <2>;
721			device_type = "pci";
722			dma-coherent;
723			ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0
724				 0x5ff0000 0x01000000 0 0 0 0xb7ff0000
725				 0 0x10000>;
726			#interrupt-cells = <1>;
727			interrupt-map-mask = <0xf800 0 0 7>;
728			interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
729					0x0 0 0 2 &mbigen_pcie0 650 4
730					0x0 0 0 3 &mbigen_pcie0 650 4
731					0x0 0 0 4 &mbigen_pcie0 650 4>;
732			status = "disabled";
733		};
734
735	};
736
737};
738