1/**
2 * dts file for Hisilicon D02 Development Board
3 *
4 * Copyright (C) 2014,2015 Hisilicon Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15	compatible = "hisilicon,hip05-d02";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	psci {
21		compatible = "arm,psci-0.2";
22		method = "smc";
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu-map {
30			cluster0 {
31				core0 {
32					cpu = <&cpu0>;
33				};
34				core1 {
35					cpu = <&cpu1>;
36				};
37				core2 {
38					cpu = <&cpu2>;
39				};
40				core3 {
41					cpu = <&cpu3>;
42				};
43			};
44			cluster1 {
45				core0 {
46					cpu = <&cpu4>;
47				};
48				core1 {
49					cpu = <&cpu5>;
50				};
51				core2 {
52					cpu = <&cpu6>;
53				};
54				core3 {
55					cpu = <&cpu7>;
56				};
57			};
58			cluster2 {
59				core0 {
60					cpu = <&cpu8>;
61				};
62				core1 {
63					cpu = <&cpu9>;
64				};
65				core2 {
66					cpu = <&cpu10>;
67				};
68				core3 {
69					cpu = <&cpu11>;
70				};
71			};
72			cluster3 {
73				core0 {
74					cpu = <&cpu12>;
75				};
76				core1 {
77					cpu = <&cpu13>;
78				};
79				core2 {
80					cpu = <&cpu14>;
81				};
82				core3 {
83					cpu = <&cpu15>;
84				};
85			};
86		};
87
88		cpu0: cpu@20000 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a57", "arm,armv8";
91			reg = <0x20000>;
92			enable-method = "psci";
93			next-level-cache = <&cluster0_l2>;
94		};
95
96		cpu1: cpu@20001 {
97			device_type = "cpu";
98			compatible = "arm,cortex-a57", "arm,armv8";
99			reg = <0x20001>;
100			enable-method = "psci";
101			next-level-cache = <&cluster0_l2>;
102		};
103
104		cpu2: cpu@20002 {
105			device_type = "cpu";
106			compatible = "arm,cortex-a57", "arm,armv8";
107			reg = <0x20002>;
108			enable-method = "psci";
109			next-level-cache = <&cluster0_l2>;
110		};
111
112		cpu3: cpu@20003 {
113			device_type = "cpu";
114			compatible = "arm,cortex-a57", "arm,armv8";
115			reg = <0x20003>;
116			enable-method = "psci";
117			next-level-cache = <&cluster0_l2>;
118		};
119
120		cpu4: cpu@20100 {
121			device_type = "cpu";
122			compatible = "arm,cortex-a57", "arm,armv8";
123			reg = <0x20100>;
124			enable-method = "psci";
125			next-level-cache = <&cluster1_l2>;
126		};
127
128		cpu5: cpu@20101 {
129			device_type = "cpu";
130			compatible = "arm,cortex-a57", "arm,armv8";
131			reg = <0x20101>;
132			enable-method = "psci";
133			next-level-cache = <&cluster1_l2>;
134		};
135
136		cpu6: cpu@20102 {
137			device_type = "cpu";
138			compatible = "arm,cortex-a57", "arm,armv8";
139			reg = <0x20102>;
140			enable-method = "psci";
141			next-level-cache = <&cluster1_l2>;
142		};
143
144		cpu7: cpu@20103 {
145			device_type = "cpu";
146			compatible = "arm,cortex-a57", "arm,armv8";
147			reg = <0x20103>;
148			enable-method = "psci";
149			next-level-cache = <&cluster1_l2>;
150		};
151
152		cpu8: cpu@20200 {
153			device_type = "cpu";
154			compatible = "arm,cortex-a57", "arm,armv8";
155			reg = <0x20200>;
156			enable-method = "psci";
157			next-level-cache = <&cluster2_l2>;
158		};
159
160		cpu9: cpu@20201 {
161			device_type = "cpu";
162			compatible = "arm,cortex-a57", "arm,armv8";
163			reg = <0x20201>;
164			enable-method = "psci";
165			next-level-cache = <&cluster2_l2>;
166		};
167
168		cpu10: cpu@20202 {
169			device_type = "cpu";
170			compatible = "arm,cortex-a57", "arm,armv8";
171			reg = <0x20202>;
172			enable-method = "psci";
173			next-level-cache = <&cluster2_l2>;
174		};
175
176		cpu11: cpu@20203 {
177			device_type = "cpu";
178			compatible = "arm,cortex-a57", "arm,armv8";
179			reg = <0x20203>;
180			enable-method = "psci";
181			next-level-cache = <&cluster2_l2>;
182		};
183
184		cpu12: cpu@20300 {
185			device_type = "cpu";
186			compatible = "arm,cortex-a57", "arm,armv8";
187			reg = <0x20300>;
188			enable-method = "psci";
189			next-level-cache = <&cluster3_l2>;
190		};
191
192		cpu13: cpu@20301 {
193			device_type = "cpu";
194			compatible = "arm,cortex-a57", "arm,armv8";
195			reg = <0x20301>;
196			enable-method = "psci";
197			next-level-cache = <&cluster3_l2>;
198		};
199
200		cpu14: cpu@20302 {
201			device_type = "cpu";
202			compatible = "arm,cortex-a57", "arm,armv8";
203			reg = <0x20302>;
204			enable-method = "psci";
205			next-level-cache = <&cluster3_l2>;
206		};
207
208		cpu15: cpu@20303 {
209			device_type = "cpu";
210			compatible = "arm,cortex-a57", "arm,armv8";
211			reg = <0x20303>;
212			enable-method = "psci";
213			next-level-cache = <&cluster3_l2>;
214		};
215
216		cluster0_l2: l2-cache0 {
217			compatible = "cache";
218		};
219
220		cluster1_l2: l2-cache1 {
221			compatible = "cache";
222		};
223
224		cluster2_l2: l2-cache2 {
225			compatible = "cache";
226		};
227
228		cluster3_l2: l2-cache3 {
229			compatible = "cache";
230		};
231	};
232
233	gic: interrupt-controller@8d000000 {
234		compatible = "arm,gic-v3";
235                #interrupt-cells = <3>;
236                #address-cells = <2>;
237                #size-cells = <2>;
238                ranges;
239                interrupt-controller;
240                #redistributor-regions = <1>;
241                redistributor-stride = <0x0 0x30000>;
242		reg = <0x0 0x8d000000 0 0x10000>,	/* GICD */
243		      <0x0 0x8d100000 0 0x300000>,	/* GICR */
244		      <0x0 0xfe000000 0 0x10000>,	/* GICC */
245		      <0x0 0xfe010000 0 0x10000>,       /* GICH */
246		      <0x0 0xfe020000 0 0x10000>;       /* GICV */
247		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
248
249		its_peri: interrupt-controller@8c000000 {
250			compatible = "arm,gic-v3-its";
251			msi-controller;
252			#msi-cells = <1>;
253			reg = <0x0 0x8c000000 0x0 0x40000>;
254		};
255
256		its_m3: interrupt-controller@a3000000 {
257			compatible = "arm,gic-v3-its";
258			msi-controller;
259			#msi-cells = <1>;
260			reg = <0x0 0xa3000000 0x0 0x40000>;
261		};
262
263		its_pcie: interrupt-controller@b7000000 {
264			compatible = "arm,gic-v3-its";
265			msi-controller;
266			#msi-cells = <1>;
267			reg = <0x0 0xb7000000 0x0 0x40000>;
268		};
269
270		its_dsa: interrupt-controller@c6000000 {
271			compatible = "arm,gic-v3-its";
272			msi-controller;
273			#msi-cells = <1>;
274			reg = <0x0 0xc6000000 0x0 0x40000>;
275		};
276	};
277
278	timer {
279		compatible = "arm,armv8-timer";
280		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
281			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
282			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
283			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
284	};
285
286	pmu {
287		compatible = "arm,cortex-a57-pmu";
288		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
289	};
290
291	soc {
292		compatible = "simple-bus";
293		#address-cells = <2>;
294		#size-cells = <2>;
295		ranges;
296
297		refclk200mhz: refclk200mhz {
298			compatible = "fixed-clock";
299			#clock-cells = <0>;
300			clock-frequency = <200000000>;
301		};
302
303		uart0: uart@80300000 {
304			compatible = "snps,dw-apb-uart";
305			reg = <0x0 0x80300000 0x0 0x10000>;
306			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
307			clocks = <&refclk200mhz>;
308			clock-names = "apb_pclk";
309			reg-shift = <2>;
310			reg-io-width = <4>;
311			status = "disabled";
312		};
313
314		uart1: uart@80310000 {
315			compatible = "snps,dw-apb-uart";
316			reg = <0x0 0x80310000 0x0 0x10000>;
317			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
318			clocks = <&refclk200mhz>;
319			clock-names = "apb_pclk";
320			reg-shift = <2>;
321			reg-io-width = <4>;
322			status = "disabled";
323		};
324
325		lbc: localbus@80380000 {
326			compatible = "hisilicon,hisi-localbus", "simple-bus";
327			reg = <0x0 0x80380000 0x0 0x10000>;
328			status = "disabled";
329		};
330
331		peri_gpio0: gpio@802e0000 {
332			#address-cells = <1>;
333			#size-cells = <0>;
334			compatible = "snps,dw-apb-gpio";
335			reg = <0x0 0x802e0000 0x0 0x10000>;
336			status = "disabled";
337
338			porta: gpio-controller@0 {
339				compatible = "snps,dw-apb-gpio-port";
340				gpio-controller;
341				#gpio-cells = <2>;
342				snps,nr-gpios = <32>;
343				reg = <0>;
344				interrupt-controller;
345				#interrupt-cells = <2>;
346				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
347			};
348		};
349
350		peri_gpio1: gpio@802f0000 {
351			#address-cells = <1>;
352			#size-cells = <0>;
353			compatible = "snps,dw-apb-gpio";
354			reg = <0x0 0x802f0000 0x0 0x10000>;
355			status = "disabled";
356
357			portb: gpio-controller@0 {
358				compatible = "snps,dw-apb-gpio-port";
359				gpio-controller;
360				#gpio-cells = <2>;
361				snps,nr-gpios = <32>;
362				reg = <0>;
363				interrupt-controller;
364				#interrupt-cells = <2>;
365				interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
366			};
367		};
368	};
369};
370