1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Pinctrl dts file for HiSilicon HiKey970 development board
4 */
5
6#include <dt-bindings/pinctrl/hisi.h>
7
8/ {
9	soc {
10		range: gpio-range {
11			#pinctrl-single,gpio-range-cells = <3>;
12		};
13
14		pmx0: pinmux@e896c000 {
15			compatible = "pinctrl-single";
16			reg = <0x0 0xe896c000 0x0 0x72c>;
17			#pinctrl-cells = <1>;
18			#gpio-range-cells = <0x3>;
19			pinctrl-single,register-width = <0x20>;
20			pinctrl-single,function-mask = <0x7>;
21			/* pin base, nr pins & gpio function */
22			pinctrl-single,gpio-range = <&range 0 82 0>;
23
24			uart0_pmx_func: uart0_pmx_func {
25				pinctrl-single,pins = <
26					0x054 MUX_M2 /* UART0_RXD */
27					0x058 MUX_M2 /* UART0_TXD */
28				>;
29			};
30
31			uart2_pmx_func: uart2_pmx_func {
32				pinctrl-single,pins = <
33					0x700 MUX_M2 /* UART2_CTS_N */
34					0x704 MUX_M2 /* UART2_RTS_N */
35					0x708 MUX_M2 /* UART2_RXD */
36					0x70c MUX_M2 /* UART2_TXD */
37				>;
38			};
39
40			uart3_pmx_func: uart3_pmx_func {
41				pinctrl-single,pins = <
42					0x064 MUX_M1 /* UART3_CTS_N */
43					0x068 MUX_M1 /* UART3_RTS_N */
44					0x06c MUX_M1 /* UART3_RXD */
45					0x070 MUX_M1 /* UART3_TXD */
46				>;
47			};
48
49			uart4_pmx_func: uart4_pmx_func {
50				pinctrl-single,pins = <
51					0x074 MUX_M1 /* UART4_CTS_N */
52					0x078 MUX_M1 /* UART4_RTS_N */
53					0x07c MUX_M1 /* UART4_RXD */
54					0x080 MUX_M1 /* UART4_TXD */
55				>;
56			};
57
58			uart6_pmx_func: uart6_pmx_func {
59				pinctrl-single,pins = <
60					0x05c MUX_M1 /* UART6_RXD */
61					0x060 MUX_M1 /* UART6_TXD */
62				>;
63			};
64		};
65
66		pmx2: pinmux@e896c800 {
67			compatible = "pinconf-single";
68			reg = <0x0 0xe896c800 0x0 0x72c>;
69			#pinctrl-cells = <1>;
70			pinctrl-single,register-width = <0x20>;
71
72			uart0_cfg_func: uart0_cfg_func {
73				pinctrl-single,pins = <
74					0x058 0x0 /* UART0_RXD */
75					0x05c 0x0 /* UART0_TXD */
76				>;
77				pinctrl-single,bias-pulldown = <
78					PULL_DIS
79					PULL_DOWN
80					PULL_DIS
81					PULL_DOWN
82				>;
83				pinctrl-single,bias-pullup = <
84					PULL_DIS
85					PULL_UP
86					PULL_DIS
87					PULL_UP
88				>;
89				pinctrl-single,drive-strength = <
90					DRIVE7_04MA DRIVE6_MASK
91				>;
92			};
93
94			uart2_cfg_func: uart2_cfg_func {
95				pinctrl-single,pins = <
96					0x700 0x0 /* UART2_CTS_N */
97					0x704 0x0 /* UART2_RTS_N */
98					0x708 0x0 /* UART2_RXD */
99					0x70c 0x0 /* UART2_TXD */
100				>;
101				pinctrl-single,bias-pulldown = <
102					PULL_DIS
103					PULL_DOWN
104					PULL_DIS
105					PULL_DOWN
106				>;
107				pinctrl-single,bias-pullup = <
108					PULL_DIS
109					PULL_UP
110					PULL_DIS
111					PULL_UP
112				>;
113				pinctrl-single,drive-strength = <
114					DRIVE7_04MA DRIVE6_MASK
115				>;
116			};
117
118			uart3_cfg_func: uart3_cfg_func {
119				pinctrl-single,pins = <
120					0x068 0x0 /* UART3_CTS_N */
121					0x06c 0x0 /* UART3_RTS_N */
122					0x070 0x0 /* UART3_RXD */
123					0x074 0x0 /* UART3_TXD */
124				>;
125				pinctrl-single,bias-pulldown = <
126					PULL_DIS
127					PULL_DOWN
128					PULL_DIS
129					PULL_DOWN
130				>;
131				pinctrl-single,bias-pullup = <
132					PULL_DIS
133					PULL_UP
134					PULL_DIS
135					PULL_UP
136				>;
137				pinctrl-single,drive-strength = <
138					DRIVE7_04MA DRIVE6_MASK
139				>;
140			};
141
142			uart4_cfg_func: uart4_cfg_func {
143				pinctrl-single,pins = <
144					0x078 0x0 /* UART4_CTS_N */
145					0x07c 0x0 /* UART4_RTS_N */
146					0x080 0x0 /* UART4_RXD */
147					0x084 0x0 /* UART4_TXD */
148				>;
149				pinctrl-single,bias-pulldown = <
150					PULL_DIS
151					PULL_DOWN
152					PULL_DIS
153					PULL_DOWN
154				>;
155				pinctrl-single,bias-pullup = <
156					PULL_DIS
157					PULL_UP
158					PULL_DIS
159					PULL_UP
160				>;
161				pinctrl-single,drive-strength = <
162					DRIVE7_04MA DRIVE6_MASK
163				>;
164			};
165
166			uart6_cfg_func: uart6_cfg_func {
167				pinctrl-single,pins = <
168					0x060 0x0 /* UART6_RXD */
169					0x064 0x0 /* UART6_TXD */
170				>;
171				pinctrl-single,bias-pulldown = <
172					PULL_DIS
173					PULL_DOWN
174					PULL_DIS
175					PULL_DOWN
176				>;
177				pinctrl-single,bias-pullup = <
178					PULL_DIS
179					PULL_UP
180					PULL_DIS
181					PULL_UP
182				>;
183				pinctrl-single,drive-strength = <
184					DRIVE7_02MA DRIVE6_MASK
185				>;
186			};
187		};
188
189		pmx5: pinmux@fc182000 {
190			compatible = "pinctrl-single";
191			reg = <0x0 0xfc182000 0x0 0x028>;
192			#gpio-range-cells = <3>;
193			#pinctrl-cells = <1>;
194			pinctrl-single,register-width = <0x20>;
195			pinctrl-single,function-mask = <0x7>;
196			/* pin base, nr pins & gpio function */
197			pinctrl-single,gpio-range = <&range 0 10 0>;
198
199		};
200
201		pmx6: pinmux@fc182800 {
202			compatible = "pinconf-single";
203			reg = <0x0 0xfc182800 0x0 0x028>;
204			#pinctrl-cells = <1>;
205			pinctrl-single,register-width = <0x20>;
206		};
207
208		pmx7: pinmux@ff37e000 {
209			compatible = "pinctrl-single";
210			reg = <0x0 0xff37e000 0x0 0x030>;
211			#gpio-range-cells = <3>;
212			#pinctrl-cells = <1>;
213			pinctrl-single,register-width = <0x20>;
214			pinctrl-single,function-mask = <7>;
215			/* pin base, nr pins & gpio function */
216			pinctrl-single,gpio-range = <&range 0 12 0>;
217		};
218
219		pmx8: pinmux@ff37e800 {
220			compatible = "pinconf-single";
221			reg = <0x0 0xff37e800 0x0 0x030>;
222			#pinctrl-cells = <1>;
223			pinctrl-single,register-width = <0x20>;
224		};
225
226		pmx1: pinmux@fff11000 {
227			compatible = "pinctrl-single";
228			reg = <0x0 0xfff11000 0x0 0x73c>;
229			#gpio-range-cells = <0x3>;
230			#pinctrl-cells = <1>;
231			pinctrl-single,register-width = <0x20>;
232			pinctrl-single,function-mask = <0x7>;
233			/* pin base, nr pins & gpio function */
234			pinctrl-single,gpio-range = <&range 0 46 0>;
235		};
236
237		pmx16: pinmux@fff11800 {
238			compatible = "pinconf-single";
239			reg = <0x0 0xfff11800 0x0 0x73c>;
240			#pinctrl-cells = <1>;
241			pinctrl-single,register-width = <0x20>;
242		};
243	};
244};
245