1/*
2 * pinctrl dts fils for Hislicon HiKey development board
3 *
4 */
5#include <dt-bindings/pinctrl/hisi.h>
6
7/ {
8	soc {
9		pmx0: pinmux@f7010000 {
10			pinctrl-names = "default";
11			pinctrl-0 = <
12				&boot_sel_pmx_func
13				&hkadc_ssi_pmx_func
14				&codec_clk_pmx_func
15				&pwm_in_pmx_func
16				&bl_pwm_pmx_func
17				>;
18
19			boot_sel_pmx_func: boot_sel_pmx_func {
20				pinctrl-single,pins = <
21					0x0    MUX_M0	/* BOOT_SEL     (IOMG000) */
22				>;
23			};
24
25			emmc_pmx_func: emmc_pmx_func {
26				pinctrl-single,pins = <
27					0x100  MUX_M0	/* EMMC_CLK     (IOMG064) */
28					0x104  MUX_M0	/* EMMC_CMD     (IOMG065) */
29					0x108  MUX_M0	/* EMMC_DATA0   (IOMG066) */
30					0x10c  MUX_M0	/* EMMC_DATA1   (IOMG067) */
31					0x110  MUX_M0	/* EMMC_DATA2   (IOMG068) */
32					0x114  MUX_M0	/* EMMC_DATA3   (IOMG069) */
33					0x118  MUX_M0	/* EMMC_DATA4   (IOMG070) */
34					0x11c  MUX_M0	/* EMMC_DATA5   (IOMG071) */
35					0x120  MUX_M0	/* EMMC_DATA6   (IOMG072) */
36					0x124  MUX_M0	/* EMMC_DATA7   (IOMG073) */
37				>;
38			};
39
40			sd_pmx_func: sd_pmx_func {
41				pinctrl-single,pins = <
42					0xc    MUX_M0	/* SD_CLK       (IOMG003) */
43					0x10   MUX_M0	/* SD_CMD       (IOMG004) */
44					0x14   MUX_M0	/* SD_DATA0     (IOMG005) */
45					0x18   MUX_M0	/* SD_DATA1     (IOMG006) */
46					0x1c   MUX_M0	/* SD_DATA2     (IOMG007) */
47					0x20   MUX_M0	/* SD_DATA3     (IOMG008) */
48				>;
49			};
50			sd_pmx_idle: sd_pmx_idle {
51				pinctrl-single,pins = <
52					0xc    MUX_M1	/* SD_CLK       (IOMG003) */
53					0x10   MUX_M1	/* SD_CMD       (IOMG004) */
54					0x14   MUX_M1	/* SD_DATA0     (IOMG005) */
55					0x18   MUX_M1	/* SD_DATA1     (IOMG006) */
56					0x1c   MUX_M1	/* SD_DATA2     (IOMG007) */
57					0x20   MUX_M1	/* SD_DATA3     (IOMG008) */
58				>;
59			};
60
61			sdio_pmx_func: sdio_pmx_func {
62				pinctrl-single,pins = <
63					0x128  MUX_M0	/* SDIO_CLK     (IOMG074) */
64					0x12c  MUX_M0	/* SDIO_CMD     (IOMG075) */
65					0x130  MUX_M0	/* SDIO_DATA0   (IOMG076) */
66					0x134  MUX_M0	/* SDIO_DATA1   (IOMG077) */
67					0x138  MUX_M0	/* SDIO_DATA2   (IOMG078) */
68					0x13c  MUX_M0	/* SDIO_DATA3   (IOMG079) */
69				>;
70			};
71			sdio_pmx_idle: sdio_pmx_idle {
72				pinctrl-single,pins = <
73					0x128  MUX_M1	/* SDIO_CLK     (IOMG074) */
74					0x12c  MUX_M1	/* SDIO_CMD     (IOMG075) */
75					0x130  MUX_M1	/* SDIO_DATA0   (IOMG076) */
76					0x134  MUX_M1	/* SDIO_DATA1   (IOMG077) */
77					0x138  MUX_M1	/* SDIO_DATA2   (IOMG078) */
78					0x13c  MUX_M1	/* SDIO_DATA3   (IOMG079) */
79				>;
80			};
81
82			isp_pmx_func: isp_pmx_func {
83				pinctrl-single,pins = <
84					0x24   MUX_M0	/* ISP_PWDN0    (IOMG009) */
85					0x28   MUX_M0	/* ISP_PWDN1    (IOMG010) */
86					0x2c   MUX_M0	/* ISP_PWDN2    (IOMG011) */
87					0x30   MUX_M1	/* ISP_SHUTTER0 (IOMG012) */
88					0x34   MUX_M1	/* ISP_SHUTTER1 (IOMG013) */
89					0x38   MUX_M1	/* ISP_PWM      (IOMG014) */
90					0x3c   MUX_M0	/* ISP_CCLK0    (IOMG015) */
91					0x40   MUX_M0	/* ISP_CCLK1    (IOMG016) */
92					0x44   MUX_M0	/* ISP_RESETB0  (IOMG017) */
93					0x48   MUX_M0	/* ISP_RESETB1  (IOMG018) */
94					0x4c   MUX_M1	/* ISP_STROBE0  (IOMG019) */
95					0x50   MUX_M1	/* ISP_STROBE1  (IOMG020) */
96					0x54   MUX_M0	/* ISP_SDA0     (IOMG021) */
97					0x58   MUX_M0	/* ISP_SCL0     (IOMG022) */
98					0x5c   MUX_M0	/* ISP_SDA1     (IOMG023) */
99					0x60   MUX_M0	/* ISP_SCL1     (IOMG024) */
100				>;
101			};
102
103			hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
104				pinctrl-single,pins = <
105					0x68   MUX_M0	/* HKADC_SSI    (IOMG026) */
106				>;
107			};
108
109			codec_clk_pmx_func: codec_clk_pmx_func {
110				pinctrl-single,pins = <
111					0x6c   MUX_M0	/* CODEC_CLK    (IOMG027) */
112				>;
113			};
114
115			codec_pmx_func: codec_pmx_func {
116				pinctrl-single,pins = <
117					0x70   MUX_M1	/* DMIC_CLK     (IOMG028) */
118					0x74   MUX_M0	/* CODEC_SYNC   (IOMG029) */
119					0x78   MUX_M0	/* CODEC_DI     (IOMG030) */
120					0x7c   MUX_M0	/* CODEC_DO     (IOMG031) */
121				>;
122			};
123
124			fm_pmx_func: fm_pmx_func {
125				pinctrl-single,pins = <
126					0x80   MUX_M1	/* FM_XCLK      (IOMG032) */
127					0x84   MUX_M1	/* FM_XFS       (IOMG033) */
128					0x88   MUX_M1	/* FM_DI        (IOMG034) */
129					0x8c   MUX_M1	/* FM_DO        (IOMG035) */
130				>;
131			};
132
133			bt_pmx_func: bt_pmx_func {
134				pinctrl-single,pins = <
135					0x90   MUX_M0	/* BT_XCLK      (IOMG036) */
136					0x94   MUX_M0	/* BT_XFS       (IOMG037) */
137					0x98   MUX_M0	/* BT_DI        (IOMG038) */
138					0x9c   MUX_M0	/* BT_DO        (IOMG039) */
139				>;
140			};
141
142			pwm_in_pmx_func: pwm_in_pmx_func {
143				pinctrl-single,pins = <
144					0xb8   MUX_M1	/* PWM_IN       (IOMG046) */
145				>;
146			};
147
148			bl_pwm_pmx_func: bl_pwm_pmx_func {
149				pinctrl-single,pins = <
150					0xbc   MUX_M1	/* BL_PWM       (IOMG047) */
151				>;
152			};
153
154			uart0_pmx_func: uart0_pmx_func {
155				pinctrl-single,pins = <
156					0xc0   MUX_M0	/* UART0_RXD    (IOMG048) */
157					0xc4   MUX_M0	/* UART0_TXD    (IOMG049) */
158				>;
159			};
160
161			uart1_pmx_func: uart1_pmx_func {
162				pinctrl-single,pins = <
163					0xc8   MUX_M0	/* UART1_CTS_N  (IOMG050) */
164					0xcc   MUX_M0	/* UART1_RTS_N  (IOMG051) */
165					0xd0   MUX_M0	/* UART1_RXD    (IOMG052) */
166					0xd4   MUX_M0	/* UART1_TXD    (IOMG053) */
167				>;
168			};
169
170			uart2_pmx_func: uart2_pmx_func {
171				pinctrl-single,pins = <
172					0xd8   MUX_M0	/* UART2_CTS_N  (IOMG054) */
173					0xdc   MUX_M0	/* UART2_RTS_N  (IOMG055) */
174					0xe0   MUX_M0	/* UART2_RXD    (IOMG056) */
175					0xe4   MUX_M0	/* UART2_TXD    (IOMG057) */
176				>;
177			};
178
179			uart3_pmx_func: uart3_pmx_func {
180				pinctrl-single,pins = <
181					0x180  MUX_M1	/* UART3_CTS_N  (IOMG096) */
182					0x184  MUX_M1	/* UART3_RTS_N  (IOMG097) */
183					0x188  MUX_M1	/* UART3_RXD    (IOMG098) */
184					0x18c  MUX_M1	/* UART3_TXD    (IOMG099) */
185				>;
186			};
187
188			uart4_pmx_func: uart4_pmx_func {
189				pinctrl-single,pins = <
190					0x1d0  MUX_M1	/* UART4_CTS_N  (IOMG116) */
191					0x1d4  MUX_M1	/* UART4_RTS_N  (IOMG117) */
192					0x1d8  MUX_M1	/* UART4_RXD    (IOMG118) */
193					0x1dc  MUX_M1	/* UART4_TXD    (IOMG119) */
194				>;
195			};
196
197			uart5_pmx_func: uart5_pmx_func {
198				pinctrl-single,pins = <
199					0x1c8  MUX_M1	/* UART5_RXD    (IOMG114) */
200					0x1cc  MUX_M1	/* UART5_TXD    (IOMG115) */
201				>;
202			};
203
204			i2c0_pmx_func: i2c0_pmx_func {
205				pinctrl-single,pins = <
206					0xe8   MUX_M0	/* I2C0_SCL     (IOMG058) */
207					0xec   MUX_M0	/* I2C0_SDA     (IOMG059) */
208				>;
209			};
210
211			i2c1_pmx_func: i2c1_pmx_func {
212				pinctrl-single,pins = <
213					0xf0   MUX_M0	/* I2C1_SCL     (IOMG060) */
214					0xf4   MUX_M0	/* I2C1_SDA     (IOMG061) */
215				>;
216			};
217
218			i2c2_pmx_func: i2c2_pmx_func {
219				pinctrl-single,pins = <
220					0xf8   MUX_M0	/* I2C2_SCL     (IOMG062) */
221					0xfc   MUX_M0	/* I2C2_SDA     (IOMG063) */
222				>;
223			};
224
225			spi0_pmx_func: spi0_pmx_func {
226				pinctrl-single,pins = <
227					0x1a0  MUX_M1   /* SPI0_DI      (IOMG104) */
228					0x1a4  MUX_M1	/* SPI0_DO	(IOMG105) */
229					0x1a8  MUX_M1	/* SPI0_CS_N	(IOMG106) */
230					0x1ac  MUX_M1	/* SPI0_CLK	(IOMG107) */
231				>;
232			};
233		};
234
235		pmx1: pinmux@f7010800 {
236
237			pinctrl-names = "default";
238			pinctrl-0 = <
239				&boot_sel_cfg_func
240				&hkadc_ssi_cfg_func
241				&codec_clk_cfg_func
242				&pwm_in_cfg_func
243				&bl_pwm_cfg_func
244				>;
245
246			boot_sel_cfg_func: boot_sel_cfg_func {
247				pinctrl-single,pins = <
248					0x0    0x0	/* BOOT_SEL     (IOCFG000) */
249				>;
250				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
251				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
252				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
253			};
254
255			hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
256				pinctrl-single,pins = <
257					0x6c   0x0	/* HKADC_SSI    (IOCFG027) */
258				>;
259				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
260				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
261				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
262			};
263
264			emmc_clk_cfg_func: emmc_clk_cfg_func {
265				pinctrl-single,pins = <
266					0x104  0x0	/* EMMC_CLK     (IOCFG065) */
267				>;
268				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
269				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
270				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
271			};
272
273			emmc_cfg_func: emmc_cfg_func {
274				pinctrl-single,pins = <
275					0x108  0x0	/* EMMC_CMD     (IOCFG066) */
276					0x10c  0x0	/* EMMC_DATA0   (IOCFG067) */
277					0x110  0x0	/* EMMC_DATA1   (IOCFG068) */
278					0x114  0x0	/* EMMC_DATA2   (IOCFG069) */
279					0x118  0x0	/* EMMC_DATA3   (IOCFG070) */
280					0x11c  0x0	/* EMMC_DATA4   (IOCFG071) */
281					0x120  0x0	/* EMMC_DATA5   (IOCFG072) */
282					0x124  0x0	/* EMMC_DATA6   (IOCFG073) */
283					0x128  0x0	/* EMMC_DATA7   (IOCFG074) */
284				>;
285				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
286				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
287				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
288			};
289
290			emmc_rst_cfg_func: emmc_rst_cfg_func {
291				pinctrl-single,pins = <
292					0x12c  0x0	/* EMMC_RST_N   (IOCFG075) */
293				>;
294				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
295				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
296				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
297			};
298
299			sd_clk_cfg_func: sd_clk_cfg_func {
300				pinctrl-single,pins = <
301					0xc    0x0	/* SD_CLK       (IOCFG003) */
302				>;
303				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
304				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
305				pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
306			};
307			sd_clk_cfg_idle: sd_clk_cfg_idle {
308				pinctrl-single,pins = <
309					0xc    0x0	/* SD_CLK       (IOCFG003) */
310				>;
311				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
312				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
313				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
314			};
315
316			sd_cfg_func: sd_cfg_func {
317				pinctrl-single,pins = <
318					0x10   0x0	/* SD_CMD       (IOCFG004) */
319					0x14   0x0	/* SD_DATA0     (IOCFG005) */
320					0x18   0x0	/* SD_DATA1     (IOCFG006) */
321					0x1c   0x0	/* SD_DATA2     (IOCFG007) */
322					0x20   0x0	/* SD_DATA3     (IOCFG008) */
323				>;
324				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
325				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
326				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
327			};
328			sd_cfg_idle: sd_cfg_idle {
329				pinctrl-single,pins = <
330					0x10   0x0	/* SD_CMD       (IOCFG004) */
331					0x14   0x0	/* SD_DATA0     (IOCFG005) */
332					0x18   0x0	/* SD_DATA1     (IOCFG006) */
333					0x1c   0x0	/* SD_DATA2     (IOCFG007) */
334					0x20   0x0	/* SD_DATA3     (IOCFG008) */
335				>;
336				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
337				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
338				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
339			};
340
341			sdio_clk_cfg_func: sdio_clk_cfg_func {
342				pinctrl-single,pins = <
343					0x134  0x0	/* SDIO_CLK     (IOCFG077) */
344				>;
345				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
346				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
347				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
348			};
349			sdio_clk_cfg_idle: sdio_clk_cfg_idle {
350				pinctrl-single,pins = <
351					0x134  0x0	/* SDIO_CLK     (IOCFG077) */
352				>;
353				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
354				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
355				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
356			};
357
358			sdio_cfg_func: sdio_cfg_func {
359				pinctrl-single,pins = <
360					0x138  0x0	/* SDIO_CMD     (IOCFG078) */
361					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */
362					0x140  0x0	/* SDIO_DATA1   (IOCFG080) */
363					0x144  0x0	/* SDIO_DATA2   (IOCFG081) */
364					0x148  0x0	/* SDIO_DATA3   (IOCFG082) */
365				>;
366				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
367				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
368				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
369			};
370			sdio_cfg_idle: sdio_cfg_idle {
371				pinctrl-single,pins = <
372					0x138  0x0	/* SDIO_CMD     (IOCFG078) */
373					0x13c  0x0	/* SDIO_DATA0   (IOCFG079) */
374					0x140  0x0	/* SDIO_DATA1   (IOCFG080) */
375					0x144  0x0	/* SDIO_DATA2   (IOCFG081) */
376					0x148  0x0	/* SDIO_DATA3   (IOCFG082) */
377				>;
378				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
379				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
380				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
381			};
382
383			isp_cfg_func1: isp_cfg_func1 {
384				pinctrl-single,pins = <
385					0x28   0x0	/* ISP_PWDN0    (IOCFG010) */
386					0x2c   0x0	/* ISP_PWDN1    (IOCFG011) */
387					0x30   0x0	/* ISP_PWDN2    (IOCFG012) */
388					0x34   0x0	/* ISP_SHUTTER0 (IOCFG013) */
389					0x38   0x0	/* ISP_SHUTTER1 (IOCFG014) */
390					0x3c   0x0	/* ISP_PWM      (IOCFG015) */
391					0x40   0x0	/* ISP_CCLK0    (IOCFG016) */
392					0x44   0x0	/* ISP_CCLK1    (IOCFG017) */
393					0x48   0x0	/* ISP_RESETB0  (IOCFG018) */
394					0x4c   0x0	/* ISP_RESETB1  (IOCFG019) */
395					0x50   0x0	/* ISP_STROBE0  (IOCFG020) */
396					0x58   0x0	/* ISP_SDA0     (IOCFG022) */
397					0x5c   0x0	/* ISP_SCL0     (IOCFG023) */
398					0x60   0x0	/* ISP_SDA1     (IOCFG024) */
399					0x64   0x0	/* ISP_SCL1     (IOCFG025) */
400				>;
401				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
402				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
403				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
404			};
405			isp_cfg_idle1: isp_cfg_idle1 {
406				pinctrl-single,pins = <
407					0x34   0x0	/* ISP_SHUTTER0 (IOCFG013) */
408					0x38   0x0	/* ISP_SHUTTER1 (IOCFG014) */
409				>;
410				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
411				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
412				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
413			};
414
415			isp_cfg_func2: isp_cfg_func2 {
416				pinctrl-single,pins = <
417					0x54   0x0	/* ISP_STROBE1  (IOCFG021) */
418				>;
419				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
420				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
421				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
422			};
423
424			codec_clk_cfg_func: codec_clk_cfg_func {
425				pinctrl-single,pins = <
426					0x70   0x0	/* CODEC_CLK    (IOCFG028) */
427				>;
428				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
429				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
430				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
431			};
432			codec_clk_cfg_idle: codec_clk_cfg_idle {
433				pinctrl-single,pins = <
434					0x70   0x0	/* CODEC_CLK    (IOCFG028) */
435				>;
436				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
437				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
438				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
439			};
440
441			codec_cfg_func1: codec_cfg_func1 {
442				pinctrl-single,pins = <
443					0x74   0x0	/* DMIC_CLK     (IOCFG029) */
444				>;
445				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
446				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
447				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
448			};
449
450			codec_cfg_func2: codec_cfg_func2 {
451				pinctrl-single,pins = <
452					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */
453					0x7c   0x0	/* CODEC_DI     (IOCFG031) */
454					0x80   0x0	/* CODEC_DO     (IOCFG032) */
455				>;
456				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
457				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
458				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
459			};
460			codec_cfg_idle2: codec_cfg_idle2 {
461				pinctrl-single,pins = <
462					0x78   0x0	/* CODEC_SYNC   (IOCFG030) */
463					0x7c   0x0	/* CODEC_DI     (IOCFG031) */
464					0x80   0x0	/* CODEC_DO     (IOCFG032) */
465				>;
466				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
467				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
468				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
469			};
470
471			fm_cfg_func: fm_cfg_func {
472				pinctrl-single,pins = <
473					0x84   0x0	/* FM_XCLK      (IOCFG033) */
474					0x88   0x0	/* FM_XFS       (IOCFG034) */
475					0x8c   0x0	/* FM_DI        (IOCFG035) */
476					0x90   0x0	/* FM_DO        (IOCFG036) */
477				>;
478				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
479				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
480				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
481			};
482
483			bt_cfg_func: bt_cfg_func {
484				pinctrl-single,pins = <
485					0x94   0x0	/* BT_XCLK      (IOCFG037) */
486					0x98   0x0	/* BT_XFS       (IOCFG038) */
487					0x9c   0x0	/* BT_DI        (IOCFG039) */
488					0xa0   0x0	/* BT_DO        (IOCFG040) */
489				>;
490				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
491				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
492				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
493			};
494			bt_cfg_idle: bt_cfg_idle {
495				pinctrl-single,pins = <
496					0x94   0x0	/* BT_XCLK      (IOCFG037) */
497					0x98   0x0	/* BT_XFS       (IOCFG038) */
498					0x9c   0x0	/* BT_DI        (IOCFG039) */
499					0xa0   0x0	/* BT_DO        (IOCFG040) */
500				>;
501				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
502				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
503				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
504			};
505
506			pwm_in_cfg_func: pwm_in_cfg_func {
507				pinctrl-single,pins = <
508					0xbc   0x0	/* PWM_IN       (IOCFG047) */
509				>;
510				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
511				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
512				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
513			};
514
515			bl_pwm_cfg_func: bl_pwm_cfg_func {
516				pinctrl-single,pins = <
517					0xc0   0x0	/* BL_PWM       (IOCFG048) */
518				>;
519				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
520				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
521				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
522			};
523
524			uart0_cfg_func1: uart0_cfg_func1 {
525				pinctrl-single,pins = <
526					0xc4   0x0	/* UART0_RXD    (IOCFG049) */
527				>;
528				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
529				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
530				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
531			};
532
533			uart0_cfg_func2: uart0_cfg_func2 {
534				pinctrl-single,pins = <
535					0xc8   0x0	/* UART0_TXD    (IOCFG050) */
536				>;
537				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
538				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
539				pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
540			};
541
542			uart1_cfg_func1: uart1_cfg_func1 {
543				pinctrl-single,pins = <
544					0xcc   0x0	/* UART1_CTS_N  (IOCFG051) */
545					0xd4   0x0	/* UART1_RXD    (IOCFG053) */
546				>;
547				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
548				pinctrl-single,bias-pullup    = <PULL_UP   PULL_UP   PULL_DIS  PULL_UP>;
549				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
550			};
551
552			uart1_cfg_func2: uart1_cfg_func2 {
553				pinctrl-single,pins = <
554					0xd0   0x0	/* UART1_RTS_N  (IOCFG052) */
555					0xd8   0x0	/* UART1_TXD    (IOCFG054) */
556				>;
557				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
558				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
559				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
560			};
561
562			uart2_cfg_func: uart2_cfg_func {
563				pinctrl-single,pins = <
564					0xdc   0x0	/* UART2_CTS_N  (IOCFG055) */
565					0xe0   0x0	/* UART2_RTS_N  (IOCFG056) */
566					0xe4   0x0	/* UART2_RXD    (IOCFG057) */
567					0xe8   0x0	/* UART2_TXD    (IOCFG058) */
568				>;
569				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
570				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
571				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
572			};
573
574			uart3_cfg_func: uart3_cfg_func {
575				pinctrl-single,pins = <
576					0x190  0x0	/* UART3_CTS_N  (IOCFG100) */
577					0x194  0x0	/* UART3_RTS_N  (IOCFG101) */
578					0x198  0x0	/* UART3_RXD    (IOCFG102) */
579					0x19c  0x0	/* UART3_TXD    (IOCFG103) */
580				>;
581				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
582				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
583				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
584			};
585
586			uart4_cfg_func: uart4_cfg_func {
587				pinctrl-single,pins = <
588					0x1e0  0x0	/* UART4_CTS_N  (IOCFG120) */
589					0x1e4  0x0	/* UART4_RTS_N  (IOCFG121) */
590					0x1e8  0x0	/* UART4_RXD    (IOCFG122) */
591					0x1ec  0x0	/* UART4_TXD    (IOCFG123) */
592				>;
593				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
594				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
595				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
596			};
597
598			uart5_cfg_func: uart5_cfg_func {
599				pinctrl-single,pins = <
600					0x1d8  0x0	/* UART4_RXD    (IOCFG118) */
601					0x1dc  0x0	/* UART4_TXD    (IOCFG119) */
602				>;
603				pinctrl-single,bias-pulldown  = <PULL_DOWN PULL_DOWN PULL_DIS  PULL_DOWN>;
604				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
605				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
606			};
607
608			i2c0_cfg_func: i2c0_cfg_func {
609				pinctrl-single,pins = <
610					0xec   0x0	/* I2C0_SCL     (IOCFG059) */
611					0xf0   0x0	/* I2C0_SDA     (IOCFG060) */
612				>;
613				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
614				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
615				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
616			};
617
618			i2c1_cfg_func: i2c1_cfg_func {
619				pinctrl-single,pins = <
620					0xf4   0x0	/* I2C1_SCL     (IOCFG061) */
621					0xf8   0x0	/* I2C1_SDA     (IOCFG062) */
622				>;
623				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
624				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
625				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
626			};
627
628			i2c2_cfg_func: i2c2_cfg_func {
629				pinctrl-single,pins = <
630					0xfc   0x0	/* I2C2_SCL     (IOCFG063) */
631					0x100  0x0	/* I2C2_SDA     (IOCFG064) */
632				>;
633				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
634				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
635				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
636			};
637
638			spi0_cfg_func: spi0_cfg_func {
639				pinctrl-single,pins = <
640					0x1b0  0x0	/* SPI0_DI	(IOCFG108) */
641					0x1b4  0x0	/* SPI0_DO	(IOCFG109) */
642					0x1b8  0x0	/* SPI0_CS_N	(IOCFG110) */
643					0x1bc  0x0	/* SPI0_CLK	(IOCFG111) */
644				>;
645				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS PULL_DOWN>;
646				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS PULL_UP>;
647				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
648			};
649		};
650
651		pmx2: pinmux@f8001800 {
652
653			pinctrl-names = "default";
654			pinctrl-0 = <
655				&rstout_n_cfg_func
656				>;
657
658			rstout_n_cfg_func: rstout_n_cfg_func {
659				pinctrl-single,pins = <
660					0x0    0x0	/* RSTOUT_N     (IOCFG000) */
661				>;
662				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
663				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
664				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
665			};
666
667			pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
668				pinctrl-single,pins = <
669					0x4    0x0	/* PMU_PERI_EN  (IOCFG001) */
670				>;
671				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
672				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
673				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
674			};
675
676			sysclk0_en_cfg_func: sysclk0_en_cfg_func {
677				pinctrl-single,pins = <
678					0x8    0x0	/* SYSCLK0_EN   (IOCFG002) */
679				>;
680				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
681				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
682				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
683			};
684
685			jtag_tdo_cfg_func: jtag_tdo_cfg_func {
686				pinctrl-single,pins = <
687					0xc    0x0	/* JTAG_TDO     (IOCFG003) */
688				>;
689				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
690				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
691				pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
692			};
693
694			rf_reset_cfg_func: rf_reset_cfg_func {
695				pinctrl-single,pins = <
696					0x70   0x0	/* RF_RESET0    (IOCFG028) */
697					0x74   0x0	/* RF_RESET1    (IOCFG029) */
698				>;
699				pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
700				pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
701				pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
702			};
703		};
704	};
705};
706