1/* 2 * dts file for Hisilicon Hi6220 SoC 3 * 4 * Copyright (C) 2015, Hisilicon Ltd. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/hi6220-clock.h> 9#include <dt-bindings/pinctrl/hisi.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 compatible = "hisilicon,hi6220"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 psci { 19 compatible = "arm,psci-0.2"; 20 method = "smc"; 21 }; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 cpu-map { 28 cluster0 { 29 core0 { 30 cpu = <&cpu0>; 31 }; 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 core2 { 36 cpu = <&cpu2>; 37 }; 38 core3 { 39 cpu = <&cpu3>; 40 }; 41 }; 42 cluster1 { 43 core0 { 44 cpu = <&cpu4>; 45 }; 46 core1 { 47 cpu = <&cpu5>; 48 }; 49 core2 { 50 cpu = <&cpu6>; 51 }; 52 core3 { 53 cpu = <&cpu7>; 54 }; 55 }; 56 }; 57 58 idle-states { 59 entry-method = "psci"; 60 61 CPU_SLEEP: cpu-sleep { 62 compatible = "arm,idle-state"; 63 local-timer-stop; 64 arm,psci-suspend-param = <0x0010000>; 65 entry-latency-us = <700>; 66 exit-latency-us = <250>; 67 min-residency-us = <1000>; 68 }; 69 70 CLUSTER_SLEEP: cluster-sleep { 71 compatible = "arm,idle-state"; 72 local-timer-stop; 73 arm,psci-suspend-param = <0x1010000>; 74 entry-latency-us = <1000>; 75 exit-latency-us = <700>; 76 min-residency-us = <2700>; 77 wakeup-latency-us = <1500>; 78 }; 79 }; 80 81 cpu0: cpu@0 { 82 compatible = "arm,cortex-a53", "arm,armv8"; 83 device_type = "cpu"; 84 reg = <0x0 0x0>; 85 enable-method = "psci"; 86 next-level-cache = <&CLUSTER0_L2>; 87 clocks = <&stub_clock 0>; 88 operating-points-v2 = <&cpu_opp_table>; 89 cooling-min-level = <4>; 90 cooling-max-level = <0>; 91 #cooling-cells = <2>; /* min followed by max */ 92 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 93 dynamic-power-coefficient = <311>; 94 }; 95 96 cpu1: cpu@1 { 97 compatible = "arm,cortex-a53", "arm,armv8"; 98 device_type = "cpu"; 99 reg = <0x0 0x1>; 100 enable-method = "psci"; 101 next-level-cache = <&CLUSTER0_L2>; 102 operating-points-v2 = <&cpu_opp_table>; 103 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 104 }; 105 106 cpu2: cpu@2 { 107 compatible = "arm,cortex-a53", "arm,armv8"; 108 device_type = "cpu"; 109 reg = <0x0 0x2>; 110 enable-method = "psci"; 111 next-level-cache = <&CLUSTER0_L2>; 112 operating-points-v2 = <&cpu_opp_table>; 113 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 114 }; 115 116 cpu3: cpu@3 { 117 compatible = "arm,cortex-a53", "arm,armv8"; 118 device_type = "cpu"; 119 reg = <0x0 0x3>; 120 enable-method = "psci"; 121 next-level-cache = <&CLUSTER0_L2>; 122 operating-points-v2 = <&cpu_opp_table>; 123 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 124 }; 125 126 cpu4: cpu@100 { 127 compatible = "arm,cortex-a53", "arm,armv8"; 128 device_type = "cpu"; 129 reg = <0x0 0x100>; 130 enable-method = "psci"; 131 next-level-cache = <&CLUSTER1_L2>; 132 operating-points-v2 = <&cpu_opp_table>; 133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 134 }; 135 136 cpu5: cpu@101 { 137 compatible = "arm,cortex-a53", "arm,armv8"; 138 device_type = "cpu"; 139 reg = <0x0 0x101>; 140 enable-method = "psci"; 141 next-level-cache = <&CLUSTER1_L2>; 142 operating-points-v2 = <&cpu_opp_table>; 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 144 }; 145 146 cpu6: cpu@102 { 147 compatible = "arm,cortex-a53", "arm,armv8"; 148 device_type = "cpu"; 149 reg = <0x0 0x102>; 150 enable-method = "psci"; 151 next-level-cache = <&CLUSTER1_L2>; 152 operating-points-v2 = <&cpu_opp_table>; 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 154 }; 155 156 cpu7: cpu@103 { 157 compatible = "arm,cortex-a53", "arm,armv8"; 158 device_type = "cpu"; 159 reg = <0x0 0x103>; 160 enable-method = "psci"; 161 next-level-cache = <&CLUSTER1_L2>; 162 operating-points-v2 = <&cpu_opp_table>; 163 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 164 }; 165 166 CLUSTER0_L2: l2-cache0 { 167 compatible = "cache"; 168 }; 169 170 CLUSTER1_L2: l2-cache1 { 171 compatible = "cache"; 172 }; 173 }; 174 175 cpu_opp_table: cpu_opp_table { 176 compatible = "operating-points-v2"; 177 opp-shared; 178 179 opp00 { 180 opp-hz = /bits/ 64 <208000000>; 181 opp-microvolt = <1040000>; 182 clock-latency-ns = <500000>; 183 }; 184 opp01 { 185 opp-hz = /bits/ 64 <432000000>; 186 opp-microvolt = <1040000>; 187 clock-latency-ns = <500000>; 188 }; 189 opp02 { 190 opp-hz = /bits/ 64 <729000000>; 191 opp-microvolt = <1090000>; 192 clock-latency-ns = <500000>; 193 }; 194 opp03 { 195 opp-hz = /bits/ 64 <960000000>; 196 opp-microvolt = <1180000>; 197 clock-latency-ns = <500000>; 198 }; 199 opp04 { 200 opp-hz = /bits/ 64 <1200000000>; 201 opp-microvolt = <1330000>; 202 clock-latency-ns = <500000>; 203 }; 204 }; 205 206 gic: interrupt-controller@f6801000 { 207 compatible = "arm,gic-400"; 208 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 209 <0x0 0xf6802000 0 0x2000>, /* GICC */ 210 <0x0 0xf6804000 0 0x2000>, /* GICH */ 211 <0x0 0xf6806000 0 0x2000>; /* GICV */ 212 #address-cells = <0>; 213 #interrupt-cells = <3>; 214 interrupt-controller; 215 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 216 }; 217 218 timer { 219 compatible = "arm,armv8-timer"; 220 interrupt-parent = <&gic>; 221 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 222 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 223 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 224 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 225 }; 226 227 soc { 228 compatible = "simple-bus"; 229 #address-cells = <2>; 230 #size-cells = <2>; 231 ranges; 232 233 sram: sram@fff80000 { 234 compatible = "hisilicon,hi6220-sramctrl", "syscon"; 235 reg = <0x0 0xfff80000 0x0 0x12000>; 236 }; 237 238 ao_ctrl: ao_ctrl@f7800000 { 239 compatible = "hisilicon,hi6220-aoctrl", "syscon"; 240 reg = <0x0 0xf7800000 0x0 0x2000>; 241 #clock-cells = <1>; 242 }; 243 244 sys_ctrl: sys_ctrl@f7030000 { 245 compatible = "hisilicon,hi6220-sysctrl", "syscon"; 246 reg = <0x0 0xf7030000 0x0 0x2000>; 247 #clock-cells = <1>; 248 #reset-cells = <1>; 249 }; 250 251 media_ctrl: media_ctrl@f4410000 { 252 compatible = "hisilicon,hi6220-mediactrl", "syscon"; 253 reg = <0x0 0xf4410000 0x0 0x1000>; 254 #clock-cells = <1>; 255 }; 256 257 pm_ctrl: pm_ctrl@f7032000 { 258 compatible = "hisilicon,hi6220-pmctrl", "syscon"; 259 reg = <0x0 0xf7032000 0x0 0x1000>; 260 #clock-cells = <1>; 261 }; 262 263 stub_clock: stub_clock { 264 compatible = "hisilicon,hi6220-stub-clk"; 265 hisilicon,hi6220-clk-sram = <&sram>; 266 #clock-cells = <1>; 267 mbox-names = "mbox-tx"; 268 mboxes = <&mailbox 1 0 11>; 269 }; 270 271 uart0: uart@f8015000 { /* console */ 272 compatible = "arm,pl011", "arm,primecell"; 273 reg = <0x0 0xf8015000 0x0 0x1000>; 274 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&ao_ctrl HI6220_UART0_PCLK>, 276 <&ao_ctrl HI6220_UART0_PCLK>; 277 clock-names = "uartclk", "apb_pclk"; 278 }; 279 280 uart1: uart@f7111000 { 281 compatible = "arm,pl011", "arm,primecell"; 282 reg = <0x0 0xf7111000 0x0 0x1000>; 283 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&sys_ctrl HI6220_UART1_PCLK>, 285 <&sys_ctrl HI6220_UART1_PCLK>; 286 clock-names = "uartclk", "apb_pclk"; 287 pinctrl-names = "default"; 288 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; 289 status = "disabled"; 290 }; 291 292 uart2: uart@f7112000 { 293 compatible = "arm,pl011", "arm,primecell"; 294 reg = <0x0 0xf7112000 0x0 0x1000>; 295 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&sys_ctrl HI6220_UART2_PCLK>, 297 <&sys_ctrl HI6220_UART2_PCLK>; 298 clock-names = "uartclk", "apb_pclk"; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 301 status = "disabled"; 302 }; 303 304 uart3: uart@f7113000 { 305 compatible = "arm,pl011", "arm,primecell"; 306 reg = <0x0 0xf7113000 0x0 0x1000>; 307 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&sys_ctrl HI6220_UART3_PCLK>, 309 <&sys_ctrl HI6220_UART3_PCLK>; 310 clock-names = "uartclk", "apb_pclk"; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 313 status = "disabled"; 314 }; 315 316 uart4: uart@f7114000 { 317 compatible = "arm,pl011", "arm,primecell"; 318 reg = <0x0 0xf7114000 0x0 0x1000>; 319 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&sys_ctrl HI6220_UART4_PCLK>, 321 <&sys_ctrl HI6220_UART4_PCLK>; 322 clock-names = "uartclk", "apb_pclk"; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 325 status = "disabled"; 326 }; 327 328 dual_timer0: timer@f8008000 { 329 compatible = "arm,sp804", "arm,primecell"; 330 reg = <0x0 0xf8008000 0x0 0x1000>; 331 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, 334 <&ao_ctrl HI6220_TIMER0_PCLK>, 335 <&ao_ctrl HI6220_TIMER0_PCLK>; 336 clock-names = "timer1", "timer2", "apb_pclk"; 337 }; 338 339 rtc0: rtc@f8003000 { 340 compatible = "arm,pl031", "arm,primecell"; 341 reg = <0x0 0xf8003000 0x0 0x1000>; 342 interrupts = <0 12 4>; 343 clocks = <&ao_ctrl HI6220_RTC0_PCLK>; 344 clock-names = "apb_pclk"; 345 }; 346 347 rtc1: rtc@f8004000 { 348 compatible = "arm,pl031", "arm,primecell"; 349 reg = <0x0 0xf8004000 0x0 0x1000>; 350 interrupts = <0 8 4>; 351 clocks = <&ao_ctrl HI6220_RTC1_PCLK>; 352 clock-names = "apb_pclk"; 353 }; 354 355 pmx0: pinmux@f7010000 { 356 compatible = "pinctrl-single"; 357 reg = <0x0 0xf7010000 0x0 0x27c>; 358 #address-cells = <1>; 359 #size-cells = <1>; 360 #gpio-range-cells = <3>; 361 pinctrl-single,register-width = <32>; 362 pinctrl-single,function-mask = <7>; 363 pinctrl-single,gpio-range = < 364 &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 365 &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 366 &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 367 &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 368 &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 369 &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 370 &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 371 &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 372 &range 0 1 MUX_M1 /* gpio 10: [0] */ 373 &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 374 &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 375 &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 376 &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 377 &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 378 &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 379 &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 380 &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 381 &range 122 1 MUX_M1 /* gpio 15: [6] */ 382 &range 126 1 MUX_M1 /* gpio 15: [7] */ 383 &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 384 &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 385 &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 386 &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 387 >; 388 range: gpio-range { 389 #pinctrl-single,gpio-range-cells = <3>; 390 }; 391 }; 392 393 pmx1: pinmux@f7010800 { 394 compatible = "pinconf-single"; 395 reg = <0x0 0xf7010800 0x0 0x28c>; 396 #address-cells = <1>; 397 #size-cells = <1>; 398 pinctrl-single,register-width = <32>; 399 }; 400 401 pmx2: pinmux@f8001800 { 402 compatible = "pinconf-single"; 403 reg = <0x0 0xf8001800 0x0 0x78>; 404 #address-cells = <1>; 405 #size-cells = <1>; 406 pinctrl-single,register-width = <32>; 407 }; 408 409 gpio0: gpio@f8011000 { 410 compatible = "arm,pl061", "arm,primecell"; 411 reg = <0x0 0xf8011000 0x0 0x1000>; 412 interrupts = <0 52 0x4>; 413 gpio-controller; 414 #gpio-cells = <2>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 clocks = <&ao_ctrl 2>; 418 clock-names = "apb_pclk"; 419 }; 420 421 gpio1: gpio@f8012000 { 422 compatible = "arm,pl061", "arm,primecell"; 423 reg = <0x0 0xf8012000 0x0 0x1000>; 424 interrupts = <0 53 0x4>; 425 gpio-controller; 426 #gpio-cells = <2>; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 clocks = <&ao_ctrl 2>; 430 clock-names = "apb_pclk"; 431 }; 432 433 gpio2: gpio@f8013000 { 434 compatible = "arm,pl061", "arm,primecell"; 435 reg = <0x0 0xf8013000 0x0 0x1000>; 436 interrupts = <0 54 0x4>; 437 gpio-controller; 438 #gpio-cells = <2>; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 clocks = <&ao_ctrl 2>; 442 clock-names = "apb_pclk"; 443 }; 444 445 gpio3: gpio@f8014000 { 446 compatible = "arm,pl061", "arm,primecell"; 447 reg = <0x0 0xf8014000 0x0 0x1000>; 448 interrupts = <0 55 0x4>; 449 gpio-controller; 450 #gpio-cells = <2>; 451 gpio-ranges = <&pmx0 0 80 8>; 452 interrupt-controller; 453 #interrupt-cells = <2>; 454 clocks = <&ao_ctrl 2>; 455 clock-names = "apb_pclk"; 456 }; 457 458 gpio4: gpio@f7020000 { 459 compatible = "arm,pl061", "arm,primecell"; 460 reg = <0x0 0xf7020000 0x0 0x1000>; 461 interrupts = <0 56 0x4>; 462 gpio-controller; 463 #gpio-cells = <2>; 464 gpio-ranges = <&pmx0 0 88 8>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 clocks = <&ao_ctrl 2>; 468 clock-names = "apb_pclk"; 469 }; 470 471 gpio5: gpio@f7021000 { 472 compatible = "arm,pl061", "arm,primecell"; 473 reg = <0x0 0xf7021000 0x0 0x1000>; 474 interrupts = <0 57 0x4>; 475 gpio-controller; 476 #gpio-cells = <2>; 477 gpio-ranges = <&pmx0 0 96 8>; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 clocks = <&ao_ctrl 2>; 481 clock-names = "apb_pclk"; 482 }; 483 484 gpio6: gpio@f7022000 { 485 compatible = "arm,pl061", "arm,primecell"; 486 reg = <0x0 0xf7022000 0x0 0x1000>; 487 interrupts = <0 58 0x4>; 488 gpio-controller; 489 #gpio-cells = <2>; 490 gpio-ranges = <&pmx0 0 104 8>; 491 interrupt-controller; 492 #interrupt-cells = <2>; 493 clocks = <&ao_ctrl 2>; 494 clock-names = "apb_pclk"; 495 }; 496 497 gpio7: gpio@f7023000 { 498 compatible = "arm,pl061", "arm,primecell"; 499 reg = <0x0 0xf7023000 0x0 0x1000>; 500 interrupts = <0 59 0x4>; 501 gpio-controller; 502 #gpio-cells = <2>; 503 gpio-ranges = <&pmx0 0 112 8>; 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 clocks = <&ao_ctrl 2>; 507 clock-names = "apb_pclk"; 508 }; 509 510 gpio8: gpio@f7024000 { 511 compatible = "arm,pl061", "arm,primecell"; 512 reg = <0x0 0xf7024000 0x0 0x1000>; 513 interrupts = <0 60 0x4>; 514 gpio-controller; 515 #gpio-cells = <2>; 516 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 clocks = <&ao_ctrl 2>; 520 clock-names = "apb_pclk"; 521 }; 522 523 gpio9: gpio@f7025000 { 524 compatible = "arm,pl061", "arm,primecell"; 525 reg = <0x0 0xf7025000 0x0 0x1000>; 526 interrupts = <0 61 0x4>; 527 gpio-controller; 528 #gpio-cells = <2>; 529 gpio-ranges = <&pmx0 0 8 8>; 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 clocks = <&ao_ctrl 2>; 533 clock-names = "apb_pclk"; 534 }; 535 536 gpio10: gpio@f7026000 { 537 compatible = "arm,pl061", "arm,primecell"; 538 reg = <0x0 0xf7026000 0x0 0x1000>; 539 interrupts = <0 62 0x4>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 543 interrupt-controller; 544 #interrupt-cells = <2>; 545 clocks = <&ao_ctrl 2>; 546 clock-names = "apb_pclk"; 547 }; 548 549 gpio11: gpio@f7027000 { 550 compatible = "arm,pl061", "arm,primecell"; 551 reg = <0x0 0xf7027000 0x0 0x1000>; 552 interrupts = <0 63 0x4>; 553 gpio-controller; 554 #gpio-cells = <2>; 555 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 clocks = <&ao_ctrl 2>; 559 clock-names = "apb_pclk"; 560 }; 561 562 gpio12: gpio@f7028000 { 563 compatible = "arm,pl061", "arm,primecell"; 564 reg = <0x0 0xf7028000 0x0 0x1000>; 565 interrupts = <0 64 0x4>; 566 gpio-controller; 567 #gpio-cells = <2>; 568 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 569 interrupt-controller; 570 #interrupt-cells = <2>; 571 clocks = <&ao_ctrl 2>; 572 clock-names = "apb_pclk"; 573 }; 574 575 gpio13: gpio@f7029000 { 576 compatible = "arm,pl061", "arm,primecell"; 577 reg = <0x0 0xf7029000 0x0 0x1000>; 578 interrupts = <0 65 0x4>; 579 gpio-controller; 580 #gpio-cells = <2>; 581 gpio-ranges = <&pmx0 0 48 8>; 582 interrupt-controller; 583 #interrupt-cells = <2>; 584 clocks = <&ao_ctrl 2>; 585 clock-names = "apb_pclk"; 586 }; 587 588 gpio14: gpio@f702a000 { 589 compatible = "arm,pl061", "arm,primecell"; 590 reg = <0x0 0xf702a000 0x0 0x1000>; 591 interrupts = <0 66 0x4>; 592 gpio-controller; 593 #gpio-cells = <2>; 594 gpio-ranges = <&pmx0 0 56 8>; 595 interrupt-controller; 596 #interrupt-cells = <2>; 597 clocks = <&ao_ctrl 2>; 598 clock-names = "apb_pclk"; 599 }; 600 601 gpio15: gpio@f702b000 { 602 compatible = "arm,pl061", "arm,primecell"; 603 reg = <0x0 0xf702b000 0x0 0x1000>; 604 interrupts = <0 67 0x4>; 605 gpio-controller; 606 #gpio-cells = <2>; 607 gpio-ranges = < 608 &pmx0 0 74 6 609 &pmx0 6 122 1 610 &pmx0 7 126 1 611 >; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 clocks = <&ao_ctrl 2>; 615 clock-names = "apb_pclk"; 616 }; 617 618 gpio16: gpio@f702c000 { 619 compatible = "arm,pl061", "arm,primecell"; 620 reg = <0x0 0xf702c000 0x0 0x1000>; 621 interrupts = <0 68 0x4>; 622 gpio-controller; 623 #gpio-cells = <2>; 624 gpio-ranges = <&pmx0 0 127 8>; 625 interrupt-controller; 626 #interrupt-cells = <2>; 627 clocks = <&ao_ctrl 2>; 628 clock-names = "apb_pclk"; 629 }; 630 631 gpio17: gpio@f702d000 { 632 compatible = "arm,pl061", "arm,primecell"; 633 reg = <0x0 0xf702d000 0x0 0x1000>; 634 interrupts = <0 69 0x4>; 635 gpio-controller; 636 #gpio-cells = <2>; 637 gpio-ranges = <&pmx0 0 135 8>; 638 interrupt-controller; 639 #interrupt-cells = <2>; 640 clocks = <&ao_ctrl 2>; 641 clock-names = "apb_pclk"; 642 }; 643 644 gpio18: gpio@f702e000 { 645 compatible = "arm,pl061", "arm,primecell"; 646 reg = <0x0 0xf702e000 0x0 0x1000>; 647 interrupts = <0 70 0x4>; 648 gpio-controller; 649 #gpio-cells = <2>; 650 gpio-ranges = <&pmx0 0 143 8>; 651 interrupt-controller; 652 #interrupt-cells = <2>; 653 clocks = <&ao_ctrl 2>; 654 clock-names = "apb_pclk"; 655 }; 656 657 gpio19: gpio@f702f000 { 658 compatible = "arm,pl061", "arm,primecell"; 659 reg = <0x0 0xf702f000 0x0 0x1000>; 660 interrupts = <0 71 0x4>; 661 gpio-controller; 662 #gpio-cells = <2>; 663 gpio-ranges = <&pmx0 0 151 8>; 664 interrupt-controller; 665 #interrupt-cells = <2>; 666 clocks = <&ao_ctrl 2>; 667 clock-names = "apb_pclk"; 668 }; 669 670 spi0: spi@f7106000 { 671 compatible = "arm,pl022", "arm,primecell"; 672 reg = <0x0 0xf7106000 0x0 0x1000>; 673 interrupts = <0 50 4>; 674 bus-id = <0>; 675 enable-dma = <0>; 676 clocks = <&sys_ctrl HI6220_SPI_CLK>; 677 clock-names = "apb_pclk"; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 680 num-cs = <1>; 681 cs-gpios = <&gpio6 2 0>; 682 status = "disabled"; 683 }; 684 685 i2c0: i2c@f7100000 { 686 compatible = "snps,designware-i2c"; 687 reg = <0x0 0xf7100000 0x0 0x1000>; 688 interrupts = <0 44 4>; 689 clocks = <&sys_ctrl HI6220_I2C0_CLK>; 690 i2c-sda-hold-time-ns = <300>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 693 status = "disabled"; 694 }; 695 696 i2c1: i2c@f7101000 { 697 compatible = "snps,designware-i2c"; 698 reg = <0x0 0xf7101000 0x0 0x1000>; 699 clocks = <&sys_ctrl HI6220_I2C1_CLK>; 700 interrupts = <0 45 4>; 701 i2c-sda-hold-time-ns = <300>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 704 status = "disabled"; 705 }; 706 707 i2c2: i2c@f7102000 { 708 compatible = "snps,designware-i2c"; 709 reg = <0x0 0xf7102000 0x0 0x1000>; 710 clocks = <&sys_ctrl HI6220_I2C2_CLK>; 711 interrupts = <0 46 4>; 712 i2c-sda-hold-time-ns = <300>; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 715 status = "disabled"; 716 }; 717 718 fixed_5v_hub: regulator@0 { 719 compatible = "regulator-fixed"; 720 regulator-name = "fixed_5v_hub"; 721 regulator-min-microvolt = <5000000>; 722 regulator-max-microvolt = <5000000>; 723 regulator-boot-on; 724 gpio = <&gpio0 7 0>; 725 regulator-always-on; 726 }; 727 728 usb_phy: usbphy { 729 compatible = "hisilicon,hi6220-usb-phy"; 730 #phy-cells = <0>; 731 phy-supply = <&fixed_5v_hub>; 732 hisilicon,peripheral-syscon = <&sys_ctrl>; 733 }; 734 735 usb: usb@f72c0000 { 736 compatible = "hisilicon,hi6220-usb"; 737 reg = <0x0 0xf72c0000 0x0 0x40000>; 738 phys = <&usb_phy>; 739 phy-names = "usb2-phy"; 740 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 741 clock-names = "otg"; 742 dr_mode = "otg"; 743 g-use-dma; 744 g-rx-fifo-size = <512>; 745 g-np-tx-fifo-size = <128>; 746 g-tx-fifo-size = <128 128 128 128 128 128>; 747 interrupts = <0 77 0x4>; 748 }; 749 750 mailbox: mailbox@f7510000 { 751 compatible = "hisilicon,hi6220-mbox"; 752 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 753 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 754 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 755 #mbox-cells = <3>; 756 }; 757 758 dwmmc_0: dwmmc0@f723d000 { 759 compatible = "hisilicon,hi6220-dw-mshc"; 760 num-slots = <0x1>; 761 cap-mmc-highspeed; 762 non-removable; 763 reg = <0x0 0xf723d000 0x0 0x1000>; 764 interrupts = <0x0 0x48 0x4>; 765 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; 766 clock-names = "ciu", "biu"; 767 bus-width = <0x8>; 768 vmmc-supply = <&ldo19>; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func 771 &emmc_cfg_func &emmc_rst_cfg_func>; 772 }; 773 774 dwmmc_1: dwmmc1@f723e000 { 775 compatible = "hisilicon,hi6220-dw-mshc"; 776 num-slots = <0x1>; 777 card-detect-delay = <200>; 778 hisilicon,peripheral-syscon = <&ao_ctrl>; 779 cap-sd-highspeed; 780 reg = <0x0 0xf723e000 0x0 0x1000>; 781 interrupts = <0x0 0x49 0x4>; 782 #address-cells = <0x1>; 783 #size-cells = <0x0>; 784 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; 785 clock-names = "ciu", "biu"; 786 vqmmc-supply = <&ldo7>; 787 vmmc-supply = <&ldo10>; 788 bus-width = <0x4>; 789 disable-wp; 790 cd-gpios = <&gpio1 0 1>; 791 pinctrl-names = "default", "idle"; 792 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; 793 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; 794 }; 795 796 dwmmc_2: dwmmc2@f723f000 { 797 compatible = "hisilicon,hi6220-dw-mshc"; 798 num-slots = <0x1>; 799 reg = <0x0 0xf723f000 0x0 0x1000>; 800 interrupts = <0x0 0x4a 0x4>; 801 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; 802 clock-names = "ciu", "biu"; 803 bus-width = <0x4>; 804 broken-cd; 805 pinctrl-names = "default", "idle"; 806 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; 807 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; 808 }; 809 810 tsensor: tsensor@0,f7030700 { 811 compatible = "hisilicon,tsensor"; 812 reg = <0x0 0xf7030700 0x0 0x1000>; 813 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&sys_ctrl 22>; 815 clock-names = "thermal_clk"; 816 #thermal-sensor-cells = <1>; 817 }; 818 819 thermal-zones { 820 821 cls0: cls0 { 822 polling-delay = <1000>; 823 polling-delay-passive = <100>; 824 sustainable-power = <3326>; 825 826 /* sensor ID */ 827 thermal-sensors = <&tsensor 2>; 828 829 trips { 830 threshold: trip-point@0 { 831 temperature = <65000>; 832 hysteresis = <0>; 833 type = "passive"; 834 }; 835 836 target: trip-point@1 { 837 temperature = <75000>; 838 hysteresis = <0>; 839 type = "passive"; 840 }; 841 }; 842 843 cooling-maps { 844 map0 { 845 trip = <&target>; 846 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 847 }; 848 }; 849 }; 850 }; 851 }; 852}; 853