1/* 2 * dts file for Hisilicon Hi6220 SoC 3 * 4 * Copyright (C) 2015, Hisilicon Ltd. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/hi6220-clock.h> 9#include <dt-bindings/pinctrl/hisi.h> 10 11/ { 12 compatible = "hisilicon,hi6220"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 psci { 18 compatible = "arm,psci-0.2"; 19 method = "smc"; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 core2 { 35 cpu = <&cpu2>; 36 }; 37 core3 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 idle-states { 58 entry-method = "psci"; 59 60 CPU_SLEEP: cpu-sleep { 61 compatible = "arm,idle-state"; 62 local-timer-stop; 63 arm,psci-suspend-param = <0x0010000>; 64 entry-latency-us = <700>; 65 exit-latency-us = <250>; 66 min-residency-us = <1000>; 67 }; 68 69 CLUSTER_SLEEP: cluster-sleep { 70 compatible = "arm,idle-state"; 71 local-timer-stop; 72 arm,psci-suspend-param = <0x1010000>; 73 entry-latency-us = <1000>; 74 exit-latency-us = <700>; 75 min-residency-us = <2700>; 76 wakeup-latency-us = <1500>; 77 }; 78 }; 79 80 cpu0: cpu@0 { 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 device_type = "cpu"; 83 reg = <0x0 0x0>; 84 enable-method = "psci"; 85 clocks = <&stub_clock 0>; 86 operating-points-v2 = <&cpu_opp_table>; 87 cooling-min-level = <4>; 88 cooling-max-level = <0>; 89 #cooling-cells = <2>; /* min followed by max */ 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu1: cpu@1 { 94 compatible = "arm,cortex-a53", "arm,armv8"; 95 device_type = "cpu"; 96 reg = <0x0 0x1>; 97 enable-method = "psci"; 98 operating-points-v2 = <&cpu_opp_table>; 99 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 100 }; 101 102 cpu2: cpu@2 { 103 compatible = "arm,cortex-a53", "arm,armv8"; 104 device_type = "cpu"; 105 reg = <0x0 0x2>; 106 enable-method = "psci"; 107 operating-points-v2 = <&cpu_opp_table>; 108 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 109 }; 110 111 cpu3: cpu@3 { 112 compatible = "arm,cortex-a53", "arm,armv8"; 113 device_type = "cpu"; 114 reg = <0x0 0x3>; 115 enable-method = "psci"; 116 operating-points-v2 = <&cpu_opp_table>; 117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 118 }; 119 120 cpu4: cpu@100 { 121 compatible = "arm,cortex-a53", "arm,armv8"; 122 device_type = "cpu"; 123 reg = <0x0 0x100>; 124 enable-method = "psci"; 125 operating-points-v2 = <&cpu_opp_table>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 }; 128 129 cpu5: cpu@101 { 130 compatible = "arm,cortex-a53", "arm,armv8"; 131 device_type = "cpu"; 132 reg = <0x0 0x101>; 133 enable-method = "psci"; 134 operating-points-v2 = <&cpu_opp_table>; 135 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 136 }; 137 138 cpu6: cpu@102 { 139 compatible = "arm,cortex-a53", "arm,armv8"; 140 device_type = "cpu"; 141 reg = <0x0 0x102>; 142 enable-method = "psci"; 143 operating-points-v2 = <&cpu_opp_table>; 144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 145 }; 146 147 cpu7: cpu@103 { 148 compatible = "arm,cortex-a53", "arm,armv8"; 149 device_type = "cpu"; 150 reg = <0x0 0x103>; 151 enable-method = "psci"; 152 operating-points-v2 = <&cpu_opp_table>; 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 154 }; 155 }; 156 157 cpu_opp_table: cpu_opp_table { 158 compatible = "operating-points-v2"; 159 opp-shared; 160 161 opp00 { 162 opp-hz = /bits/ 64 <208000000>; 163 opp-microvolt = <1040000>; 164 clock-latency-ns = <500000>; 165 }; 166 opp01 { 167 opp-hz = /bits/ 64 <432000000>; 168 opp-microvolt = <1040000>; 169 clock-latency-ns = <500000>; 170 }; 171 opp02 { 172 opp-hz = /bits/ 64 <729000000>; 173 opp-microvolt = <1090000>; 174 clock-latency-ns = <500000>; 175 }; 176 opp03 { 177 opp-hz = /bits/ 64 <960000000>; 178 opp-microvolt = <1180000>; 179 clock-latency-ns = <500000>; 180 }; 181 opp04 { 182 opp-hz = /bits/ 64 <1200000000>; 183 opp-microvolt = <1330000>; 184 clock-latency-ns = <500000>; 185 }; 186 }; 187 188 gic: interrupt-controller@f6801000 { 189 compatible = "arm,gic-400"; 190 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 191 <0x0 0xf6802000 0 0x2000>, /* GICC */ 192 <0x0 0xf6804000 0 0x2000>, /* GICH */ 193 <0x0 0xf6806000 0 0x2000>; /* GICV */ 194 #address-cells = <0>; 195 #interrupt-cells = <3>; 196 interrupt-controller; 197 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupt-parent = <&gic>; 203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 205 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 206 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 207 }; 208 209 soc { 210 compatible = "simple-bus"; 211 #address-cells = <2>; 212 #size-cells = <2>; 213 ranges; 214 215 sram: sram@fff80000 { 216 compatible = "hisilicon,hi6220-sramctrl", "syscon"; 217 reg = <0x0 0xfff80000 0x0 0x12000>; 218 }; 219 220 ao_ctrl: ao_ctrl@f7800000 { 221 compatible = "hisilicon,hi6220-aoctrl", "syscon"; 222 reg = <0x0 0xf7800000 0x0 0x2000>; 223 #clock-cells = <1>; 224 }; 225 226 sys_ctrl: sys_ctrl@f7030000 { 227 compatible = "hisilicon,hi6220-sysctrl", "syscon"; 228 reg = <0x0 0xf7030000 0x0 0x2000>; 229 #clock-cells = <1>; 230 #reset-cells = <1>; 231 }; 232 233 media_ctrl: media_ctrl@f4410000 { 234 compatible = "hisilicon,hi6220-mediactrl", "syscon"; 235 reg = <0x0 0xf4410000 0x0 0x1000>; 236 #clock-cells = <1>; 237 }; 238 239 pm_ctrl: pm_ctrl@f7032000 { 240 compatible = "hisilicon,hi6220-pmctrl", "syscon"; 241 reg = <0x0 0xf7032000 0x0 0x1000>; 242 #clock-cells = <1>; 243 }; 244 245 stub_clock: stub_clock { 246 compatible = "hisilicon,hi6220-stub-clk"; 247 hisilicon,hi6220-clk-sram = <&sram>; 248 #clock-cells = <1>; 249 mbox-names = "mbox-tx"; 250 mboxes = <&mailbox 1 0 11>; 251 }; 252 253 uart0: uart@f8015000 { /* console */ 254 compatible = "arm,pl011", "arm,primecell"; 255 reg = <0x0 0xf8015000 0x0 0x1000>; 256 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&ao_ctrl HI6220_UART0_PCLK>, 258 <&ao_ctrl HI6220_UART0_PCLK>; 259 clock-names = "uartclk", "apb_pclk"; 260 }; 261 262 uart1: uart@f7111000 { 263 compatible = "arm,pl011", "arm,primecell"; 264 reg = <0x0 0xf7111000 0x0 0x1000>; 265 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&sys_ctrl HI6220_UART1_PCLK>, 267 <&sys_ctrl HI6220_UART1_PCLK>; 268 clock-names = "uartclk", "apb_pclk"; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; 271 status = "disabled"; 272 }; 273 274 uart2: uart@f7112000 { 275 compatible = "arm,pl011", "arm,primecell"; 276 reg = <0x0 0xf7112000 0x0 0x1000>; 277 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&sys_ctrl HI6220_UART2_PCLK>, 279 <&sys_ctrl HI6220_UART2_PCLK>; 280 clock-names = "uartclk", "apb_pclk"; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 283 status = "disabled"; 284 }; 285 286 uart3: uart@f7113000 { 287 compatible = "arm,pl011", "arm,primecell"; 288 reg = <0x0 0xf7113000 0x0 0x1000>; 289 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&sys_ctrl HI6220_UART3_PCLK>, 291 <&sys_ctrl HI6220_UART3_PCLK>; 292 clock-names = "uartclk", "apb_pclk"; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 295 status = "disabled"; 296 }; 297 298 uart4: uart@f7114000 { 299 compatible = "arm,pl011", "arm,primecell"; 300 reg = <0x0 0xf7114000 0x0 0x1000>; 301 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&sys_ctrl HI6220_UART4_PCLK>, 303 <&sys_ctrl HI6220_UART4_PCLK>; 304 clock-names = "uartclk", "apb_pclk"; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 307 status = "disabled"; 308 }; 309 310 dual_timer0: timer@f8008000 { 311 compatible = "arm,sp804", "arm,primecell"; 312 reg = <0x0 0xf8008000 0x0 0x1000>; 313 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, 316 <&ao_ctrl HI6220_TIMER0_PCLK>, 317 <&ao_ctrl HI6220_TIMER0_PCLK>; 318 clock-names = "timer1", "timer2", "apb_pclk"; 319 }; 320 321 pmx0: pinmux@f7010000 { 322 compatible = "pinctrl-single"; 323 reg = <0x0 0xf7010000 0x0 0x27c>; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 #gpio-range-cells = <3>; 327 pinctrl-single,register-width = <32>; 328 pinctrl-single,function-mask = <7>; 329 pinctrl-single,gpio-range = < 330 &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 331 &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 332 &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 333 &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 334 &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 335 &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 336 &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 337 &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 338 &range 0 1 MUX_M1 /* gpio 10: [0] */ 339 &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 340 &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 341 &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 342 &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 343 &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 344 &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 345 &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 346 &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 347 &range 122 1 MUX_M1 /* gpio 15: [6] */ 348 &range 126 1 MUX_M1 /* gpio 15: [7] */ 349 &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 350 &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 351 &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 352 &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 353 >; 354 range: gpio-range { 355 #pinctrl-single,gpio-range-cells = <3>; 356 }; 357 }; 358 359 pmx1: pinmux@f7010800 { 360 compatible = "pinconf-single"; 361 reg = <0x0 0xf7010800 0x0 0x28c>; 362 #address-cells = <1>; 363 #size-cells = <1>; 364 pinctrl-single,register-width = <32>; 365 }; 366 367 pmx2: pinmux@f8001800 { 368 compatible = "pinconf-single"; 369 reg = <0x0 0xf8001800 0x0 0x78>; 370 #address-cells = <1>; 371 #size-cells = <1>; 372 pinctrl-single,register-width = <32>; 373 }; 374 375 gpio0: gpio@f8011000 { 376 compatible = "arm,pl061", "arm,primecell"; 377 reg = <0x0 0xf8011000 0x0 0x1000>; 378 interrupts = <0 52 0x4>; 379 gpio-controller; 380 #gpio-cells = <2>; 381 interrupt-controller; 382 #interrupt-cells = <2>; 383 clocks = <&ao_ctrl 2>; 384 clock-names = "apb_pclk"; 385 }; 386 387 gpio1: gpio@f8012000 { 388 compatible = "arm,pl061", "arm,primecell"; 389 reg = <0x0 0xf8012000 0x0 0x1000>; 390 interrupts = <0 53 0x4>; 391 gpio-controller; 392 #gpio-cells = <2>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 clocks = <&ao_ctrl 2>; 396 clock-names = "apb_pclk"; 397 }; 398 399 gpio2: gpio@f8013000 { 400 compatible = "arm,pl061", "arm,primecell"; 401 reg = <0x0 0xf8013000 0x0 0x1000>; 402 interrupts = <0 54 0x4>; 403 gpio-controller; 404 #gpio-cells = <2>; 405 interrupt-controller; 406 #interrupt-cells = <2>; 407 clocks = <&ao_ctrl 2>; 408 clock-names = "apb_pclk"; 409 }; 410 411 gpio3: gpio@f8014000 { 412 compatible = "arm,pl061", "arm,primecell"; 413 reg = <0x0 0xf8014000 0x0 0x1000>; 414 interrupts = <0 55 0x4>; 415 gpio-controller; 416 #gpio-cells = <2>; 417 gpio-ranges = <&pmx0 0 80 8>; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 clocks = <&ao_ctrl 2>; 421 clock-names = "apb_pclk"; 422 }; 423 424 gpio4: gpio@f7020000 { 425 compatible = "arm,pl061", "arm,primecell"; 426 reg = <0x0 0xf7020000 0x0 0x1000>; 427 interrupts = <0 56 0x4>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 gpio-ranges = <&pmx0 0 88 8>; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 clocks = <&ao_ctrl 2>; 434 clock-names = "apb_pclk"; 435 }; 436 437 gpio5: gpio@f7021000 { 438 compatible = "arm,pl061", "arm,primecell"; 439 reg = <0x0 0xf7021000 0x0 0x1000>; 440 interrupts = <0 57 0x4>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 gpio-ranges = <&pmx0 0 96 8>; 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 clocks = <&ao_ctrl 2>; 447 clock-names = "apb_pclk"; 448 }; 449 450 gpio6: gpio@f7022000 { 451 compatible = "arm,pl061", "arm,primecell"; 452 reg = <0x0 0xf7022000 0x0 0x1000>; 453 interrupts = <0 58 0x4>; 454 gpio-controller; 455 #gpio-cells = <2>; 456 gpio-ranges = <&pmx0 0 104 8>; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 clocks = <&ao_ctrl 2>; 460 clock-names = "apb_pclk"; 461 }; 462 463 gpio7: gpio@f7023000 { 464 compatible = "arm,pl061", "arm,primecell"; 465 reg = <0x0 0xf7023000 0x0 0x1000>; 466 interrupts = <0 59 0x4>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 gpio-ranges = <&pmx0 0 112 8>; 470 interrupt-controller; 471 #interrupt-cells = <2>; 472 clocks = <&ao_ctrl 2>; 473 clock-names = "apb_pclk"; 474 }; 475 476 gpio8: gpio@f7024000 { 477 compatible = "arm,pl061", "arm,primecell"; 478 reg = <0x0 0xf7024000 0x0 0x1000>; 479 interrupts = <0 60 0x4>; 480 gpio-controller; 481 #gpio-cells = <2>; 482 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 clocks = <&ao_ctrl 2>; 486 clock-names = "apb_pclk"; 487 }; 488 489 gpio9: gpio@f7025000 { 490 compatible = "arm,pl061", "arm,primecell"; 491 reg = <0x0 0xf7025000 0x0 0x1000>; 492 interrupts = <0 61 0x4>; 493 gpio-controller; 494 #gpio-cells = <2>; 495 gpio-ranges = <&pmx0 0 8 8>; 496 interrupt-controller; 497 #interrupt-cells = <2>; 498 clocks = <&ao_ctrl 2>; 499 clock-names = "apb_pclk"; 500 }; 501 502 gpio10: gpio@f7026000 { 503 compatible = "arm,pl061", "arm,primecell"; 504 reg = <0x0 0xf7026000 0x0 0x1000>; 505 interrupts = <0 62 0x4>; 506 gpio-controller; 507 #gpio-cells = <2>; 508 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 509 interrupt-controller; 510 #interrupt-cells = <2>; 511 clocks = <&ao_ctrl 2>; 512 clock-names = "apb_pclk"; 513 }; 514 515 gpio11: gpio@f7027000 { 516 compatible = "arm,pl061", "arm,primecell"; 517 reg = <0x0 0xf7027000 0x0 0x1000>; 518 interrupts = <0 63 0x4>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 clocks = <&ao_ctrl 2>; 525 clock-names = "apb_pclk"; 526 }; 527 528 gpio12: gpio@f7028000 { 529 compatible = "arm,pl061", "arm,primecell"; 530 reg = <0x0 0xf7028000 0x0 0x1000>; 531 interrupts = <0 64 0x4>; 532 gpio-controller; 533 #gpio-cells = <2>; 534 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 clocks = <&ao_ctrl 2>; 538 clock-names = "apb_pclk"; 539 }; 540 541 gpio13: gpio@f7029000 { 542 compatible = "arm,pl061", "arm,primecell"; 543 reg = <0x0 0xf7029000 0x0 0x1000>; 544 interrupts = <0 65 0x4>; 545 gpio-controller; 546 #gpio-cells = <2>; 547 gpio-ranges = <&pmx0 0 48 8>; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 clocks = <&ao_ctrl 2>; 551 clock-names = "apb_pclk"; 552 }; 553 554 gpio14: gpio@f702a000 { 555 compatible = "arm,pl061", "arm,primecell"; 556 reg = <0x0 0xf702a000 0x0 0x1000>; 557 interrupts = <0 66 0x4>; 558 gpio-controller; 559 #gpio-cells = <2>; 560 gpio-ranges = <&pmx0 0 56 8>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 clocks = <&ao_ctrl 2>; 564 clock-names = "apb_pclk"; 565 }; 566 567 gpio15: gpio@f702b000 { 568 compatible = "arm,pl061", "arm,primecell"; 569 reg = <0x0 0xf702b000 0x0 0x1000>; 570 interrupts = <0 67 0x4>; 571 gpio-controller; 572 #gpio-cells = <2>; 573 gpio-ranges = < 574 &pmx0 0 74 6 575 &pmx0 6 122 1 576 &pmx0 7 126 1 577 >; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 clocks = <&ao_ctrl 2>; 581 clock-names = "apb_pclk"; 582 }; 583 584 gpio16: gpio@f702c000 { 585 compatible = "arm,pl061", "arm,primecell"; 586 reg = <0x0 0xf702c000 0x0 0x1000>; 587 interrupts = <0 68 0x4>; 588 gpio-controller; 589 #gpio-cells = <2>; 590 gpio-ranges = <&pmx0 0 127 8>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 clocks = <&ao_ctrl 2>; 594 clock-names = "apb_pclk"; 595 }; 596 597 gpio17: gpio@f702d000 { 598 compatible = "arm,pl061", "arm,primecell"; 599 reg = <0x0 0xf702d000 0x0 0x1000>; 600 interrupts = <0 69 0x4>; 601 gpio-controller; 602 #gpio-cells = <2>; 603 gpio-ranges = <&pmx0 0 135 8>; 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 clocks = <&ao_ctrl 2>; 607 clock-names = "apb_pclk"; 608 }; 609 610 gpio18: gpio@f702e000 { 611 compatible = "arm,pl061", "arm,primecell"; 612 reg = <0x0 0xf702e000 0x0 0x1000>; 613 interrupts = <0 70 0x4>; 614 gpio-controller; 615 #gpio-cells = <2>; 616 gpio-ranges = <&pmx0 0 143 8>; 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 clocks = <&ao_ctrl 2>; 620 clock-names = "apb_pclk"; 621 }; 622 623 gpio19: gpio@f702f000 { 624 compatible = "arm,pl061", "arm,primecell"; 625 reg = <0x0 0xf702f000 0x0 0x1000>; 626 interrupts = <0 71 0x4>; 627 gpio-controller; 628 #gpio-cells = <2>; 629 gpio-ranges = <&pmx0 0 151 8>; 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 clocks = <&ao_ctrl 2>; 633 clock-names = "apb_pclk"; 634 }; 635 636 spi0: spi@f7106000 { 637 compatible = "arm,pl022", "arm,primecell"; 638 reg = <0x0 0xf7106000 0x0 0x1000>; 639 interrupts = <0 50 4>; 640 bus-id = <0>; 641 enable-dma = <0>; 642 clocks = <&sys_ctrl HI6220_SPI_CLK>; 643 clock-names = "apb_pclk"; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 646 num-cs = <1>; 647 cs-gpios = <&gpio6 2 0>; 648 status = "disabled"; 649 }; 650 651 i2c0: i2c@f7100000 { 652 compatible = "snps,designware-i2c"; 653 reg = <0x0 0xf7100000 0x0 0x1000>; 654 interrupts = <0 44 4>; 655 clocks = <&sys_ctrl HI6220_I2C0_CLK>; 656 i2c-sda-hold-time-ns = <300>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 659 status = "disabled"; 660 }; 661 662 i2c1: i2c@f7101000 { 663 compatible = "snps,designware-i2c"; 664 reg = <0x0 0xf7101000 0x0 0x1000>; 665 clocks = <&sys_ctrl HI6220_I2C1_CLK>; 666 interrupts = <0 45 4>; 667 i2c-sda-hold-time-ns = <300>; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 670 status = "disabled"; 671 }; 672 673 i2c2: i2c@f7102000 { 674 compatible = "snps,designware-i2c"; 675 reg = <0x0 0xf7102000 0x0 0x1000>; 676 clocks = <&sys_ctrl HI6220_I2C2_CLK>; 677 interrupts = <0 46 4>; 678 i2c-sda-hold-time-ns = <300>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 681 status = "disabled"; 682 }; 683 684 fixed_5v_hub: regulator@0 { 685 compatible = "regulator-fixed"; 686 regulator-name = "fixed_5v_hub"; 687 regulator-min-microvolt = <5000000>; 688 regulator-max-microvolt = <5000000>; 689 regulator-boot-on; 690 gpio = <&gpio0 7 0>; 691 regulator-always-on; 692 }; 693 694 usb_phy: usbphy { 695 compatible = "hisilicon,hi6220-usb-phy"; 696 #phy-cells = <0>; 697 phy-supply = <&fixed_5v_hub>; 698 hisilicon,peripheral-syscon = <&sys_ctrl>; 699 }; 700 701 usb: usb@f72c0000 { 702 compatible = "hisilicon,hi6220-usb"; 703 reg = <0x0 0xf72c0000 0x0 0x40000>; 704 phys = <&usb_phy>; 705 phy-names = "usb2-phy"; 706 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 707 clock-names = "otg"; 708 dr_mode = "otg"; 709 g-use-dma; 710 g-rx-fifo-size = <512>; 711 g-np-tx-fifo-size = <128>; 712 g-tx-fifo-size = <128 128 128 128 128 128>; 713 interrupts = <0 77 0x4>; 714 }; 715 716 mailbox: mailbox@f7510000 { 717 compatible = "hisilicon,hi6220-mbox"; 718 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 719 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 720 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 721 #mbox-cells = <3>; 722 }; 723 724 dwmmc_0: dwmmc0@f723d000 { 725 compatible = "hisilicon,hi6220-dw-mshc"; 726 num-slots = <0x1>; 727 cap-mmc-highspeed; 728 non-removable; 729 reg = <0x0 0xf723d000 0x0 0x1000>; 730 interrupts = <0x0 0x48 0x4>; 731 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; 732 clock-names = "ciu", "biu"; 733 bus-width = <0x8>; 734 vmmc-supply = <&ldo19>; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func 737 &emmc_cfg_func &emmc_rst_cfg_func>; 738 }; 739 740 dwmmc_1: dwmmc1@f723e000 { 741 compatible = "hisilicon,hi6220-dw-mshc"; 742 num-slots = <0x1>; 743 card-detect-delay = <200>; 744 hisilicon,peripheral-syscon = <&ao_ctrl>; 745 cap-sd-highspeed; 746 reg = <0x0 0xf723e000 0x0 0x1000>; 747 interrupts = <0x0 0x49 0x4>; 748 #address-cells = <0x1>; 749 #size-cells = <0x0>; 750 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; 751 clock-names = "ciu", "biu"; 752 vqmmc-supply = <&ldo7>; 753 vmmc-supply = <&ldo10>; 754 bus-width = <0x4>; 755 disable-wp; 756 cd-gpios = <&gpio1 0 1>; 757 pinctrl-names = "default", "idle"; 758 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; 759 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; 760 }; 761 762 dwmmc_2: dwmmc2@f723f000 { 763 compatible = "hisilicon,hi6220-dw-mshc"; 764 num-slots = <0x1>; 765 reg = <0x0 0xf723f000 0x0 0x1000>; 766 interrupts = <0x0 0x4a 0x4>; 767 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; 768 clock-names = "ciu", "biu"; 769 bus-width = <0x4>; 770 broken-cd; 771 pinctrl-names = "default", "idle"; 772 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; 773 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; 774 }; 775 776 tsensor: tsensor@0,f7030700 { 777 compatible = "hisilicon,tsensor"; 778 reg = <0x0 0xf7030700 0x0 0x1000>; 779 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&sys_ctrl 22>; 781 clock-names = "thermal_clk"; 782 #thermal-sensor-cells = <1>; 783 }; 784 }; 785}; 786