1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi6220 SoC 4 * 5 * Copyright (C) 2015, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/hisi,hi6220-resets.h> 10#include <dt-bindings/clock/hi6220-clock.h> 11#include <dt-bindings/pinctrl/hisi.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "hisilicon,hi6220"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 psci { 21 compatible = "arm,psci-0.2"; 22 method = "smc"; 23 }; 24 25 cpus { 26 #address-cells = <2>; 27 #size-cells = <0>; 28 29 cpu-map { 30 cluster0 { 31 core0 { 32 cpu = <&cpu0>; 33 }; 34 core1 { 35 cpu = <&cpu1>; 36 }; 37 core2 { 38 cpu = <&cpu2>; 39 }; 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 }; 44 cluster1 { 45 core0 { 46 cpu = <&cpu4>; 47 }; 48 core1 { 49 cpu = <&cpu5>; 50 }; 51 core2 { 52 cpu = <&cpu6>; 53 }; 54 core3 { 55 cpu = <&cpu7>; 56 }; 57 }; 58 }; 59 60 idle-states { 61 entry-method = "psci"; 62 63 CPU_SLEEP: cpu-sleep { 64 compatible = "arm,idle-state"; 65 local-timer-stop; 66 arm,psci-suspend-param = <0x0010000>; 67 entry-latency-us = <700>; 68 exit-latency-us = <250>; 69 min-residency-us = <1000>; 70 }; 71 72 CLUSTER_SLEEP: cluster-sleep { 73 compatible = "arm,idle-state"; 74 local-timer-stop; 75 arm,psci-suspend-param = <0x1010000>; 76 entry-latency-us = <1000>; 77 exit-latency-us = <700>; 78 min-residency-us = <2700>; 79 wakeup-latency-us = <1500>; 80 }; 81 }; 82 83 cpu0: cpu@0 { 84 compatible = "arm,cortex-a53", "arm,armv8"; 85 device_type = "cpu"; 86 reg = <0x0 0x0>; 87 enable-method = "psci"; 88 next-level-cache = <&CLUSTER0_L2>; 89 clocks = <&stub_clock 0>; 90 operating-points-v2 = <&cpu_opp_table>; 91 #cooling-cells = <2>; /* min followed by max */ 92 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 93 dynamic-power-coefficient = <311>; 94 }; 95 96 cpu1: cpu@1 { 97 compatible = "arm,cortex-a53", "arm,armv8"; 98 device_type = "cpu"; 99 reg = <0x0 0x1>; 100 enable-method = "psci"; 101 next-level-cache = <&CLUSTER0_L2>; 102 operating-points-v2 = <&cpu_opp_table>; 103 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 104 }; 105 106 cpu2: cpu@2 { 107 compatible = "arm,cortex-a53", "arm,armv8"; 108 device_type = "cpu"; 109 reg = <0x0 0x2>; 110 enable-method = "psci"; 111 next-level-cache = <&CLUSTER0_L2>; 112 operating-points-v2 = <&cpu_opp_table>; 113 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 114 }; 115 116 cpu3: cpu@3 { 117 compatible = "arm,cortex-a53", "arm,armv8"; 118 device_type = "cpu"; 119 reg = <0x0 0x3>; 120 enable-method = "psci"; 121 next-level-cache = <&CLUSTER0_L2>; 122 operating-points-v2 = <&cpu_opp_table>; 123 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 124 }; 125 126 cpu4: cpu@100 { 127 compatible = "arm,cortex-a53", "arm,armv8"; 128 device_type = "cpu"; 129 reg = <0x0 0x100>; 130 enable-method = "psci"; 131 next-level-cache = <&CLUSTER1_L2>; 132 operating-points-v2 = <&cpu_opp_table>; 133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 134 }; 135 136 cpu5: cpu@101 { 137 compatible = "arm,cortex-a53", "arm,armv8"; 138 device_type = "cpu"; 139 reg = <0x0 0x101>; 140 enable-method = "psci"; 141 next-level-cache = <&CLUSTER1_L2>; 142 operating-points-v2 = <&cpu_opp_table>; 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 144 }; 145 146 cpu6: cpu@102 { 147 compatible = "arm,cortex-a53", "arm,armv8"; 148 device_type = "cpu"; 149 reg = <0x0 0x102>; 150 enable-method = "psci"; 151 next-level-cache = <&CLUSTER1_L2>; 152 operating-points-v2 = <&cpu_opp_table>; 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 154 }; 155 156 cpu7: cpu@103 { 157 compatible = "arm,cortex-a53", "arm,armv8"; 158 device_type = "cpu"; 159 reg = <0x0 0x103>; 160 enable-method = "psci"; 161 next-level-cache = <&CLUSTER1_L2>; 162 operating-points-v2 = <&cpu_opp_table>; 163 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 164 }; 165 166 CLUSTER0_L2: l2-cache0 { 167 compatible = "cache"; 168 }; 169 170 CLUSTER1_L2: l2-cache1 { 171 compatible = "cache"; 172 }; 173 }; 174 175 cpu_opp_table: cpu_opp_table { 176 compatible = "operating-points-v2"; 177 opp-shared; 178 179 opp00 { 180 opp-hz = /bits/ 64 <208000000>; 181 opp-microvolt = <1040000>; 182 clock-latency-ns = <500000>; 183 }; 184 opp01 { 185 opp-hz = /bits/ 64 <432000000>; 186 opp-microvolt = <1040000>; 187 clock-latency-ns = <500000>; 188 }; 189 opp02 { 190 opp-hz = /bits/ 64 <729000000>; 191 opp-microvolt = <1090000>; 192 clock-latency-ns = <500000>; 193 }; 194 opp03 { 195 opp-hz = /bits/ 64 <960000000>; 196 opp-microvolt = <1180000>; 197 clock-latency-ns = <500000>; 198 }; 199 opp04 { 200 opp-hz = /bits/ 64 <1200000000>; 201 opp-microvolt = <1330000>; 202 clock-latency-ns = <500000>; 203 }; 204 }; 205 206 gic: interrupt-controller@f6801000 { 207 compatible = "arm,gic-400"; 208 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 209 <0x0 0xf6802000 0 0x2000>, /* GICC */ 210 <0x0 0xf6804000 0 0x2000>, /* GICH */ 211 <0x0 0xf6806000 0 0x2000>; /* GICV */ 212 #address-cells = <0>; 213 #interrupt-cells = <3>; 214 interrupt-controller; 215 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 216 }; 217 218 timer { 219 compatible = "arm,armv8-timer"; 220 interrupt-parent = <&gic>; 221 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 222 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 223 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 224 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 225 }; 226 227 soc { 228 compatible = "simple-bus"; 229 #address-cells = <2>; 230 #size-cells = <2>; 231 ranges; 232 233 sram: sram@fff80000 { 234 compatible = "hisilicon,hi6220-sramctrl", "syscon"; 235 reg = <0x0 0xfff80000 0x0 0x12000>; 236 }; 237 238 ao_ctrl: ao_ctrl@f7800000 { 239 compatible = "hisilicon,hi6220-aoctrl", "syscon"; 240 reg = <0x0 0xf7800000 0x0 0x2000>; 241 #clock-cells = <1>; 242 }; 243 244 sys_ctrl: sys_ctrl@f7030000 { 245 compatible = "hisilicon,hi6220-sysctrl", "syscon"; 246 reg = <0x0 0xf7030000 0x0 0x2000>; 247 #clock-cells = <1>; 248 #reset-cells = <1>; 249 }; 250 251 media_ctrl: media_ctrl@f4410000 { 252 compatible = "hisilicon,hi6220-mediactrl", "syscon"; 253 reg = <0x0 0xf4410000 0x0 0x1000>; 254 #clock-cells = <1>; 255 #reset-cells = <1>; 256 }; 257 258 pm_ctrl: pm_ctrl@f7032000 { 259 compatible = "hisilicon,hi6220-pmctrl", "syscon"; 260 reg = <0x0 0xf7032000 0x0 0x1000>; 261 #clock-cells = <1>; 262 }; 263 264 acpu_sctrl: acpu_sctrl@f6504000 { 265 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; 266 reg = <0x0 0xf6504000 0x0 0x1000>; 267 #clock-cells = <1>; 268 }; 269 270 medianoc_ade: medianoc_ade@f4520000 { 271 compatible = "syscon"; 272 reg = <0x0 0xf4520000 0x0 0x4000>; 273 }; 274 275 stub_clock: stub_clock { 276 compatible = "hisilicon,hi6220-stub-clk"; 277 hisilicon,hi6220-clk-sram = <&sram>; 278 #clock-cells = <1>; 279 mbox-names = "mbox-tx"; 280 mboxes = <&mailbox 1 0 11>; 281 }; 282 283 uart0: uart@f8015000 { /* console */ 284 compatible = "arm,pl011", "arm,primecell"; 285 reg = <0x0 0xf8015000 0x0 0x1000>; 286 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&ao_ctrl HI6220_UART0_PCLK>, 288 <&ao_ctrl HI6220_UART0_PCLK>; 289 clock-names = "uartclk", "apb_pclk"; 290 }; 291 292 uart1: uart@f7111000 { 293 compatible = "arm,pl011", "arm,primecell"; 294 reg = <0x0 0xf7111000 0x0 0x1000>; 295 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&sys_ctrl HI6220_UART1_PCLK>, 297 <&sys_ctrl HI6220_UART1_PCLK>; 298 clock-names = "uartclk", "apb_pclk"; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; 301 status = "disabled"; 302 }; 303 304 uart2: uart@f7112000 { 305 compatible = "arm,pl011", "arm,primecell"; 306 reg = <0x0 0xf7112000 0x0 0x1000>; 307 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&sys_ctrl HI6220_UART2_PCLK>, 309 <&sys_ctrl HI6220_UART2_PCLK>; 310 clock-names = "uartclk", "apb_pclk"; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 313 status = "disabled"; 314 }; 315 316 uart3: uart@f7113000 { 317 compatible = "arm,pl011", "arm,primecell"; 318 reg = <0x0 0xf7113000 0x0 0x1000>; 319 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&sys_ctrl HI6220_UART3_PCLK>, 321 <&sys_ctrl HI6220_UART3_PCLK>; 322 clock-names = "uartclk", "apb_pclk"; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 325 status = "disabled"; 326 }; 327 328 uart4: uart@f7114000 { 329 compatible = "arm,pl011", "arm,primecell"; 330 reg = <0x0 0xf7114000 0x0 0x1000>; 331 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&sys_ctrl HI6220_UART4_PCLK>, 333 <&sys_ctrl HI6220_UART4_PCLK>; 334 clock-names = "uartclk", "apb_pclk"; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 337 status = "disabled"; 338 }; 339 340 dma0: dma@f7370000 { 341 compatible = "hisilicon,k3-dma-1.0"; 342 reg = <0x0 0xf7370000 0x0 0x1000>; 343 #dma-cells = <1>; 344 dma-channels = <15>; 345 dma-requests = <32>; 346 interrupts = <0 84 4>; 347 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; 348 dma-no-cci; 349 dma-type = "hi6220_dma"; 350 status = "ok"; 351 }; 352 353 dual_timer0: timer@f8008000 { 354 compatible = "arm,sp804", "arm,primecell"; 355 reg = <0x0 0xf8008000 0x0 0x1000>; 356 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, 359 <&ao_ctrl HI6220_TIMER0_PCLK>, 360 <&ao_ctrl HI6220_TIMER0_PCLK>; 361 clock-names = "timer1", "timer2", "apb_pclk"; 362 }; 363 364 rtc0: rtc@f8003000 { 365 compatible = "arm,pl031", "arm,primecell"; 366 reg = <0x0 0xf8003000 0x0 0x1000>; 367 interrupts = <0 12 4>; 368 clocks = <&ao_ctrl HI6220_RTC0_PCLK>; 369 clock-names = "apb_pclk"; 370 }; 371 372 rtc1: rtc@f8004000 { 373 compatible = "arm,pl031", "arm,primecell"; 374 reg = <0x0 0xf8004000 0x0 0x1000>; 375 interrupts = <0 8 4>; 376 clocks = <&ao_ctrl HI6220_RTC1_PCLK>; 377 clock-names = "apb_pclk"; 378 }; 379 380 pmx0: pinmux@f7010000 { 381 compatible = "pinctrl-single"; 382 reg = <0x0 0xf7010000 0x0 0x27c>; 383 #address-cells = <1>; 384 #size-cells = <1>; 385 #pinctrl-cells = <1>; 386 #gpio-range-cells = <3>; 387 pinctrl-single,register-width = <32>; 388 pinctrl-single,function-mask = <7>; 389 pinctrl-single,gpio-range = < 390 &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 391 &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 392 &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 393 &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 394 &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 395 &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 396 &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 397 &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 398 &range 0 1 MUX_M1 /* gpio 10: [0] */ 399 &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 400 &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 401 &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 402 &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 403 &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 404 &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 405 &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 406 &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 407 &range 122 1 MUX_M1 /* gpio 15: [6] */ 408 &range 126 1 MUX_M1 /* gpio 15: [7] */ 409 &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 410 &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 411 &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 412 &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 413 >; 414 range: gpio-range { 415 #pinctrl-single,gpio-range-cells = <3>; 416 }; 417 }; 418 419 pmx1: pinmux@f7010800 { 420 compatible = "pinconf-single"; 421 reg = <0x0 0xf7010800 0x0 0x28c>; 422 #address-cells = <1>; 423 #size-cells = <1>; 424 #pinctrl-cells = <1>; 425 pinctrl-single,register-width = <32>; 426 }; 427 428 pmx2: pinmux@f8001800 { 429 compatible = "pinconf-single"; 430 reg = <0x0 0xf8001800 0x0 0x78>; 431 #address-cells = <1>; 432 #size-cells = <1>; 433 #pinctrl-cells = <1>; 434 pinctrl-single,register-width = <32>; 435 }; 436 437 gpio0: gpio@f8011000 { 438 compatible = "arm,pl061", "arm,primecell"; 439 reg = <0x0 0xf8011000 0x0 0x1000>; 440 interrupts = <0 52 0x4>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 clocks = <&ao_ctrl 2>; 446 clock-names = "apb_pclk"; 447 }; 448 449 gpio1: gpio@f8012000 { 450 compatible = "arm,pl061", "arm,primecell"; 451 reg = <0x0 0xf8012000 0x0 0x1000>; 452 interrupts = <0 53 0x4>; 453 gpio-controller; 454 #gpio-cells = <2>; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 clocks = <&ao_ctrl 2>; 458 clock-names = "apb_pclk"; 459 }; 460 461 gpio2: gpio@f8013000 { 462 compatible = "arm,pl061", "arm,primecell"; 463 reg = <0x0 0xf8013000 0x0 0x1000>; 464 interrupts = <0 54 0x4>; 465 gpio-controller; 466 #gpio-cells = <2>; 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 clocks = <&ao_ctrl 2>; 470 clock-names = "apb_pclk"; 471 }; 472 473 gpio3: gpio@f8014000 { 474 compatible = "arm,pl061", "arm,primecell"; 475 reg = <0x0 0xf8014000 0x0 0x1000>; 476 interrupts = <0 55 0x4>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 gpio-ranges = <&pmx0 0 80 8>; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 clocks = <&ao_ctrl 2>; 483 clock-names = "apb_pclk"; 484 }; 485 486 gpio4: gpio@f7020000 { 487 compatible = "arm,pl061", "arm,primecell"; 488 reg = <0x0 0xf7020000 0x0 0x1000>; 489 interrupts = <0 56 0x4>; 490 gpio-controller; 491 #gpio-cells = <2>; 492 gpio-ranges = <&pmx0 0 88 8>; 493 interrupt-controller; 494 #interrupt-cells = <2>; 495 clocks = <&ao_ctrl 2>; 496 clock-names = "apb_pclk"; 497 }; 498 499 gpio5: gpio@f7021000 { 500 compatible = "arm,pl061", "arm,primecell"; 501 reg = <0x0 0xf7021000 0x0 0x1000>; 502 interrupts = <0 57 0x4>; 503 gpio-controller; 504 #gpio-cells = <2>; 505 gpio-ranges = <&pmx0 0 96 8>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 clocks = <&ao_ctrl 2>; 509 clock-names = "apb_pclk"; 510 }; 511 512 gpio6: gpio@f7022000 { 513 compatible = "arm,pl061", "arm,primecell"; 514 reg = <0x0 0xf7022000 0x0 0x1000>; 515 interrupts = <0 58 0x4>; 516 gpio-controller; 517 #gpio-cells = <2>; 518 gpio-ranges = <&pmx0 0 104 8>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 clocks = <&ao_ctrl 2>; 522 clock-names = "apb_pclk"; 523 }; 524 525 gpio7: gpio@f7023000 { 526 compatible = "arm,pl061", "arm,primecell"; 527 reg = <0x0 0xf7023000 0x0 0x1000>; 528 interrupts = <0 59 0x4>; 529 gpio-controller; 530 #gpio-cells = <2>; 531 gpio-ranges = <&pmx0 0 112 8>; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 clocks = <&ao_ctrl 2>; 535 clock-names = "apb_pclk"; 536 }; 537 538 gpio8: gpio@f7024000 { 539 compatible = "arm,pl061", "arm,primecell"; 540 reg = <0x0 0xf7024000 0x0 0x1000>; 541 interrupts = <0 60 0x4>; 542 gpio-controller; 543 #gpio-cells = <2>; 544 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 clocks = <&ao_ctrl 2>; 548 clock-names = "apb_pclk"; 549 }; 550 551 gpio9: gpio@f7025000 { 552 compatible = "arm,pl061", "arm,primecell"; 553 reg = <0x0 0xf7025000 0x0 0x1000>; 554 interrupts = <0 61 0x4>; 555 gpio-controller; 556 #gpio-cells = <2>; 557 gpio-ranges = <&pmx0 0 8 8>; 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 clocks = <&ao_ctrl 2>; 561 clock-names = "apb_pclk"; 562 }; 563 564 gpio10: gpio@f7026000 { 565 compatible = "arm,pl061", "arm,primecell"; 566 reg = <0x0 0xf7026000 0x0 0x1000>; 567 interrupts = <0 62 0x4>; 568 gpio-controller; 569 #gpio-cells = <2>; 570 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 clocks = <&ao_ctrl 2>; 574 clock-names = "apb_pclk"; 575 }; 576 577 gpio11: gpio@f7027000 { 578 compatible = "arm,pl061", "arm,primecell"; 579 reg = <0x0 0xf7027000 0x0 0x1000>; 580 interrupts = <0 63 0x4>; 581 gpio-controller; 582 #gpio-cells = <2>; 583 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 584 interrupt-controller; 585 #interrupt-cells = <2>; 586 clocks = <&ao_ctrl 2>; 587 clock-names = "apb_pclk"; 588 }; 589 590 gpio12: gpio@f7028000 { 591 compatible = "arm,pl061", "arm,primecell"; 592 reg = <0x0 0xf7028000 0x0 0x1000>; 593 interrupts = <0 64 0x4>; 594 gpio-controller; 595 #gpio-cells = <2>; 596 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 clocks = <&ao_ctrl 2>; 600 clock-names = "apb_pclk"; 601 }; 602 603 gpio13: gpio@f7029000 { 604 compatible = "arm,pl061", "arm,primecell"; 605 reg = <0x0 0xf7029000 0x0 0x1000>; 606 interrupts = <0 65 0x4>; 607 gpio-controller; 608 #gpio-cells = <2>; 609 gpio-ranges = <&pmx0 0 48 8>; 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 clocks = <&ao_ctrl 2>; 613 clock-names = "apb_pclk"; 614 }; 615 616 gpio14: gpio@f702a000 { 617 compatible = "arm,pl061", "arm,primecell"; 618 reg = <0x0 0xf702a000 0x0 0x1000>; 619 interrupts = <0 66 0x4>; 620 gpio-controller; 621 #gpio-cells = <2>; 622 gpio-ranges = <&pmx0 0 56 8>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 clocks = <&ao_ctrl 2>; 626 clock-names = "apb_pclk"; 627 }; 628 629 gpio15: gpio@f702b000 { 630 compatible = "arm,pl061", "arm,primecell"; 631 reg = <0x0 0xf702b000 0x0 0x1000>; 632 interrupts = <0 67 0x4>; 633 gpio-controller; 634 #gpio-cells = <2>; 635 gpio-ranges = < 636 &pmx0 0 74 6 637 &pmx0 6 122 1 638 &pmx0 7 126 1 639 >; 640 interrupt-controller; 641 #interrupt-cells = <2>; 642 clocks = <&ao_ctrl 2>; 643 clock-names = "apb_pclk"; 644 }; 645 646 gpio16: gpio@f702c000 { 647 compatible = "arm,pl061", "arm,primecell"; 648 reg = <0x0 0xf702c000 0x0 0x1000>; 649 interrupts = <0 68 0x4>; 650 gpio-controller; 651 #gpio-cells = <2>; 652 gpio-ranges = <&pmx0 0 127 8>; 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 clocks = <&ao_ctrl 2>; 656 clock-names = "apb_pclk"; 657 }; 658 659 gpio17: gpio@f702d000 { 660 compatible = "arm,pl061", "arm,primecell"; 661 reg = <0x0 0xf702d000 0x0 0x1000>; 662 interrupts = <0 69 0x4>; 663 gpio-controller; 664 #gpio-cells = <2>; 665 gpio-ranges = <&pmx0 0 135 8>; 666 interrupt-controller; 667 #interrupt-cells = <2>; 668 clocks = <&ao_ctrl 2>; 669 clock-names = "apb_pclk"; 670 }; 671 672 gpio18: gpio@f702e000 { 673 compatible = "arm,pl061", "arm,primecell"; 674 reg = <0x0 0xf702e000 0x0 0x1000>; 675 interrupts = <0 70 0x4>; 676 gpio-controller; 677 #gpio-cells = <2>; 678 gpio-ranges = <&pmx0 0 143 8>; 679 interrupt-controller; 680 #interrupt-cells = <2>; 681 clocks = <&ao_ctrl 2>; 682 clock-names = "apb_pclk"; 683 }; 684 685 gpio19: gpio@f702f000 { 686 compatible = "arm,pl061", "arm,primecell"; 687 reg = <0x0 0xf702f000 0x0 0x1000>; 688 interrupts = <0 71 0x4>; 689 gpio-controller; 690 #gpio-cells = <2>; 691 gpio-ranges = <&pmx0 0 151 8>; 692 interrupt-controller; 693 #interrupt-cells = <2>; 694 clocks = <&ao_ctrl 2>; 695 clock-names = "apb_pclk"; 696 }; 697 698 spi0: spi@f7106000 { 699 compatible = "arm,pl022", "arm,primecell"; 700 reg = <0x0 0xf7106000 0x0 0x1000>; 701 interrupts = <0 50 4>; 702 bus-id = <0>; 703 enable-dma = <0>; 704 clocks = <&sys_ctrl HI6220_SPI_CLK>; 705 clock-names = "apb_pclk"; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 708 num-cs = <1>; 709 cs-gpios = <&gpio6 2 0>; 710 status = "disabled"; 711 }; 712 713 i2c0: i2c@f7100000 { 714 compatible = "snps,designware-i2c"; 715 reg = <0x0 0xf7100000 0x0 0x1000>; 716 interrupts = <0 44 4>; 717 clocks = <&sys_ctrl HI6220_I2C0_CLK>; 718 i2c-sda-hold-time-ns = <300>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 721 status = "disabled"; 722 }; 723 724 i2c1: i2c@f7101000 { 725 compatible = "snps,designware-i2c"; 726 reg = <0x0 0xf7101000 0x0 0x1000>; 727 clocks = <&sys_ctrl HI6220_I2C1_CLK>; 728 interrupts = <0 45 4>; 729 i2c-sda-hold-time-ns = <300>; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 732 status = "disabled"; 733 }; 734 735 i2c2: i2c@f7102000 { 736 compatible = "snps,designware-i2c"; 737 reg = <0x0 0xf7102000 0x0 0x1000>; 738 clocks = <&sys_ctrl HI6220_I2C2_CLK>; 739 interrupts = <0 46 4>; 740 i2c-sda-hold-time-ns = <300>; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 743 status = "disabled"; 744 }; 745 746 usb_phy: usbphy { 747 compatible = "hisilicon,hi6220-usb-phy"; 748 #phy-cells = <0>; 749 phy-supply = <®_5v_hub>; 750 hisilicon,peripheral-syscon = <&sys_ctrl>; 751 }; 752 753 usb: usb@f72c0000 { 754 compatible = "hisilicon,hi6220-usb"; 755 reg = <0x0 0xf72c0000 0x0 0x40000>; 756 phys = <&usb_phy>; 757 phy-names = "usb2-phy"; 758 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 759 clock-names = "otg"; 760 dr_mode = "otg"; 761 g-rx-fifo-size = <512>; 762 g-np-tx-fifo-size = <128>; 763 g-tx-fifo-size = <128 128 128 128 128 128 128 128 764 16 16 16 16 16 16 16>; 765 interrupts = <0 77 0x4>; 766 }; 767 768 mailbox: mailbox@f7510000 { 769 compatible = "hisilicon,hi6220-mbox"; 770 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 771 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 772 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 773 #mbox-cells = <3>; 774 }; 775 776 dwmmc_0: dwmmc0@f723d000 { 777 compatible = "hisilicon,hi6220-dw-mshc"; 778 reg = <0x0 0xf723d000 0x0 0x1000>; 779 interrupts = <0x0 0x48 0x4>; 780 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; 781 clock-names = "ciu", "biu"; 782 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; 783 reset-names = "reset"; 784 pinctrl-names = "default"; 785 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func 786 &emmc_cfg_func &emmc_rst_cfg_func>; 787 }; 788 789 dwmmc_1: dwmmc1@f723e000 { 790 compatible = "hisilicon,hi6220-dw-mshc"; 791 hisilicon,peripheral-syscon = <&ao_ctrl>; 792 reg = <0x0 0xf723e000 0x0 0x1000>; 793 interrupts = <0x0 0x49 0x4>; 794 #address-cells = <0x1>; 795 #size-cells = <0x0>; 796 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; 797 clock-names = "ciu", "biu"; 798 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; 799 reset-names = "reset"; 800 pinctrl-names = "default", "idle"; 801 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; 802 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; 803 }; 804 805 dwmmc_2: dwmmc2@f723f000 { 806 compatible = "hisilicon,hi6220-dw-mshc"; 807 reg = <0x0 0xf723f000 0x0 0x1000>; 808 interrupts = <0x0 0x4a 0x4>; 809 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; 810 clock-names = "ciu", "biu"; 811 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; 812 reset-names = "reset"; 813 pinctrl-names = "default", "idle"; 814 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; 815 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; 816 }; 817 818 tsensor: tsensor@0,f7030700 { 819 compatible = "hisilicon,tsensor"; 820 reg = <0x0 0xf7030700 0x0 0x1000>; 821 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&sys_ctrl 22>; 823 clock-names = "thermal_clk"; 824 #thermal-sensor-cells = <1>; 825 }; 826 827 i2s0: i2s@f7118000{ 828 compatible = "hisilicon,hi6210-i2s"; 829 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ 830 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */ 831 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, 832 <&sys_ctrl HI6220_BBPPLL0_DIV>; 833 clock-names = "dacodec", "i2s-base"; 834 dmas = <&dma0 15 &dma0 14>; 835 dma-names = "rx", "tx"; 836 hisilicon,sysctrl-syscon = <&sys_ctrl>; 837 #sound-dai-cells = <1>; 838 }; 839 840 thermal-zones { 841 842 cls0: cls0 { 843 polling-delay = <1000>; 844 polling-delay-passive = <100>; 845 sustainable-power = <3326>; 846 847 /* sensor ID */ 848 thermal-sensors = <&tsensor 2>; 849 850 trips { 851 threshold: trip-point@0 { 852 temperature = <65000>; 853 hysteresis = <0>; 854 type = "passive"; 855 }; 856 857 target: trip-point@1 { 858 temperature = <75000>; 859 hysteresis = <0>; 860 type = "passive"; 861 }; 862 }; 863 864 cooling-maps { 865 map0 { 866 trip = <&target>; 867 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 868 }; 869 }; 870 }; 871 }; 872 873 ade: ade@f4100000 { 874 compatible = "hisilicon,hi6220-ade"; 875 reg = <0x0 0xf4100000 0x0 0x7800>; 876 reg-names = "ade_base"; 877 hisilicon,noc-syscon = <&medianoc_ade>; 878 resets = <&media_ctrl MEDIA_ADE>; 879 interrupts = <0 115 4>; /* ldi interrupt */ 880 881 clocks = <&media_ctrl HI6220_ADE_CORE>, 882 <&media_ctrl HI6220_CODEC_JPEG>, 883 <&media_ctrl HI6220_ADE_PIX_SRC>; 884 /*clock name*/ 885 clock-names = "clk_ade_core", 886 "clk_codec_jpeg", 887 "clk_ade_pix"; 888 889 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, 890 <&media_ctrl HI6220_CODEC_JPEG>; 891 assigned-clock-rates = <360000000>, <288000000>; 892 dma-coherent; 893 status = "disabled"; 894 895 port { 896 ade_out: endpoint { 897 remote-endpoint = <&dsi_in>; 898 }; 899 }; 900 }; 901 902 dsi: dsi@f4107800 { 903 compatible = "hisilicon,hi6220-dsi"; 904 reg = <0x0 0xf4107800 0x0 0x100>; 905 clocks = <&media_ctrl HI6220_DSI_PCLK>; 906 clock-names = "pclk"; 907 status = "disabled"; 908 909 ports { 910 #address-cells = <1>; 911 #size-cells = <0>; 912 913 /* 0 for input port */ 914 port@0 { 915 reg = <0>; 916 dsi_in: endpoint { 917 remote-endpoint = <&ade_out>; 918 }; 919 }; 920 }; 921 }; 922 923 debug@f6590000 { 924 compatible = "arm,coresight-cpu-debug","arm,primecell"; 925 reg = <0 0xf6590000 0 0x1000>; 926 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 927 clock-names = "apb_pclk"; 928 cpu = <&cpu0>; 929 }; 930 931 debug@f6592000 { 932 compatible = "arm,coresight-cpu-debug","arm,primecell"; 933 reg = <0 0xf6592000 0 0x1000>; 934 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 935 clock-names = "apb_pclk"; 936 cpu = <&cpu1>; 937 }; 938 939 debug@f6594000 { 940 compatible = "arm,coresight-cpu-debug","arm,primecell"; 941 reg = <0 0xf6594000 0 0x1000>; 942 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 943 clock-names = "apb_pclk"; 944 cpu = <&cpu2>; 945 }; 946 947 debug@f6596000 { 948 compatible = "arm,coresight-cpu-debug","arm,primecell"; 949 reg = <0 0xf6596000 0 0x1000>; 950 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 951 clock-names = "apb_pclk"; 952 cpu = <&cpu3>; 953 }; 954 955 debug@f65d0000 { 956 compatible = "arm,coresight-cpu-debug","arm,primecell"; 957 reg = <0 0xf65d0000 0 0x1000>; 958 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 959 clock-names = "apb_pclk"; 960 cpu = <&cpu4>; 961 }; 962 963 debug@f65d2000 { 964 compatible = "arm,coresight-cpu-debug","arm,primecell"; 965 reg = <0 0xf65d2000 0 0x1000>; 966 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 967 clock-names = "apb_pclk"; 968 cpu = <&cpu5>; 969 }; 970 971 debug@f65d4000 { 972 compatible = "arm,coresight-cpu-debug","arm,primecell"; 973 reg = <0 0xf65d4000 0 0x1000>; 974 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 975 clock-names = "apb_pclk"; 976 cpu = <&cpu6>; 977 }; 978 979 debug@f65d6000 { 980 compatible = "arm,coresight-cpu-debug","arm,primecell"; 981 reg = <0 0xf65d6000 0 0x1000>; 982 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 983 clock-names = "apb_pclk"; 984 cpu = <&cpu7>; 985 }; 986 }; 987}; 988 989#include "hi6220-coresight.dtsi" 990