1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 286e8f528SBintian Wang/* 386e8f528SBintian Wang * dts file for Hisilicon Hi6220 SoC 486e8f528SBintian Wang * 586e8f528SBintian Wang * Copyright (C) 2015, Hisilicon Ltd. 686e8f528SBintian Wang */ 786e8f528SBintian Wang 886e8f528SBintian Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 9339d00cbSXinliang Liu#include <dt-bindings/reset/hisi,hi6220-resets.h> 10a362ec8fSTyler Baker#include <dt-bindings/clock/hi6220-clock.h> 11379e9bf5SZhong Kaihua#include <dt-bindings/pinctrl/hisi.h> 12cd0b69ecSLeo Yan#include <dt-bindings/thermal/thermal.h> 1386e8f528SBintian Wang 1486e8f528SBintian Wang/ { 1586e8f528SBintian Wang compatible = "hisilicon,hi6220"; 1686e8f528SBintian Wang interrupt-parent = <&gic>; 1786e8f528SBintian Wang #address-cells = <2>; 1886e8f528SBintian Wang #size-cells = <2>; 1986e8f528SBintian Wang 2086e8f528SBintian Wang psci { 2186e8f528SBintian Wang compatible = "arm,psci-0.2"; 2286e8f528SBintian Wang method = "smc"; 2386e8f528SBintian Wang }; 2486e8f528SBintian Wang 2586e8f528SBintian Wang cpus { 2686e8f528SBintian Wang #address-cells = <2>; 2786e8f528SBintian Wang #size-cells = <0>; 2886e8f528SBintian Wang 2986e8f528SBintian Wang cpu-map { 3086e8f528SBintian Wang cluster0 { 3186e8f528SBintian Wang core0 { 3286e8f528SBintian Wang cpu = <&cpu0>; 3386e8f528SBintian Wang }; 3486e8f528SBintian Wang core1 { 3586e8f528SBintian Wang cpu = <&cpu1>; 3686e8f528SBintian Wang }; 3786e8f528SBintian Wang core2 { 3886e8f528SBintian Wang cpu = <&cpu2>; 3986e8f528SBintian Wang }; 4086e8f528SBintian Wang core3 { 4186e8f528SBintian Wang cpu = <&cpu3>; 4286e8f528SBintian Wang }; 4386e8f528SBintian Wang }; 4486e8f528SBintian Wang cluster1 { 4586e8f528SBintian Wang core0 { 4686e8f528SBintian Wang cpu = <&cpu4>; 4786e8f528SBintian Wang }; 4886e8f528SBintian Wang core1 { 4986e8f528SBintian Wang cpu = <&cpu5>; 5086e8f528SBintian Wang }; 5186e8f528SBintian Wang core2 { 5286e8f528SBintian Wang cpu = <&cpu6>; 5386e8f528SBintian Wang }; 5486e8f528SBintian Wang core3 { 5586e8f528SBintian Wang cpu = <&cpu7>; 5686e8f528SBintian Wang }; 5786e8f528SBintian Wang }; 5886e8f528SBintian Wang }; 5986e8f528SBintian Wang 6058fa29bfSLeo Yan idle-states { 6158fa29bfSLeo Yan entry-method = "psci"; 6258fa29bfSLeo Yan 6358fa29bfSLeo Yan CPU_SLEEP: cpu-sleep { 6458fa29bfSLeo Yan compatible = "arm,idle-state"; 6558fa29bfSLeo Yan local-timer-stop; 6658fa29bfSLeo Yan arm,psci-suspend-param = <0x0010000>; 6758fa29bfSLeo Yan entry-latency-us = <700>; 6858fa29bfSLeo Yan exit-latency-us = <250>; 6958fa29bfSLeo Yan min-residency-us = <1000>; 7058fa29bfSLeo Yan }; 7158fa29bfSLeo Yan 7258fa29bfSLeo Yan CLUSTER_SLEEP: cluster-sleep { 7358fa29bfSLeo Yan compatible = "arm,idle-state"; 7458fa29bfSLeo Yan local-timer-stop; 7558fa29bfSLeo Yan arm,psci-suspend-param = <0x1010000>; 7658fa29bfSLeo Yan entry-latency-us = <1000>; 7758fa29bfSLeo Yan exit-latency-us = <700>; 7858fa29bfSLeo Yan min-residency-us = <2700>; 7958fa29bfSLeo Yan wakeup-latency-us = <1500>; 8058fa29bfSLeo Yan }; 8158fa29bfSLeo Yan }; 8258fa29bfSLeo Yan 8386e8f528SBintian Wang cpu0: cpu@0 { 8486e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 8586e8f528SBintian Wang device_type = "cpu"; 8686e8f528SBintian Wang reg = <0x0 0x0>; 8786e8f528SBintian Wang enable-method = "psci"; 8864851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 8999860540SLeo Yan clocks = <&stub_clock 0>; 9099860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 9199860540SLeo Yan cooling-min-level = <4>; 9299860540SLeo Yan cooling-max-level = <0>; 9399860540SLeo Yan #cooling-cells = <2>; /* min followed by max */ 9458fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 95cd0b69ecSLeo Yan dynamic-power-coefficient = <311>; 9686e8f528SBintian Wang }; 9786e8f528SBintian Wang 9886e8f528SBintian Wang cpu1: cpu@1 { 9986e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 10086e8f528SBintian Wang device_type = "cpu"; 10186e8f528SBintian Wang reg = <0x0 0x1>; 10286e8f528SBintian Wang enable-method = "psci"; 10364851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 10499860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 10558fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 10686e8f528SBintian Wang }; 10786e8f528SBintian Wang 10886e8f528SBintian Wang cpu2: cpu@2 { 10986e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 11086e8f528SBintian Wang device_type = "cpu"; 11186e8f528SBintian Wang reg = <0x0 0x2>; 11286e8f528SBintian Wang enable-method = "psci"; 11364851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 11499860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 11558fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 11686e8f528SBintian Wang }; 11786e8f528SBintian Wang 11886e8f528SBintian Wang cpu3: cpu@3 { 11986e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 12086e8f528SBintian Wang device_type = "cpu"; 12186e8f528SBintian Wang reg = <0x0 0x3>; 12286e8f528SBintian Wang enable-method = "psci"; 12364851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 12499860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 12558fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 12686e8f528SBintian Wang }; 12786e8f528SBintian Wang 12886e8f528SBintian Wang cpu4: cpu@100 { 12986e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 13086e8f528SBintian Wang device_type = "cpu"; 13186e8f528SBintian Wang reg = <0x0 0x100>; 13286e8f528SBintian Wang enable-method = "psci"; 13364851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 13499860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 13558fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 13686e8f528SBintian Wang }; 13786e8f528SBintian Wang 13886e8f528SBintian Wang cpu5: cpu@101 { 13986e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 14086e8f528SBintian Wang device_type = "cpu"; 14186e8f528SBintian Wang reg = <0x0 0x101>; 14286e8f528SBintian Wang enable-method = "psci"; 14364851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 14499860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 14558fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 14686e8f528SBintian Wang }; 14786e8f528SBintian Wang 14886e8f528SBintian Wang cpu6: cpu@102 { 14986e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 15086e8f528SBintian Wang device_type = "cpu"; 15186e8f528SBintian Wang reg = <0x0 0x102>; 15286e8f528SBintian Wang enable-method = "psci"; 15364851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 15499860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 15558fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 15686e8f528SBintian Wang }; 15786e8f528SBintian Wang 15886e8f528SBintian Wang cpu7: cpu@103 { 15986e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 16086e8f528SBintian Wang device_type = "cpu"; 16186e8f528SBintian Wang reg = <0x0 0x103>; 16286e8f528SBintian Wang enable-method = "psci"; 16364851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 16499860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 16558fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 16686e8f528SBintian Wang }; 16764851603SLeo Yan 16864851603SLeo Yan CLUSTER0_L2: l2-cache0 { 16964851603SLeo Yan compatible = "cache"; 17064851603SLeo Yan }; 17164851603SLeo Yan 17264851603SLeo Yan CLUSTER1_L2: l2-cache1 { 17364851603SLeo Yan compatible = "cache"; 17464851603SLeo Yan }; 17586e8f528SBintian Wang }; 17686e8f528SBintian Wang 17799860540SLeo Yan cpu_opp_table: cpu_opp_table { 17899860540SLeo Yan compatible = "operating-points-v2"; 17999860540SLeo Yan opp-shared; 18099860540SLeo Yan 18199860540SLeo Yan opp00 { 18299860540SLeo Yan opp-hz = /bits/ 64 <208000000>; 18399860540SLeo Yan opp-microvolt = <1040000>; 18499860540SLeo Yan clock-latency-ns = <500000>; 18599860540SLeo Yan }; 18699860540SLeo Yan opp01 { 18799860540SLeo Yan opp-hz = /bits/ 64 <432000000>; 18899860540SLeo Yan opp-microvolt = <1040000>; 18999860540SLeo Yan clock-latency-ns = <500000>; 19099860540SLeo Yan }; 19199860540SLeo Yan opp02 { 19299860540SLeo Yan opp-hz = /bits/ 64 <729000000>; 19399860540SLeo Yan opp-microvolt = <1090000>; 19499860540SLeo Yan clock-latency-ns = <500000>; 19599860540SLeo Yan }; 19699860540SLeo Yan opp03 { 19799860540SLeo Yan opp-hz = /bits/ 64 <960000000>; 19899860540SLeo Yan opp-microvolt = <1180000>; 19999860540SLeo Yan clock-latency-ns = <500000>; 20099860540SLeo Yan }; 20199860540SLeo Yan opp04 { 20299860540SLeo Yan opp-hz = /bits/ 64 <1200000000>; 20399860540SLeo Yan opp-microvolt = <1330000>; 20499860540SLeo Yan clock-latency-ns = <500000>; 20599860540SLeo Yan }; 20699860540SLeo Yan }; 20799860540SLeo Yan 20886e8f528SBintian Wang gic: interrupt-controller@f6801000 { 20986e8f528SBintian Wang compatible = "arm,gic-400"; 21086e8f528SBintian Wang reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 21186e8f528SBintian Wang <0x0 0xf6802000 0 0x2000>, /* GICC */ 21286e8f528SBintian Wang <0x0 0xf6804000 0 0x2000>, /* GICH */ 21386e8f528SBintian Wang <0x0 0xf6806000 0 0x2000>; /* GICV */ 21486e8f528SBintian Wang #address-cells = <0>; 21586e8f528SBintian Wang #interrupt-cells = <3>; 21686e8f528SBintian Wang interrupt-controller; 21786e8f528SBintian Wang interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 21886e8f528SBintian Wang }; 21986e8f528SBintian Wang 22086e8f528SBintian Wang timer { 22186e8f528SBintian Wang compatible = "arm,armv8-timer"; 22286e8f528SBintian Wang interrupt-parent = <&gic>; 22386e8f528SBintian Wang interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 22486e8f528SBintian Wang <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 22586e8f528SBintian Wang <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 22686e8f528SBintian Wang <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 22786e8f528SBintian Wang }; 22886e8f528SBintian Wang 22986e8f528SBintian Wang soc { 23086e8f528SBintian Wang compatible = "simple-bus"; 23186e8f528SBintian Wang #address-cells = <2>; 23286e8f528SBintian Wang #size-cells = <2>; 23386e8f528SBintian Wang ranges; 23486e8f528SBintian Wang 23599860540SLeo Yan sram: sram@fff80000 { 23699860540SLeo Yan compatible = "hisilicon,hi6220-sramctrl", "syscon"; 23799860540SLeo Yan reg = <0x0 0xfff80000 0x0 0x12000>; 23899860540SLeo Yan }; 23999860540SLeo Yan 24086e8f528SBintian Wang ao_ctrl: ao_ctrl@f7800000 { 24186e8f528SBintian Wang compatible = "hisilicon,hi6220-aoctrl", "syscon"; 24286e8f528SBintian Wang reg = <0x0 0xf7800000 0x0 0x2000>; 24386e8f528SBintian Wang #clock-cells = <1>; 24486e8f528SBintian Wang }; 24586e8f528SBintian Wang 24686e8f528SBintian Wang sys_ctrl: sys_ctrl@f7030000 { 24786e8f528SBintian Wang compatible = "hisilicon,hi6220-sysctrl", "syscon"; 24886e8f528SBintian Wang reg = <0x0 0xf7030000 0x0 0x2000>; 24986e8f528SBintian Wang #clock-cells = <1>; 2503e14cd4cSChen Feng #reset-cells = <1>; 25186e8f528SBintian Wang }; 25286e8f528SBintian Wang 25386e8f528SBintian Wang media_ctrl: media_ctrl@f4410000 { 25486e8f528SBintian Wang compatible = "hisilicon,hi6220-mediactrl", "syscon"; 25586e8f528SBintian Wang reg = <0x0 0xf4410000 0x0 0x1000>; 25686e8f528SBintian Wang #clock-cells = <1>; 257339d00cbSXinliang Liu #reset-cells = <1>; 25886e8f528SBintian Wang }; 25986e8f528SBintian Wang 26086e8f528SBintian Wang pm_ctrl: pm_ctrl@f7032000 { 26186e8f528SBintian Wang compatible = "hisilicon,hi6220-pmctrl", "syscon"; 26286e8f528SBintian Wang reg = <0x0 0xf7032000 0x0 0x1000>; 26386e8f528SBintian Wang #clock-cells = <1>; 26486e8f528SBintian Wang }; 26586e8f528SBintian Wang 26694d2d94bSZhangfei Gao acpu_sctrl: acpu_sctrl@f6504000 { 26794d2d94bSZhangfei Gao compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; 26894d2d94bSZhangfei Gao reg = <0x0 0xf6504000 0x0 0x1000>; 26994d2d94bSZhangfei Gao #clock-cells = <1>; 27094d2d94bSZhangfei Gao }; 27194d2d94bSZhangfei Gao 2723814b61bSXinliang Liu medianoc_ade: medianoc_ade@f4520000 { 2733814b61bSXinliang Liu compatible = "syscon"; 2743814b61bSXinliang Liu reg = <0x0 0xf4520000 0x0 0x4000>; 2753814b61bSXinliang Liu }; 2763814b61bSXinliang Liu 27799860540SLeo Yan stub_clock: stub_clock { 27899860540SLeo Yan compatible = "hisilicon,hi6220-stub-clk"; 27999860540SLeo Yan hisilicon,hi6220-clk-sram = <&sram>; 28099860540SLeo Yan #clock-cells = <1>; 28199860540SLeo Yan mbox-names = "mbox-tx"; 28299860540SLeo Yan mboxes = <&mailbox 1 0 11>; 28399860540SLeo Yan }; 28499860540SLeo Yan 28586e8f528SBintian Wang uart0: uart@f8015000 { /* console */ 28686e8f528SBintian Wang compatible = "arm,pl011", "arm,primecell"; 28786e8f528SBintian Wang reg = <0x0 0xf8015000 0x0 0x1000>; 28886e8f528SBintian Wang interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 289a362ec8fSTyler Baker clocks = <&ao_ctrl HI6220_UART0_PCLK>, 290a362ec8fSTyler Baker <&ao_ctrl HI6220_UART0_PCLK>; 29186e8f528SBintian Wang clock-names = "uartclk", "apb_pclk"; 29286e8f528SBintian Wang }; 293a362ec8fSTyler Baker 294a362ec8fSTyler Baker uart1: uart@f7111000 { 295a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 296a362ec8fSTyler Baker reg = <0x0 0xf7111000 0x0 0x1000>; 297a362ec8fSTyler Baker interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 298a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART1_PCLK>, 299a362ec8fSTyler Baker <&sys_ctrl HI6220_UART1_PCLK>; 300a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 301c2aad932SGuodong Xu pinctrl-names = "default"; 302c2aad932SGuodong Xu pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; 303a362ec8fSTyler Baker status = "disabled"; 304a362ec8fSTyler Baker }; 305a362ec8fSTyler Baker 306a362ec8fSTyler Baker uart2: uart@f7112000 { 307a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 308a362ec8fSTyler Baker reg = <0x0 0xf7112000 0x0 0x1000>; 309a362ec8fSTyler Baker interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 310a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART2_PCLK>, 311a362ec8fSTyler Baker <&sys_ctrl HI6220_UART2_PCLK>; 312a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 313c2aad932SGuodong Xu pinctrl-names = "default"; 314c2aad932SGuodong Xu pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 315a362ec8fSTyler Baker status = "disabled"; 316a362ec8fSTyler Baker }; 317a362ec8fSTyler Baker 318a362ec8fSTyler Baker uart3: uart@f7113000 { 319a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 320a362ec8fSTyler Baker reg = <0x0 0xf7113000 0x0 0x1000>; 321a362ec8fSTyler Baker interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 322a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART3_PCLK>, 323a362ec8fSTyler Baker <&sys_ctrl HI6220_UART3_PCLK>; 324a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 325c2aad932SGuodong Xu pinctrl-names = "default"; 326c2aad932SGuodong Xu pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 327c2aad932SGuodong Xu status = "disabled"; 328a362ec8fSTyler Baker }; 329a362ec8fSTyler Baker 330a362ec8fSTyler Baker uart4: uart@f7114000 { 331a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 332a362ec8fSTyler Baker reg = <0x0 0xf7114000 0x0 0x1000>; 333a362ec8fSTyler Baker interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 334a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART4_PCLK>, 335a362ec8fSTyler Baker <&sys_ctrl HI6220_UART4_PCLK>; 336a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 337c2aad932SGuodong Xu pinctrl-names = "default"; 338c2aad932SGuodong Xu pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 339a362ec8fSTyler Baker status = "disabled"; 340a362ec8fSTyler Baker }; 3419e927031SLeo Yan 3420cf6a8e2SJohn Stultz dma0: dma@f7370000 { 3430cf6a8e2SJohn Stultz compatible = "hisilicon,k3-dma-1.0"; 3440cf6a8e2SJohn Stultz reg = <0x0 0xf7370000 0x0 0x1000>; 3450cf6a8e2SJohn Stultz #dma-cells = <1>; 3460cf6a8e2SJohn Stultz dma-channels = <15>; 3470cf6a8e2SJohn Stultz dma-requests = <32>; 3480cf6a8e2SJohn Stultz interrupts = <0 84 4>; 3490cf6a8e2SJohn Stultz clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; 3500cf6a8e2SJohn Stultz dma-no-cci; 3510cf6a8e2SJohn Stultz dma-type = "hi6220_dma"; 3520cf6a8e2SJohn Stultz status = "ok"; 3530cf6a8e2SJohn Stultz }; 3540cf6a8e2SJohn Stultz 3559e927031SLeo Yan dual_timer0: timer@f8008000 { 3569e927031SLeo Yan compatible = "arm,sp804", "arm,primecell"; 3579e927031SLeo Yan reg = <0x0 0xf8008000 0x0 0x1000>; 3589e927031SLeo Yan interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 3599e927031SLeo Yan <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 3609e927031SLeo Yan clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, 3619e927031SLeo Yan <&ao_ctrl HI6220_TIMER0_PCLK>, 3629e927031SLeo Yan <&ao_ctrl HI6220_TIMER0_PCLK>; 3639e927031SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 3649e927031SLeo Yan }; 365f2bfacf9SZhong Kaihua 366810bd15fSZhangfei Gao rtc0: rtc@f8003000 { 367810bd15fSZhangfei Gao compatible = "arm,pl031", "arm,primecell"; 368810bd15fSZhangfei Gao reg = <0x0 0xf8003000 0x0 0x1000>; 369810bd15fSZhangfei Gao interrupts = <0 12 4>; 370810bd15fSZhangfei Gao clocks = <&ao_ctrl HI6220_RTC0_PCLK>; 371810bd15fSZhangfei Gao clock-names = "apb_pclk"; 372810bd15fSZhangfei Gao }; 373810bd15fSZhangfei Gao 374810bd15fSZhangfei Gao rtc1: rtc@f8004000 { 375810bd15fSZhangfei Gao compatible = "arm,pl031", "arm,primecell"; 376810bd15fSZhangfei Gao reg = <0x0 0xf8004000 0x0 0x1000>; 377810bd15fSZhangfei Gao interrupts = <0 8 4>; 378810bd15fSZhangfei Gao clocks = <&ao_ctrl HI6220_RTC1_PCLK>; 379810bd15fSZhangfei Gao clock-names = "apb_pclk"; 380810bd15fSZhangfei Gao }; 381810bd15fSZhangfei Gao 382379e9bf5SZhong Kaihua pmx0: pinmux@f7010000 { 383379e9bf5SZhong Kaihua compatible = "pinctrl-single"; 384379e9bf5SZhong Kaihua reg = <0x0 0xf7010000 0x0 0x27c>; 385379e9bf5SZhong Kaihua #address-cells = <1>; 386379e9bf5SZhong Kaihua #size-cells = <1>; 387be76fd31STony Lindgren #pinctrl-cells = <1>; 388379e9bf5SZhong Kaihua #gpio-range-cells = <3>; 389379e9bf5SZhong Kaihua pinctrl-single,register-width = <32>; 390379e9bf5SZhong Kaihua pinctrl-single,function-mask = <7>; 391379e9bf5SZhong Kaihua pinctrl-single,gpio-range = < 392379e9bf5SZhong Kaihua &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 393379e9bf5SZhong Kaihua &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 394379e9bf5SZhong Kaihua &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 395379e9bf5SZhong Kaihua &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 396379e9bf5SZhong Kaihua &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 397379e9bf5SZhong Kaihua &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 398379e9bf5SZhong Kaihua &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 399379e9bf5SZhong Kaihua &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 400379e9bf5SZhong Kaihua &range 0 1 MUX_M1 /* gpio 10: [0] */ 401379e9bf5SZhong Kaihua &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 402379e9bf5SZhong Kaihua &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 403379e9bf5SZhong Kaihua &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 404379e9bf5SZhong Kaihua &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 405379e9bf5SZhong Kaihua &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 406379e9bf5SZhong Kaihua &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 407379e9bf5SZhong Kaihua &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 408379e9bf5SZhong Kaihua &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 409379e9bf5SZhong Kaihua &range 122 1 MUX_M1 /* gpio 15: [6] */ 410379e9bf5SZhong Kaihua &range 126 1 MUX_M1 /* gpio 15: [7] */ 411379e9bf5SZhong Kaihua &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 412379e9bf5SZhong Kaihua &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 413379e9bf5SZhong Kaihua &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 414379e9bf5SZhong Kaihua &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 415379e9bf5SZhong Kaihua >; 416379e9bf5SZhong Kaihua range: gpio-range { 417379e9bf5SZhong Kaihua #pinctrl-single,gpio-range-cells = <3>; 418379e9bf5SZhong Kaihua }; 419379e9bf5SZhong Kaihua }; 420379e9bf5SZhong Kaihua 421379e9bf5SZhong Kaihua pmx1: pinmux@f7010800 { 422379e9bf5SZhong Kaihua compatible = "pinconf-single"; 423379e9bf5SZhong Kaihua reg = <0x0 0xf7010800 0x0 0x28c>; 424379e9bf5SZhong Kaihua #address-cells = <1>; 425379e9bf5SZhong Kaihua #size-cells = <1>; 426be76fd31STony Lindgren #pinctrl-cells = <1>; 427379e9bf5SZhong Kaihua pinctrl-single,register-width = <32>; 428379e9bf5SZhong Kaihua }; 429379e9bf5SZhong Kaihua 430379e9bf5SZhong Kaihua pmx2: pinmux@f8001800 { 431379e9bf5SZhong Kaihua compatible = "pinconf-single"; 432379e9bf5SZhong Kaihua reg = <0x0 0xf8001800 0x0 0x78>; 433379e9bf5SZhong Kaihua #address-cells = <1>; 434379e9bf5SZhong Kaihua #size-cells = <1>; 435be76fd31STony Lindgren #pinctrl-cells = <1>; 436379e9bf5SZhong Kaihua pinctrl-single,register-width = <32>; 437379e9bf5SZhong Kaihua }; 438379e9bf5SZhong Kaihua 439f2bfacf9SZhong Kaihua gpio0: gpio@f8011000 { 440f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 441f2bfacf9SZhong Kaihua reg = <0x0 0xf8011000 0x0 0x1000>; 442f2bfacf9SZhong Kaihua interrupts = <0 52 0x4>; 443f2bfacf9SZhong Kaihua gpio-controller; 444f2bfacf9SZhong Kaihua #gpio-cells = <2>; 445f2bfacf9SZhong Kaihua interrupt-controller; 446f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 447f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 448f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 449f2bfacf9SZhong Kaihua }; 450f2bfacf9SZhong Kaihua 451f2bfacf9SZhong Kaihua gpio1: gpio@f8012000 { 452f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 453f2bfacf9SZhong Kaihua reg = <0x0 0xf8012000 0x0 0x1000>; 454f2bfacf9SZhong Kaihua interrupts = <0 53 0x4>; 455f2bfacf9SZhong Kaihua gpio-controller; 456f2bfacf9SZhong Kaihua #gpio-cells = <2>; 457f2bfacf9SZhong Kaihua interrupt-controller; 458f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 459f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 460f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 461f2bfacf9SZhong Kaihua }; 462f2bfacf9SZhong Kaihua 463f2bfacf9SZhong Kaihua gpio2: gpio@f8013000 { 464f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 465f2bfacf9SZhong Kaihua reg = <0x0 0xf8013000 0x0 0x1000>; 466f2bfacf9SZhong Kaihua interrupts = <0 54 0x4>; 467f2bfacf9SZhong Kaihua gpio-controller; 468f2bfacf9SZhong Kaihua #gpio-cells = <2>; 469f2bfacf9SZhong Kaihua interrupt-controller; 470f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 471f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 472f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 473f2bfacf9SZhong Kaihua }; 474f2bfacf9SZhong Kaihua 475f2bfacf9SZhong Kaihua gpio3: gpio@f8014000 { 476f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 477f2bfacf9SZhong Kaihua reg = <0x0 0xf8014000 0x0 0x1000>; 478f2bfacf9SZhong Kaihua interrupts = <0 55 0x4>; 479f2bfacf9SZhong Kaihua gpio-controller; 480f2bfacf9SZhong Kaihua #gpio-cells = <2>; 481379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 80 8>; 482f2bfacf9SZhong Kaihua interrupt-controller; 483f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 484f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 485f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 486f2bfacf9SZhong Kaihua }; 487f2bfacf9SZhong Kaihua 488f2bfacf9SZhong Kaihua gpio4: gpio@f7020000 { 489f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 490f2bfacf9SZhong Kaihua reg = <0x0 0xf7020000 0x0 0x1000>; 491f2bfacf9SZhong Kaihua interrupts = <0 56 0x4>; 492f2bfacf9SZhong Kaihua gpio-controller; 493f2bfacf9SZhong Kaihua #gpio-cells = <2>; 494379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 88 8>; 495f2bfacf9SZhong Kaihua interrupt-controller; 496f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 497f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 498f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 499f2bfacf9SZhong Kaihua }; 500f2bfacf9SZhong Kaihua 501f2bfacf9SZhong Kaihua gpio5: gpio@f7021000 { 502f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 503f2bfacf9SZhong Kaihua reg = <0x0 0xf7021000 0x0 0x1000>; 504f2bfacf9SZhong Kaihua interrupts = <0 57 0x4>; 505f2bfacf9SZhong Kaihua gpio-controller; 506f2bfacf9SZhong Kaihua #gpio-cells = <2>; 507379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 96 8>; 508f2bfacf9SZhong Kaihua interrupt-controller; 509f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 510f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 511f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 512f2bfacf9SZhong Kaihua }; 513f2bfacf9SZhong Kaihua 514f2bfacf9SZhong Kaihua gpio6: gpio@f7022000 { 515f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 516f2bfacf9SZhong Kaihua reg = <0x0 0xf7022000 0x0 0x1000>; 517f2bfacf9SZhong Kaihua interrupts = <0 58 0x4>; 518f2bfacf9SZhong Kaihua gpio-controller; 519f2bfacf9SZhong Kaihua #gpio-cells = <2>; 520379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 104 8>; 521f2bfacf9SZhong Kaihua interrupt-controller; 522f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 523f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 524f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 525f2bfacf9SZhong Kaihua }; 526f2bfacf9SZhong Kaihua 527f2bfacf9SZhong Kaihua gpio7: gpio@f7023000 { 528f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 529f2bfacf9SZhong Kaihua reg = <0x0 0xf7023000 0x0 0x1000>; 530f2bfacf9SZhong Kaihua interrupts = <0 59 0x4>; 531f2bfacf9SZhong Kaihua gpio-controller; 532f2bfacf9SZhong Kaihua #gpio-cells = <2>; 533379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 112 8>; 534f2bfacf9SZhong Kaihua interrupt-controller; 535f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 536f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 537f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 538f2bfacf9SZhong Kaihua }; 539f2bfacf9SZhong Kaihua 540f2bfacf9SZhong Kaihua gpio8: gpio@f7024000 { 541f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 542f2bfacf9SZhong Kaihua reg = <0x0 0xf7024000 0x0 0x1000>; 543f2bfacf9SZhong Kaihua interrupts = <0 60 0x4>; 544f2bfacf9SZhong Kaihua gpio-controller; 545f2bfacf9SZhong Kaihua #gpio-cells = <2>; 546379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 547f2bfacf9SZhong Kaihua interrupt-controller; 548f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 549f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 550f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 551f2bfacf9SZhong Kaihua }; 552f2bfacf9SZhong Kaihua 553f2bfacf9SZhong Kaihua gpio9: gpio@f7025000 { 554f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 555f2bfacf9SZhong Kaihua reg = <0x0 0xf7025000 0x0 0x1000>; 556f2bfacf9SZhong Kaihua interrupts = <0 61 0x4>; 557f2bfacf9SZhong Kaihua gpio-controller; 558f2bfacf9SZhong Kaihua #gpio-cells = <2>; 559379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 8 8>; 560f2bfacf9SZhong Kaihua interrupt-controller; 561f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 562f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 563f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 564f2bfacf9SZhong Kaihua }; 565f2bfacf9SZhong Kaihua 566f2bfacf9SZhong Kaihua gpio10: gpio@f7026000 { 567f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 568f2bfacf9SZhong Kaihua reg = <0x0 0xf7026000 0x0 0x1000>; 569f2bfacf9SZhong Kaihua interrupts = <0 62 0x4>; 570f2bfacf9SZhong Kaihua gpio-controller; 571f2bfacf9SZhong Kaihua #gpio-cells = <2>; 572379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 573f2bfacf9SZhong Kaihua interrupt-controller; 574f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 575f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 576f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 577f2bfacf9SZhong Kaihua }; 578f2bfacf9SZhong Kaihua 579f2bfacf9SZhong Kaihua gpio11: gpio@f7027000 { 580f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 581f2bfacf9SZhong Kaihua reg = <0x0 0xf7027000 0x0 0x1000>; 582f2bfacf9SZhong Kaihua interrupts = <0 63 0x4>; 583f2bfacf9SZhong Kaihua gpio-controller; 584f2bfacf9SZhong Kaihua #gpio-cells = <2>; 585379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 586f2bfacf9SZhong Kaihua interrupt-controller; 587f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 588f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 589f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 590f2bfacf9SZhong Kaihua }; 591f2bfacf9SZhong Kaihua 592f2bfacf9SZhong Kaihua gpio12: gpio@f7028000 { 593f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 594f2bfacf9SZhong Kaihua reg = <0x0 0xf7028000 0x0 0x1000>; 595f2bfacf9SZhong Kaihua interrupts = <0 64 0x4>; 596f2bfacf9SZhong Kaihua gpio-controller; 597f2bfacf9SZhong Kaihua #gpio-cells = <2>; 598379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 599f2bfacf9SZhong Kaihua interrupt-controller; 600f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 601f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 602f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 603f2bfacf9SZhong Kaihua }; 604f2bfacf9SZhong Kaihua 605f2bfacf9SZhong Kaihua gpio13: gpio@f7029000 { 606f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 607f2bfacf9SZhong Kaihua reg = <0x0 0xf7029000 0x0 0x1000>; 608f2bfacf9SZhong Kaihua interrupts = <0 65 0x4>; 609f2bfacf9SZhong Kaihua gpio-controller; 610379e9bf5SZhong Kaihua #gpio-cells = <2>; 611379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 48 8>; 612f2bfacf9SZhong Kaihua interrupt-controller; 613f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 614f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 615f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 616f2bfacf9SZhong Kaihua }; 617f2bfacf9SZhong Kaihua 618f2bfacf9SZhong Kaihua gpio14: gpio@f702a000 { 619f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 620f2bfacf9SZhong Kaihua reg = <0x0 0xf702a000 0x0 0x1000>; 621f2bfacf9SZhong Kaihua interrupts = <0 66 0x4>; 622f2bfacf9SZhong Kaihua gpio-controller; 623f2bfacf9SZhong Kaihua #gpio-cells = <2>; 624379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 56 8>; 625f2bfacf9SZhong Kaihua interrupt-controller; 626f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 627f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 628f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 629f2bfacf9SZhong Kaihua }; 630f2bfacf9SZhong Kaihua 631f2bfacf9SZhong Kaihua gpio15: gpio@f702b000 { 632f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 633f2bfacf9SZhong Kaihua reg = <0x0 0xf702b000 0x0 0x1000>; 634f2bfacf9SZhong Kaihua interrupts = <0 67 0x4>; 635f2bfacf9SZhong Kaihua gpio-controller; 636f2bfacf9SZhong Kaihua #gpio-cells = <2>; 637379e9bf5SZhong Kaihua gpio-ranges = < 638379e9bf5SZhong Kaihua &pmx0 0 74 6 639379e9bf5SZhong Kaihua &pmx0 6 122 1 640379e9bf5SZhong Kaihua &pmx0 7 126 1 641379e9bf5SZhong Kaihua >; 642f2bfacf9SZhong Kaihua interrupt-controller; 643f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 644f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 645f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 646f2bfacf9SZhong Kaihua }; 647f2bfacf9SZhong Kaihua 648f2bfacf9SZhong Kaihua gpio16: gpio@f702c000 { 649f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 650f2bfacf9SZhong Kaihua reg = <0x0 0xf702c000 0x0 0x1000>; 651f2bfacf9SZhong Kaihua interrupts = <0 68 0x4>; 652f2bfacf9SZhong Kaihua gpio-controller; 653f2bfacf9SZhong Kaihua #gpio-cells = <2>; 654379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 127 8>; 655f2bfacf9SZhong Kaihua interrupt-controller; 656f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 657f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 658f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 659f2bfacf9SZhong Kaihua }; 660f2bfacf9SZhong Kaihua 661f2bfacf9SZhong Kaihua gpio17: gpio@f702d000 { 662f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 663f2bfacf9SZhong Kaihua reg = <0x0 0xf702d000 0x0 0x1000>; 664f2bfacf9SZhong Kaihua interrupts = <0 69 0x4>; 665f2bfacf9SZhong Kaihua gpio-controller; 666f2bfacf9SZhong Kaihua #gpio-cells = <2>; 667379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 135 8>; 668f2bfacf9SZhong Kaihua interrupt-controller; 669f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 670f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 671f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 672f2bfacf9SZhong Kaihua }; 673f2bfacf9SZhong Kaihua 674f2bfacf9SZhong Kaihua gpio18: gpio@f702e000 { 675f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 676f2bfacf9SZhong Kaihua reg = <0x0 0xf702e000 0x0 0x1000>; 677f2bfacf9SZhong Kaihua interrupts = <0 70 0x4>; 678f2bfacf9SZhong Kaihua gpio-controller; 679f2bfacf9SZhong Kaihua #gpio-cells = <2>; 680379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 143 8>; 681f2bfacf9SZhong Kaihua interrupt-controller; 682f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 683f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 684f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 685f2bfacf9SZhong Kaihua }; 686f2bfacf9SZhong Kaihua 687f2bfacf9SZhong Kaihua gpio19: gpio@f702f000 { 688f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 689f2bfacf9SZhong Kaihua reg = <0x0 0xf702f000 0x0 0x1000>; 690f2bfacf9SZhong Kaihua interrupts = <0 71 0x4>; 691f2bfacf9SZhong Kaihua gpio-controller; 692f2bfacf9SZhong Kaihua #gpio-cells = <2>; 693379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 151 8>; 694f2bfacf9SZhong Kaihua interrupt-controller; 695f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 696f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 697f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 698f2bfacf9SZhong Kaihua }; 69960dac1b1SZhong Kaihua 70060dac1b1SZhong Kaihua spi0: spi@f7106000 { 70160dac1b1SZhong Kaihua compatible = "arm,pl022", "arm,primecell"; 70260dac1b1SZhong Kaihua reg = <0x0 0xf7106000 0x0 0x1000>; 70360dac1b1SZhong Kaihua interrupts = <0 50 4>; 70460dac1b1SZhong Kaihua bus-id = <0>; 70560dac1b1SZhong Kaihua enable-dma = <0>; 70660dac1b1SZhong Kaihua clocks = <&sys_ctrl HI6220_SPI_CLK>; 70760dac1b1SZhong Kaihua clock-names = "apb_pclk"; 70860dac1b1SZhong Kaihua pinctrl-names = "default"; 70960dac1b1SZhong Kaihua pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 71060dac1b1SZhong Kaihua num-cs = <1>; 71160dac1b1SZhong Kaihua cs-gpios = <&gpio6 2 0>; 71260dac1b1SZhong Kaihua status = "disabled"; 71360dac1b1SZhong Kaihua }; 7145ff3a4ddSXinwei Kong 7155ff3a4ddSXinwei Kong i2c0: i2c@f7100000 { 7165ff3a4ddSXinwei Kong compatible = "snps,designware-i2c"; 7175ff3a4ddSXinwei Kong reg = <0x0 0xf7100000 0x0 0x1000>; 7185ff3a4ddSXinwei Kong interrupts = <0 44 4>; 7195ff3a4ddSXinwei Kong clocks = <&sys_ctrl HI6220_I2C0_CLK>; 7205ff3a4ddSXinwei Kong i2c-sda-hold-time-ns = <300>; 7215ff3a4ddSXinwei Kong pinctrl-names = "default"; 7225ff3a4ddSXinwei Kong pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 7235ff3a4ddSXinwei Kong status = "disabled"; 7245ff3a4ddSXinwei Kong }; 7255ff3a4ddSXinwei Kong 7265ff3a4ddSXinwei Kong i2c1: i2c@f7101000 { 7275ff3a4ddSXinwei Kong compatible = "snps,designware-i2c"; 7285ff3a4ddSXinwei Kong reg = <0x0 0xf7101000 0x0 0x1000>; 7295ff3a4ddSXinwei Kong clocks = <&sys_ctrl HI6220_I2C1_CLK>; 7305ff3a4ddSXinwei Kong interrupts = <0 45 4>; 7315ff3a4ddSXinwei Kong i2c-sda-hold-time-ns = <300>; 7325ff3a4ddSXinwei Kong pinctrl-names = "default"; 7335ff3a4ddSXinwei Kong pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 7345ff3a4ddSXinwei Kong status = "disabled"; 7355ff3a4ddSXinwei Kong }; 7365ff3a4ddSXinwei Kong 7375ff3a4ddSXinwei Kong i2c2: i2c@f7102000 { 7385ff3a4ddSXinwei Kong compatible = "snps,designware-i2c"; 7395ff3a4ddSXinwei Kong reg = <0x0 0xf7102000 0x0 0x1000>; 7405ff3a4ddSXinwei Kong clocks = <&sys_ctrl HI6220_I2C2_CLK>; 7415ff3a4ddSXinwei Kong interrupts = <0 46 4>; 7425ff3a4ddSXinwei Kong i2c-sda-hold-time-ns = <300>; 7435ff3a4ddSXinwei Kong pinctrl-names = "default"; 7445ff3a4ddSXinwei Kong pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 7455ff3a4ddSXinwei Kong status = "disabled"; 7465ff3a4ddSXinwei Kong }; 747b4b31a7cSZhangfei Gao 748b4b31a7cSZhangfei Gao usb_phy: usbphy { 749b4b31a7cSZhangfei Gao compatible = "hisilicon,hi6220-usb-phy"; 750b4b31a7cSZhangfei Gao #phy-cells = <0>; 7511b32a5ffSUlf Hansson phy-supply = <®_5v_hub>; 752b4b31a7cSZhangfei Gao hisilicon,peripheral-syscon = <&sys_ctrl>; 753b4b31a7cSZhangfei Gao }; 754b4b31a7cSZhangfei Gao 755b4b31a7cSZhangfei Gao usb: usb@f72c0000 { 756b4b31a7cSZhangfei Gao compatible = "hisilicon,hi6220-usb"; 757b4b31a7cSZhangfei Gao reg = <0x0 0xf72c0000 0x0 0x40000>; 758b4b31a7cSZhangfei Gao phys = <&usb_phy>; 759b4b31a7cSZhangfei Gao phy-names = "usb2-phy"; 760b4b31a7cSZhangfei Gao clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 761b4b31a7cSZhangfei Gao clock-names = "otg"; 762b4b31a7cSZhangfei Gao dr_mode = "otg"; 763b4b31a7cSZhangfei Gao g-rx-fifo-size = <512>; 764b4b31a7cSZhangfei Gao g-np-tx-fifo-size = <128>; 765341b26b7SShawn Guo g-tx-fifo-size = <128 128 128 128 128 128 128 128 766341b26b7SShawn Guo 16 16 16 16 16 16 16>; 767b4b31a7cSZhangfei Gao interrupts = <0 77 0x4>; 768b4b31a7cSZhangfei Gao }; 76986073570SLeo Yan 77086073570SLeo Yan mailbox: mailbox@f7510000 { 77186073570SLeo Yan compatible = "hisilicon,hi6220-mbox"; 77286073570SLeo Yan reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 77386073570SLeo Yan <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 77486073570SLeo Yan interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 77586073570SLeo Yan #mbox-cells = <3>; 77686073570SLeo Yan }; 777d6b259d4SXinwei Kong 778d6b259d4SXinwei Kong dwmmc_0: dwmmc0@f723d000 { 779d6b259d4SXinwei Kong compatible = "hisilicon,hi6220-dw-mshc"; 780d6b259d4SXinwei Kong reg = <0x0 0xf723d000 0x0 0x1000>; 781d6b259d4SXinwei Kong interrupts = <0x0 0x48 0x4>; 782d6b259d4SXinwei Kong clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; 783d6b259d4SXinwei Kong clock-names = "ciu", "biu"; 78494914fc8SGuodong Xu resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; 7850fbdf995SDaniel Lezcano reset-names = "reset"; 786d6b259d4SXinwei Kong pinctrl-names = "default"; 787d6b259d4SXinwei Kong pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func 788d6b259d4SXinwei Kong &emmc_cfg_func &emmc_rst_cfg_func>; 789d6b259d4SXinwei Kong }; 790d6b259d4SXinwei Kong 791d6b259d4SXinwei Kong dwmmc_1: dwmmc1@f723e000 { 792d6b259d4SXinwei Kong compatible = "hisilicon,hi6220-dw-mshc"; 793d6b259d4SXinwei Kong hisilicon,peripheral-syscon = <&ao_ctrl>; 794d6b259d4SXinwei Kong reg = <0x0 0xf723e000 0x0 0x1000>; 795d6b259d4SXinwei Kong interrupts = <0x0 0x49 0x4>; 796d6b259d4SXinwei Kong #address-cells = <0x1>; 797d6b259d4SXinwei Kong #size-cells = <0x0>; 798d6b259d4SXinwei Kong clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; 799d6b259d4SXinwei Kong clock-names = "ciu", "biu"; 80094914fc8SGuodong Xu resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; 8010fbdf995SDaniel Lezcano reset-names = "reset"; 802d6b259d4SXinwei Kong pinctrl-names = "default", "idle"; 803d6b259d4SXinwei Kong pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; 804d6b259d4SXinwei Kong pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; 805d6b259d4SXinwei Kong }; 806d6b259d4SXinwei Kong 807d6b259d4SXinwei Kong dwmmc_2: dwmmc2@f723f000 { 808d6b259d4SXinwei Kong compatible = "hisilicon,hi6220-dw-mshc"; 809d6b259d4SXinwei Kong reg = <0x0 0xf723f000 0x0 0x1000>; 810d6b259d4SXinwei Kong interrupts = <0x0 0x4a 0x4>; 811d6b259d4SXinwei Kong clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; 812d6b259d4SXinwei Kong clock-names = "ciu", "biu"; 81394914fc8SGuodong Xu resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; 8140fbdf995SDaniel Lezcano reset-names = "reset"; 815d6b259d4SXinwei Kong pinctrl-names = "default", "idle"; 816d6b259d4SXinwei Kong pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; 817d6b259d4SXinwei Kong pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; 818d6b259d4SXinwei Kong }; 8192158ab08SLeo Yan 8202158ab08SLeo Yan tsensor: tsensor@0,f7030700 { 8212158ab08SLeo Yan compatible = "hisilicon,tsensor"; 8222158ab08SLeo Yan reg = <0x0 0xf7030700 0x0 0x1000>; 8232158ab08SLeo Yan interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 8242158ab08SLeo Yan clocks = <&sys_ctrl 22>; 8252158ab08SLeo Yan clock-names = "thermal_clk"; 8262158ab08SLeo Yan #thermal-sensor-cells = <1>; 8272158ab08SLeo Yan }; 828cd0b69ecSLeo Yan 8290cf6a8e2SJohn Stultz i2s0: i2s@f7118000{ 8300cf6a8e2SJohn Stultz compatible = "hisilicon,hi6210-i2s"; 8310cf6a8e2SJohn Stultz reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ 8320cf6a8e2SJohn Stultz interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */ 8330cf6a8e2SJohn Stultz clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, 8340cf6a8e2SJohn Stultz <&sys_ctrl HI6220_BBPPLL0_DIV>; 8350cf6a8e2SJohn Stultz clock-names = "dacodec", "i2s-base"; 8360cf6a8e2SJohn Stultz dmas = <&dma0 15 &dma0 14>; 8370cf6a8e2SJohn Stultz dma-names = "rx", "tx"; 8380cf6a8e2SJohn Stultz hisilicon,sysctrl-syscon = <&sys_ctrl>; 8390cf6a8e2SJohn Stultz #sound-dai-cells = <1>; 8400cf6a8e2SJohn Stultz }; 8410cf6a8e2SJohn Stultz 842cd0b69ecSLeo Yan thermal-zones { 843cd0b69ecSLeo Yan 844cd0b69ecSLeo Yan cls0: cls0 { 845cd0b69ecSLeo Yan polling-delay = <1000>; 846cd0b69ecSLeo Yan polling-delay-passive = <100>; 847cd0b69ecSLeo Yan sustainable-power = <3326>; 848cd0b69ecSLeo Yan 849cd0b69ecSLeo Yan /* sensor ID */ 850cd0b69ecSLeo Yan thermal-sensors = <&tsensor 2>; 851cd0b69ecSLeo Yan 852cd0b69ecSLeo Yan trips { 853cd0b69ecSLeo Yan threshold: trip-point@0 { 854cd0b69ecSLeo Yan temperature = <65000>; 855cd0b69ecSLeo Yan hysteresis = <0>; 856cd0b69ecSLeo Yan type = "passive"; 857cd0b69ecSLeo Yan }; 858cd0b69ecSLeo Yan 859cd0b69ecSLeo Yan target: trip-point@1 { 860cd0b69ecSLeo Yan temperature = <75000>; 861cd0b69ecSLeo Yan hysteresis = <0>; 862cd0b69ecSLeo Yan type = "passive"; 863cd0b69ecSLeo Yan }; 864cd0b69ecSLeo Yan }; 865cd0b69ecSLeo Yan 866cd0b69ecSLeo Yan cooling-maps { 867cd0b69ecSLeo Yan map0 { 868cd0b69ecSLeo Yan trip = <&target>; 869cd0b69ecSLeo Yan cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 870cd0b69ecSLeo Yan }; 871cd0b69ecSLeo Yan }; 872cd0b69ecSLeo Yan }; 873cd0b69ecSLeo Yan }; 8743814b61bSXinliang Liu 8753814b61bSXinliang Liu ade: ade@f4100000 { 8763814b61bSXinliang Liu compatible = "hisilicon,hi6220-ade"; 8773814b61bSXinliang Liu reg = <0x0 0xf4100000 0x0 0x7800>; 8783814b61bSXinliang Liu reg-names = "ade_base"; 8793814b61bSXinliang Liu hisilicon,noc-syscon = <&medianoc_ade>; 8803814b61bSXinliang Liu resets = <&media_ctrl MEDIA_ADE>; 8813814b61bSXinliang Liu interrupts = <0 115 4>; /* ldi interrupt */ 8823814b61bSXinliang Liu 8833814b61bSXinliang Liu clocks = <&media_ctrl HI6220_ADE_CORE>, 8843814b61bSXinliang Liu <&media_ctrl HI6220_CODEC_JPEG>, 8853814b61bSXinliang Liu <&media_ctrl HI6220_ADE_PIX_SRC>; 8863814b61bSXinliang Liu /*clock name*/ 8873814b61bSXinliang Liu clock-names = "clk_ade_core", 8883814b61bSXinliang Liu "clk_codec_jpeg", 8893814b61bSXinliang Liu "clk_ade_pix"; 8903814b61bSXinliang Liu 8913814b61bSXinliang Liu assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, 8923814b61bSXinliang Liu <&media_ctrl HI6220_CODEC_JPEG>; 8933814b61bSXinliang Liu assigned-clock-rates = <360000000>, <288000000>; 8943814b61bSXinliang Liu dma-coherent; 8953814b61bSXinliang Liu status = "disabled"; 8963814b61bSXinliang Liu 8973814b61bSXinliang Liu port { 8983814b61bSXinliang Liu ade_out: endpoint { 8993814b61bSXinliang Liu remote-endpoint = <&dsi_in>; 9003814b61bSXinliang Liu }; 9013814b61bSXinliang Liu }; 9023814b61bSXinliang Liu }; 9033814b61bSXinliang Liu 9043814b61bSXinliang Liu dsi: dsi@f4107800 { 9053814b61bSXinliang Liu compatible = "hisilicon,hi6220-dsi"; 9063814b61bSXinliang Liu reg = <0x0 0xf4107800 0x0 0x100>; 9073814b61bSXinliang Liu clocks = <&media_ctrl HI6220_DSI_PCLK>; 9083814b61bSXinliang Liu clock-names = "pclk"; 9093814b61bSXinliang Liu status = "disabled"; 9103814b61bSXinliang Liu 9113814b61bSXinliang Liu ports { 9123814b61bSXinliang Liu #address-cells = <1>; 9133814b61bSXinliang Liu #size-cells = <0>; 9143814b61bSXinliang Liu 9153814b61bSXinliang Liu /* 0 for input port */ 9163814b61bSXinliang Liu port@0 { 9173814b61bSXinliang Liu reg = <0>; 9183814b61bSXinliang Liu dsi_in: endpoint { 9193814b61bSXinliang Liu remote-endpoint = <&ade_out>; 9203814b61bSXinliang Liu }; 9213814b61bSXinliang Liu }; 9223814b61bSXinliang Liu }; 9233814b61bSXinliang Liu }; 9244fcf9a62SLeo Yan 9254fcf9a62SLeo Yan debug@f6590000 { 9264fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9274fcf9a62SLeo Yan reg = <0 0xf6590000 0 0x1000>; 9284fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9294fcf9a62SLeo Yan clock-names = "apb_pclk"; 9304fcf9a62SLeo Yan cpu = <&cpu0>; 9314fcf9a62SLeo Yan }; 9324fcf9a62SLeo Yan 9334fcf9a62SLeo Yan debug@f6592000 { 9344fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9354fcf9a62SLeo Yan reg = <0 0xf6592000 0 0x1000>; 9364fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9374fcf9a62SLeo Yan clock-names = "apb_pclk"; 9384fcf9a62SLeo Yan cpu = <&cpu1>; 9394fcf9a62SLeo Yan }; 9404fcf9a62SLeo Yan 9414fcf9a62SLeo Yan debug@f6594000 { 9424fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9434fcf9a62SLeo Yan reg = <0 0xf6594000 0 0x1000>; 9444fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9454fcf9a62SLeo Yan clock-names = "apb_pclk"; 9464fcf9a62SLeo Yan cpu = <&cpu2>; 9474fcf9a62SLeo Yan }; 9484fcf9a62SLeo Yan 9494fcf9a62SLeo Yan debug@f6596000 { 9504fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9514fcf9a62SLeo Yan reg = <0 0xf6596000 0 0x1000>; 9524fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9534fcf9a62SLeo Yan clock-names = "apb_pclk"; 9544fcf9a62SLeo Yan cpu = <&cpu3>; 9554fcf9a62SLeo Yan }; 9564fcf9a62SLeo Yan 9574fcf9a62SLeo Yan debug@f65d0000 { 9584fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9594fcf9a62SLeo Yan reg = <0 0xf65d0000 0 0x1000>; 9604fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9614fcf9a62SLeo Yan clock-names = "apb_pclk"; 9624fcf9a62SLeo Yan cpu = <&cpu4>; 9634fcf9a62SLeo Yan }; 9644fcf9a62SLeo Yan 9654fcf9a62SLeo Yan debug@f65d2000 { 9664fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9674fcf9a62SLeo Yan reg = <0 0xf65d2000 0 0x1000>; 9684fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9694fcf9a62SLeo Yan clock-names = "apb_pclk"; 9704fcf9a62SLeo Yan cpu = <&cpu5>; 9714fcf9a62SLeo Yan }; 9724fcf9a62SLeo Yan 9734fcf9a62SLeo Yan debug@f65d4000 { 9744fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9754fcf9a62SLeo Yan reg = <0 0xf65d4000 0 0x1000>; 9764fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9774fcf9a62SLeo Yan clock-names = "apb_pclk"; 9784fcf9a62SLeo Yan cpu = <&cpu6>; 9794fcf9a62SLeo Yan }; 9804fcf9a62SLeo Yan 9814fcf9a62SLeo Yan debug@f65d6000 { 9824fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9834fcf9a62SLeo Yan reg = <0 0xf65d6000 0 0x1000>; 9844fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9854fcf9a62SLeo Yan clock-names = "apb_pclk"; 9864fcf9a62SLeo Yan cpu = <&cpu7>; 9874fcf9a62SLeo Yan }; 98886e8f528SBintian Wang }; 98986e8f528SBintian Wang}; 990