1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 286e8f528SBintian Wang/* 386e8f528SBintian Wang * dts file for Hisilicon Hi6220 SoC 486e8f528SBintian Wang * 586e8f528SBintian Wang * Copyright (C) 2015, Hisilicon Ltd. 686e8f528SBintian Wang */ 786e8f528SBintian Wang 886e8f528SBintian Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 9339d00cbSXinliang Liu#include <dt-bindings/reset/hisi,hi6220-resets.h> 10a362ec8fSTyler Baker#include <dt-bindings/clock/hi6220-clock.h> 11379e9bf5SZhong Kaihua#include <dt-bindings/pinctrl/hisi.h> 12cd0b69ecSLeo Yan#include <dt-bindings/thermal/thermal.h> 1386e8f528SBintian Wang 1486e8f528SBintian Wang/ { 1586e8f528SBintian Wang compatible = "hisilicon,hi6220"; 1686e8f528SBintian Wang interrupt-parent = <&gic>; 1786e8f528SBintian Wang #address-cells = <2>; 1886e8f528SBintian Wang #size-cells = <2>; 1986e8f528SBintian Wang 2086e8f528SBintian Wang psci { 2186e8f528SBintian Wang compatible = "arm,psci-0.2"; 2286e8f528SBintian Wang method = "smc"; 2386e8f528SBintian Wang }; 2486e8f528SBintian Wang 2586e8f528SBintian Wang cpus { 2686e8f528SBintian Wang #address-cells = <2>; 2786e8f528SBintian Wang #size-cells = <0>; 2886e8f528SBintian Wang 2986e8f528SBintian Wang cpu-map { 3086e8f528SBintian Wang cluster0 { 3186e8f528SBintian Wang core0 { 3286e8f528SBintian Wang cpu = <&cpu0>; 3386e8f528SBintian Wang }; 3486e8f528SBintian Wang core1 { 3586e8f528SBintian Wang cpu = <&cpu1>; 3686e8f528SBintian Wang }; 3786e8f528SBintian Wang core2 { 3886e8f528SBintian Wang cpu = <&cpu2>; 3986e8f528SBintian Wang }; 4086e8f528SBintian Wang core3 { 4186e8f528SBintian Wang cpu = <&cpu3>; 4286e8f528SBintian Wang }; 4386e8f528SBintian Wang }; 4486e8f528SBintian Wang cluster1 { 4586e8f528SBintian Wang core0 { 4686e8f528SBintian Wang cpu = <&cpu4>; 4786e8f528SBintian Wang }; 4886e8f528SBintian Wang core1 { 4986e8f528SBintian Wang cpu = <&cpu5>; 5086e8f528SBintian Wang }; 5186e8f528SBintian Wang core2 { 5286e8f528SBintian Wang cpu = <&cpu6>; 5386e8f528SBintian Wang }; 5486e8f528SBintian Wang core3 { 5586e8f528SBintian Wang cpu = <&cpu7>; 5686e8f528SBintian Wang }; 5786e8f528SBintian Wang }; 5886e8f528SBintian Wang }; 5986e8f528SBintian Wang 6058fa29bfSLeo Yan idle-states { 6158fa29bfSLeo Yan entry-method = "psci"; 6258fa29bfSLeo Yan 6358fa29bfSLeo Yan CPU_SLEEP: cpu-sleep { 6458fa29bfSLeo Yan compatible = "arm,idle-state"; 6558fa29bfSLeo Yan local-timer-stop; 6658fa29bfSLeo Yan arm,psci-suspend-param = <0x0010000>; 6758fa29bfSLeo Yan entry-latency-us = <700>; 6858fa29bfSLeo Yan exit-latency-us = <250>; 6958fa29bfSLeo Yan min-residency-us = <1000>; 7058fa29bfSLeo Yan }; 7158fa29bfSLeo Yan 7258fa29bfSLeo Yan CLUSTER_SLEEP: cluster-sleep { 7358fa29bfSLeo Yan compatible = "arm,idle-state"; 7458fa29bfSLeo Yan local-timer-stop; 7558fa29bfSLeo Yan arm,psci-suspend-param = <0x1010000>; 7658fa29bfSLeo Yan entry-latency-us = <1000>; 7758fa29bfSLeo Yan exit-latency-us = <700>; 7858fa29bfSLeo Yan min-residency-us = <2700>; 7958fa29bfSLeo Yan wakeup-latency-us = <1500>; 8058fa29bfSLeo Yan }; 8158fa29bfSLeo Yan }; 8258fa29bfSLeo Yan 8386e8f528SBintian Wang cpu0: cpu@0 { 8486e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 8586e8f528SBintian Wang device_type = "cpu"; 8686e8f528SBintian Wang reg = <0x0 0x0>; 8786e8f528SBintian Wang enable-method = "psci"; 8864851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 8999860540SLeo Yan clocks = <&stub_clock 0>; 9099860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 9158fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 924d4585c2SViresh Kumar #cooling-cells = <2>; /* min followed by max */ 93cd0b69ecSLeo Yan dynamic-power-coefficient = <311>; 9486e8f528SBintian Wang }; 9586e8f528SBintian Wang 9686e8f528SBintian Wang cpu1: cpu@1 { 9786e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 9886e8f528SBintian Wang device_type = "cpu"; 9986e8f528SBintian Wang reg = <0x0 0x1>; 10086e8f528SBintian Wang enable-method = "psci"; 10164851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 102b27dedf5SViresh Kumar clocks = <&stub_clock 0>; 10399860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 10458fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 1054d4585c2SViresh Kumar #cooling-cells = <2>; /* min followed by max */ 1064d4585c2SViresh Kumar dynamic-power-coefficient = <311>; 10786e8f528SBintian Wang }; 10886e8f528SBintian Wang 10986e8f528SBintian Wang cpu2: cpu@2 { 11086e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 11186e8f528SBintian Wang device_type = "cpu"; 11286e8f528SBintian Wang reg = <0x0 0x2>; 11386e8f528SBintian Wang enable-method = "psci"; 11464851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 115b27dedf5SViresh Kumar clocks = <&stub_clock 0>; 11699860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 11758fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 1184d4585c2SViresh Kumar #cooling-cells = <2>; /* min followed by max */ 1194d4585c2SViresh Kumar dynamic-power-coefficient = <311>; 12086e8f528SBintian Wang }; 12186e8f528SBintian Wang 12286e8f528SBintian Wang cpu3: cpu@3 { 12386e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 12486e8f528SBintian Wang device_type = "cpu"; 12586e8f528SBintian Wang reg = <0x0 0x3>; 12686e8f528SBintian Wang enable-method = "psci"; 12764851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 128b27dedf5SViresh Kumar clocks = <&stub_clock 0>; 12999860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 13058fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 1314d4585c2SViresh Kumar #cooling-cells = <2>; /* min followed by max */ 1324d4585c2SViresh Kumar dynamic-power-coefficient = <311>; 13386e8f528SBintian Wang }; 13486e8f528SBintian Wang 13586e8f528SBintian Wang cpu4: cpu@100 { 13686e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 13786e8f528SBintian Wang device_type = "cpu"; 13886e8f528SBintian Wang reg = <0x0 0x100>; 13986e8f528SBintian Wang enable-method = "psci"; 14064851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 141b27dedf5SViresh Kumar clocks = <&stub_clock 0>; 14299860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 14358fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 1444d4585c2SViresh Kumar #cooling-cells = <2>; /* min followed by max */ 1454d4585c2SViresh Kumar dynamic-power-coefficient = <311>; 14686e8f528SBintian Wang }; 14786e8f528SBintian Wang 14886e8f528SBintian Wang cpu5: cpu@101 { 14986e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 15086e8f528SBintian Wang device_type = "cpu"; 15186e8f528SBintian Wang reg = <0x0 0x101>; 15286e8f528SBintian Wang enable-method = "psci"; 15364851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 154b27dedf5SViresh Kumar clocks = <&stub_clock 0>; 15599860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 15658fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 1574d4585c2SViresh Kumar #cooling-cells = <2>; /* min followed by max */ 1584d4585c2SViresh Kumar dynamic-power-coefficient = <311>; 15986e8f528SBintian Wang }; 16086e8f528SBintian Wang 16186e8f528SBintian Wang cpu6: cpu@102 { 16286e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 16386e8f528SBintian Wang device_type = "cpu"; 16486e8f528SBintian Wang reg = <0x0 0x102>; 16586e8f528SBintian Wang enable-method = "psci"; 16664851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 167b27dedf5SViresh Kumar clocks = <&stub_clock 0>; 16899860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 16958fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 1704d4585c2SViresh Kumar #cooling-cells = <2>; /* min followed by max */ 1714d4585c2SViresh Kumar dynamic-power-coefficient = <311>; 17286e8f528SBintian Wang }; 17386e8f528SBintian Wang 17486e8f528SBintian Wang cpu7: cpu@103 { 17586e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 17686e8f528SBintian Wang device_type = "cpu"; 17786e8f528SBintian Wang reg = <0x0 0x103>; 17886e8f528SBintian Wang enable-method = "psci"; 17964851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 180b27dedf5SViresh Kumar clocks = <&stub_clock 0>; 18199860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 18258fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 1834d4585c2SViresh Kumar #cooling-cells = <2>; /* min followed by max */ 1844d4585c2SViresh Kumar dynamic-power-coefficient = <311>; 18586e8f528SBintian Wang }; 18664851603SLeo Yan 18764851603SLeo Yan CLUSTER0_L2: l2-cache0 { 18864851603SLeo Yan compatible = "cache"; 18964851603SLeo Yan }; 19064851603SLeo Yan 19164851603SLeo Yan CLUSTER1_L2: l2-cache1 { 19264851603SLeo Yan compatible = "cache"; 19364851603SLeo Yan }; 19486e8f528SBintian Wang }; 19586e8f528SBintian Wang 19699860540SLeo Yan cpu_opp_table: cpu_opp_table { 19799860540SLeo Yan compatible = "operating-points-v2"; 19899860540SLeo Yan opp-shared; 19999860540SLeo Yan 20099860540SLeo Yan opp00 { 20199860540SLeo Yan opp-hz = /bits/ 64 <208000000>; 20299860540SLeo Yan opp-microvolt = <1040000>; 20399860540SLeo Yan clock-latency-ns = <500000>; 20499860540SLeo Yan }; 20599860540SLeo Yan opp01 { 20699860540SLeo Yan opp-hz = /bits/ 64 <432000000>; 20799860540SLeo Yan opp-microvolt = <1040000>; 20899860540SLeo Yan clock-latency-ns = <500000>; 20999860540SLeo Yan }; 21099860540SLeo Yan opp02 { 21199860540SLeo Yan opp-hz = /bits/ 64 <729000000>; 21299860540SLeo Yan opp-microvolt = <1090000>; 21399860540SLeo Yan clock-latency-ns = <500000>; 21499860540SLeo Yan }; 21599860540SLeo Yan opp03 { 21699860540SLeo Yan opp-hz = /bits/ 64 <960000000>; 21799860540SLeo Yan opp-microvolt = <1180000>; 21899860540SLeo Yan clock-latency-ns = <500000>; 21999860540SLeo Yan }; 22099860540SLeo Yan opp04 { 22199860540SLeo Yan opp-hz = /bits/ 64 <1200000000>; 22299860540SLeo Yan opp-microvolt = <1330000>; 22399860540SLeo Yan clock-latency-ns = <500000>; 22499860540SLeo Yan }; 22599860540SLeo Yan }; 22699860540SLeo Yan 22786e8f528SBintian Wang gic: interrupt-controller@f6801000 { 22886e8f528SBintian Wang compatible = "arm,gic-400"; 22986e8f528SBintian Wang reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 23086e8f528SBintian Wang <0x0 0xf6802000 0 0x2000>, /* GICC */ 23186e8f528SBintian Wang <0x0 0xf6804000 0 0x2000>, /* GICH */ 23286e8f528SBintian Wang <0x0 0xf6806000 0 0x2000>; /* GICV */ 23386e8f528SBintian Wang #address-cells = <0>; 23486e8f528SBintian Wang #interrupt-cells = <3>; 23586e8f528SBintian Wang interrupt-controller; 23686e8f528SBintian Wang interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 23786e8f528SBintian Wang }; 23886e8f528SBintian Wang 23986e8f528SBintian Wang timer { 24086e8f528SBintian Wang compatible = "arm,armv8-timer"; 24186e8f528SBintian Wang interrupt-parent = <&gic>; 24286e8f528SBintian Wang interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 24386e8f528SBintian Wang <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 24486e8f528SBintian Wang <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 24586e8f528SBintian Wang <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 24686e8f528SBintian Wang }; 24786e8f528SBintian Wang 24886e8f528SBintian Wang soc { 24986e8f528SBintian Wang compatible = "simple-bus"; 25086e8f528SBintian Wang #address-cells = <2>; 25186e8f528SBintian Wang #size-cells = <2>; 25286e8f528SBintian Wang ranges; 25386e8f528SBintian Wang 25499860540SLeo Yan sram: sram@fff80000 { 25599860540SLeo Yan compatible = "hisilicon,hi6220-sramctrl", "syscon"; 25699860540SLeo Yan reg = <0x0 0xfff80000 0x0 0x12000>; 25799860540SLeo Yan }; 25899860540SLeo Yan 25986e8f528SBintian Wang ao_ctrl: ao_ctrl@f7800000 { 26086e8f528SBintian Wang compatible = "hisilicon,hi6220-aoctrl", "syscon"; 26186e8f528SBintian Wang reg = <0x0 0xf7800000 0x0 0x2000>; 26286e8f528SBintian Wang #clock-cells = <1>; 26386e8f528SBintian Wang }; 26486e8f528SBintian Wang 26586e8f528SBintian Wang sys_ctrl: sys_ctrl@f7030000 { 26686e8f528SBintian Wang compatible = "hisilicon,hi6220-sysctrl", "syscon"; 26786e8f528SBintian Wang reg = <0x0 0xf7030000 0x0 0x2000>; 26886e8f528SBintian Wang #clock-cells = <1>; 2693e14cd4cSChen Feng #reset-cells = <1>; 27086e8f528SBintian Wang }; 27186e8f528SBintian Wang 27286e8f528SBintian Wang media_ctrl: media_ctrl@f4410000 { 27386e8f528SBintian Wang compatible = "hisilicon,hi6220-mediactrl", "syscon"; 27486e8f528SBintian Wang reg = <0x0 0xf4410000 0x0 0x1000>; 27586e8f528SBintian Wang #clock-cells = <1>; 276339d00cbSXinliang Liu #reset-cells = <1>; 27786e8f528SBintian Wang }; 27886e8f528SBintian Wang 27986e8f528SBintian Wang pm_ctrl: pm_ctrl@f7032000 { 28086e8f528SBintian Wang compatible = "hisilicon,hi6220-pmctrl", "syscon"; 28186e8f528SBintian Wang reg = <0x0 0xf7032000 0x0 0x1000>; 28286e8f528SBintian Wang #clock-cells = <1>; 28386e8f528SBintian Wang }; 28486e8f528SBintian Wang 28594d2d94bSZhangfei Gao acpu_sctrl: acpu_sctrl@f6504000 { 28694d2d94bSZhangfei Gao compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; 28794d2d94bSZhangfei Gao reg = <0x0 0xf6504000 0x0 0x1000>; 28894d2d94bSZhangfei Gao #clock-cells = <1>; 28994d2d94bSZhangfei Gao }; 29094d2d94bSZhangfei Gao 2913814b61bSXinliang Liu medianoc_ade: medianoc_ade@f4520000 { 2923814b61bSXinliang Liu compatible = "syscon"; 2933814b61bSXinliang Liu reg = <0x0 0xf4520000 0x0 0x4000>; 2943814b61bSXinliang Liu }; 2953814b61bSXinliang Liu 29699860540SLeo Yan stub_clock: stub_clock { 29799860540SLeo Yan compatible = "hisilicon,hi6220-stub-clk"; 29899860540SLeo Yan hisilicon,hi6220-clk-sram = <&sram>; 29999860540SLeo Yan #clock-cells = <1>; 30099860540SLeo Yan mbox-names = "mbox-tx"; 30199860540SLeo Yan mboxes = <&mailbox 1 0 11>; 30299860540SLeo Yan }; 30399860540SLeo Yan 30486e8f528SBintian Wang uart0: uart@f8015000 { /* console */ 30586e8f528SBintian Wang compatible = "arm,pl011", "arm,primecell"; 30686e8f528SBintian Wang reg = <0x0 0xf8015000 0x0 0x1000>; 30786e8f528SBintian Wang interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 308a362ec8fSTyler Baker clocks = <&ao_ctrl HI6220_UART0_PCLK>, 309a362ec8fSTyler Baker <&ao_ctrl HI6220_UART0_PCLK>; 31086e8f528SBintian Wang clock-names = "uartclk", "apb_pclk"; 31186e8f528SBintian Wang }; 312a362ec8fSTyler Baker 313a362ec8fSTyler Baker uart1: uart@f7111000 { 314a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 315a362ec8fSTyler Baker reg = <0x0 0xf7111000 0x0 0x1000>; 316a362ec8fSTyler Baker interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 317a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART1_PCLK>, 318a362ec8fSTyler Baker <&sys_ctrl HI6220_UART1_PCLK>; 319a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 320c2aad932SGuodong Xu pinctrl-names = "default"; 321c2aad932SGuodong Xu pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; 322a362ec8fSTyler Baker status = "disabled"; 323a362ec8fSTyler Baker }; 324a362ec8fSTyler Baker 325a362ec8fSTyler Baker uart2: uart@f7112000 { 326a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 327a362ec8fSTyler Baker reg = <0x0 0xf7112000 0x0 0x1000>; 328a362ec8fSTyler Baker interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 329a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART2_PCLK>, 330a362ec8fSTyler Baker <&sys_ctrl HI6220_UART2_PCLK>; 331a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 332c2aad932SGuodong Xu pinctrl-names = "default"; 333c2aad932SGuodong Xu pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 334a362ec8fSTyler Baker status = "disabled"; 335a362ec8fSTyler Baker }; 336a362ec8fSTyler Baker 337a362ec8fSTyler Baker uart3: uart@f7113000 { 338a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 339a362ec8fSTyler Baker reg = <0x0 0xf7113000 0x0 0x1000>; 340a362ec8fSTyler Baker interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 341a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART3_PCLK>, 342a362ec8fSTyler Baker <&sys_ctrl HI6220_UART3_PCLK>; 343a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 344c2aad932SGuodong Xu pinctrl-names = "default"; 345c2aad932SGuodong Xu pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 346c2aad932SGuodong Xu status = "disabled"; 347a362ec8fSTyler Baker }; 348a362ec8fSTyler Baker 349a362ec8fSTyler Baker uart4: uart@f7114000 { 350a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 351a362ec8fSTyler Baker reg = <0x0 0xf7114000 0x0 0x1000>; 352a362ec8fSTyler Baker interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 353a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART4_PCLK>, 354a362ec8fSTyler Baker <&sys_ctrl HI6220_UART4_PCLK>; 355a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 356c2aad932SGuodong Xu pinctrl-names = "default"; 357c2aad932SGuodong Xu pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 358a362ec8fSTyler Baker status = "disabled"; 359a362ec8fSTyler Baker }; 3609e927031SLeo Yan 3610cf6a8e2SJohn Stultz dma0: dma@f7370000 { 3620cf6a8e2SJohn Stultz compatible = "hisilicon,k3-dma-1.0"; 3630cf6a8e2SJohn Stultz reg = <0x0 0xf7370000 0x0 0x1000>; 3640cf6a8e2SJohn Stultz #dma-cells = <1>; 3650cf6a8e2SJohn Stultz dma-channels = <15>; 3660cf6a8e2SJohn Stultz dma-requests = <32>; 3670cf6a8e2SJohn Stultz interrupts = <0 84 4>; 3680cf6a8e2SJohn Stultz clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; 3690cf6a8e2SJohn Stultz dma-no-cci; 3700cf6a8e2SJohn Stultz dma-type = "hi6220_dma"; 3710cf6a8e2SJohn Stultz status = "ok"; 3720cf6a8e2SJohn Stultz }; 3730cf6a8e2SJohn Stultz 3749e927031SLeo Yan dual_timer0: timer@f8008000 { 3759e927031SLeo Yan compatible = "arm,sp804", "arm,primecell"; 3769e927031SLeo Yan reg = <0x0 0xf8008000 0x0 0x1000>; 3779e927031SLeo Yan interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 3789e927031SLeo Yan <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 3799e927031SLeo Yan clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, 3809e927031SLeo Yan <&ao_ctrl HI6220_TIMER0_PCLK>, 3819e927031SLeo Yan <&ao_ctrl HI6220_TIMER0_PCLK>; 3829e927031SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 3839e927031SLeo Yan }; 384f2bfacf9SZhong Kaihua 385810bd15fSZhangfei Gao rtc0: rtc@f8003000 { 386810bd15fSZhangfei Gao compatible = "arm,pl031", "arm,primecell"; 387810bd15fSZhangfei Gao reg = <0x0 0xf8003000 0x0 0x1000>; 388810bd15fSZhangfei Gao interrupts = <0 12 4>; 389810bd15fSZhangfei Gao clocks = <&ao_ctrl HI6220_RTC0_PCLK>; 390810bd15fSZhangfei Gao clock-names = "apb_pclk"; 391810bd15fSZhangfei Gao }; 392810bd15fSZhangfei Gao 393810bd15fSZhangfei Gao rtc1: rtc@f8004000 { 394810bd15fSZhangfei Gao compatible = "arm,pl031", "arm,primecell"; 395810bd15fSZhangfei Gao reg = <0x0 0xf8004000 0x0 0x1000>; 396810bd15fSZhangfei Gao interrupts = <0 8 4>; 397810bd15fSZhangfei Gao clocks = <&ao_ctrl HI6220_RTC1_PCLK>; 398810bd15fSZhangfei Gao clock-names = "apb_pclk"; 399810bd15fSZhangfei Gao }; 400810bd15fSZhangfei Gao 401379e9bf5SZhong Kaihua pmx0: pinmux@f7010000 { 402379e9bf5SZhong Kaihua compatible = "pinctrl-single"; 403379e9bf5SZhong Kaihua reg = <0x0 0xf7010000 0x0 0x27c>; 404379e9bf5SZhong Kaihua #address-cells = <1>; 405379e9bf5SZhong Kaihua #size-cells = <1>; 406be76fd31STony Lindgren #pinctrl-cells = <1>; 407379e9bf5SZhong Kaihua #gpio-range-cells = <3>; 408379e9bf5SZhong Kaihua pinctrl-single,register-width = <32>; 409379e9bf5SZhong Kaihua pinctrl-single,function-mask = <7>; 410379e9bf5SZhong Kaihua pinctrl-single,gpio-range = < 411379e9bf5SZhong Kaihua &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 412379e9bf5SZhong Kaihua &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 413379e9bf5SZhong Kaihua &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 414379e9bf5SZhong Kaihua &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 415379e9bf5SZhong Kaihua &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 416379e9bf5SZhong Kaihua &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 417379e9bf5SZhong Kaihua &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 418379e9bf5SZhong Kaihua &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 419379e9bf5SZhong Kaihua &range 0 1 MUX_M1 /* gpio 10: [0] */ 420379e9bf5SZhong Kaihua &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 421379e9bf5SZhong Kaihua &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 422379e9bf5SZhong Kaihua &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 423379e9bf5SZhong Kaihua &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 424379e9bf5SZhong Kaihua &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 425379e9bf5SZhong Kaihua &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 426379e9bf5SZhong Kaihua &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 427379e9bf5SZhong Kaihua &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 428379e9bf5SZhong Kaihua &range 122 1 MUX_M1 /* gpio 15: [6] */ 429379e9bf5SZhong Kaihua &range 126 1 MUX_M1 /* gpio 15: [7] */ 430379e9bf5SZhong Kaihua &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 431379e9bf5SZhong Kaihua &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 432379e9bf5SZhong Kaihua &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 433379e9bf5SZhong Kaihua &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 434379e9bf5SZhong Kaihua >; 435379e9bf5SZhong Kaihua range: gpio-range { 436379e9bf5SZhong Kaihua #pinctrl-single,gpio-range-cells = <3>; 437379e9bf5SZhong Kaihua }; 438379e9bf5SZhong Kaihua }; 439379e9bf5SZhong Kaihua 440379e9bf5SZhong Kaihua pmx1: pinmux@f7010800 { 441379e9bf5SZhong Kaihua compatible = "pinconf-single"; 442379e9bf5SZhong Kaihua reg = <0x0 0xf7010800 0x0 0x28c>; 443379e9bf5SZhong Kaihua #address-cells = <1>; 444379e9bf5SZhong Kaihua #size-cells = <1>; 445be76fd31STony Lindgren #pinctrl-cells = <1>; 446379e9bf5SZhong Kaihua pinctrl-single,register-width = <32>; 447379e9bf5SZhong Kaihua }; 448379e9bf5SZhong Kaihua 449379e9bf5SZhong Kaihua pmx2: pinmux@f8001800 { 450379e9bf5SZhong Kaihua compatible = "pinconf-single"; 451379e9bf5SZhong Kaihua reg = <0x0 0xf8001800 0x0 0x78>; 452379e9bf5SZhong Kaihua #address-cells = <1>; 453379e9bf5SZhong Kaihua #size-cells = <1>; 454be76fd31STony Lindgren #pinctrl-cells = <1>; 455379e9bf5SZhong Kaihua pinctrl-single,register-width = <32>; 456379e9bf5SZhong Kaihua }; 457379e9bf5SZhong Kaihua 458f2bfacf9SZhong Kaihua gpio0: gpio@f8011000 { 459f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 460f2bfacf9SZhong Kaihua reg = <0x0 0xf8011000 0x0 0x1000>; 461f2bfacf9SZhong Kaihua interrupts = <0 52 0x4>; 462f2bfacf9SZhong Kaihua gpio-controller; 463f2bfacf9SZhong Kaihua #gpio-cells = <2>; 464f2bfacf9SZhong Kaihua interrupt-controller; 465f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 466f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 467f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 468f2bfacf9SZhong Kaihua }; 469f2bfacf9SZhong Kaihua 470f2bfacf9SZhong Kaihua gpio1: gpio@f8012000 { 471f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 472f2bfacf9SZhong Kaihua reg = <0x0 0xf8012000 0x0 0x1000>; 473f2bfacf9SZhong Kaihua interrupts = <0 53 0x4>; 474f2bfacf9SZhong Kaihua gpio-controller; 475f2bfacf9SZhong Kaihua #gpio-cells = <2>; 476f2bfacf9SZhong Kaihua interrupt-controller; 477f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 478f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 479f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 480f2bfacf9SZhong Kaihua }; 481f2bfacf9SZhong Kaihua 482f2bfacf9SZhong Kaihua gpio2: gpio@f8013000 { 483f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 484f2bfacf9SZhong Kaihua reg = <0x0 0xf8013000 0x0 0x1000>; 485f2bfacf9SZhong Kaihua interrupts = <0 54 0x4>; 486f2bfacf9SZhong Kaihua gpio-controller; 487f2bfacf9SZhong Kaihua #gpio-cells = <2>; 488f2bfacf9SZhong Kaihua interrupt-controller; 489f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 490f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 491f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 492f2bfacf9SZhong Kaihua }; 493f2bfacf9SZhong Kaihua 494f2bfacf9SZhong Kaihua gpio3: gpio@f8014000 { 495f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 496f2bfacf9SZhong Kaihua reg = <0x0 0xf8014000 0x0 0x1000>; 497f2bfacf9SZhong Kaihua interrupts = <0 55 0x4>; 498f2bfacf9SZhong Kaihua gpio-controller; 499f2bfacf9SZhong Kaihua #gpio-cells = <2>; 500379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 80 8>; 501f2bfacf9SZhong Kaihua interrupt-controller; 502f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 503f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 504f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 505f2bfacf9SZhong Kaihua }; 506f2bfacf9SZhong Kaihua 507f2bfacf9SZhong Kaihua gpio4: gpio@f7020000 { 508f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 509f2bfacf9SZhong Kaihua reg = <0x0 0xf7020000 0x0 0x1000>; 510f2bfacf9SZhong Kaihua interrupts = <0 56 0x4>; 511f2bfacf9SZhong Kaihua gpio-controller; 512f2bfacf9SZhong Kaihua #gpio-cells = <2>; 513379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 88 8>; 514f2bfacf9SZhong Kaihua interrupt-controller; 515f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 516f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 517f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 518f2bfacf9SZhong Kaihua }; 519f2bfacf9SZhong Kaihua 520f2bfacf9SZhong Kaihua gpio5: gpio@f7021000 { 521f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 522f2bfacf9SZhong Kaihua reg = <0x0 0xf7021000 0x0 0x1000>; 523f2bfacf9SZhong Kaihua interrupts = <0 57 0x4>; 524f2bfacf9SZhong Kaihua gpio-controller; 525f2bfacf9SZhong Kaihua #gpio-cells = <2>; 526379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 96 8>; 527f2bfacf9SZhong Kaihua interrupt-controller; 528f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 529f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 530f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 531f2bfacf9SZhong Kaihua }; 532f2bfacf9SZhong Kaihua 533f2bfacf9SZhong Kaihua gpio6: gpio@f7022000 { 534f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 535f2bfacf9SZhong Kaihua reg = <0x0 0xf7022000 0x0 0x1000>; 536f2bfacf9SZhong Kaihua interrupts = <0 58 0x4>; 537f2bfacf9SZhong Kaihua gpio-controller; 538f2bfacf9SZhong Kaihua #gpio-cells = <2>; 539379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 104 8>; 540f2bfacf9SZhong Kaihua interrupt-controller; 541f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 542f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 543f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 544f2bfacf9SZhong Kaihua }; 545f2bfacf9SZhong Kaihua 546f2bfacf9SZhong Kaihua gpio7: gpio@f7023000 { 547f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 548f2bfacf9SZhong Kaihua reg = <0x0 0xf7023000 0x0 0x1000>; 549f2bfacf9SZhong Kaihua interrupts = <0 59 0x4>; 550f2bfacf9SZhong Kaihua gpio-controller; 551f2bfacf9SZhong Kaihua #gpio-cells = <2>; 552379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 112 8>; 553f2bfacf9SZhong Kaihua interrupt-controller; 554f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 555f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 556f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 557f2bfacf9SZhong Kaihua }; 558f2bfacf9SZhong Kaihua 559f2bfacf9SZhong Kaihua gpio8: gpio@f7024000 { 560f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 561f2bfacf9SZhong Kaihua reg = <0x0 0xf7024000 0x0 0x1000>; 562f2bfacf9SZhong Kaihua interrupts = <0 60 0x4>; 563f2bfacf9SZhong Kaihua gpio-controller; 564f2bfacf9SZhong Kaihua #gpio-cells = <2>; 565379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 566f2bfacf9SZhong Kaihua interrupt-controller; 567f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 568f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 569f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 570f2bfacf9SZhong Kaihua }; 571f2bfacf9SZhong Kaihua 572f2bfacf9SZhong Kaihua gpio9: gpio@f7025000 { 573f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 574f2bfacf9SZhong Kaihua reg = <0x0 0xf7025000 0x0 0x1000>; 575f2bfacf9SZhong Kaihua interrupts = <0 61 0x4>; 576f2bfacf9SZhong Kaihua gpio-controller; 577f2bfacf9SZhong Kaihua #gpio-cells = <2>; 578379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 8 8>; 579f2bfacf9SZhong Kaihua interrupt-controller; 580f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 581f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 582f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 583f2bfacf9SZhong Kaihua }; 584f2bfacf9SZhong Kaihua 585f2bfacf9SZhong Kaihua gpio10: gpio@f7026000 { 586f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 587f2bfacf9SZhong Kaihua reg = <0x0 0xf7026000 0x0 0x1000>; 588f2bfacf9SZhong Kaihua interrupts = <0 62 0x4>; 589f2bfacf9SZhong Kaihua gpio-controller; 590f2bfacf9SZhong Kaihua #gpio-cells = <2>; 591379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 592f2bfacf9SZhong Kaihua interrupt-controller; 593f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 594f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 595f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 596f2bfacf9SZhong Kaihua }; 597f2bfacf9SZhong Kaihua 598f2bfacf9SZhong Kaihua gpio11: gpio@f7027000 { 599f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 600f2bfacf9SZhong Kaihua reg = <0x0 0xf7027000 0x0 0x1000>; 601f2bfacf9SZhong Kaihua interrupts = <0 63 0x4>; 602f2bfacf9SZhong Kaihua gpio-controller; 603f2bfacf9SZhong Kaihua #gpio-cells = <2>; 604379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 605f2bfacf9SZhong Kaihua interrupt-controller; 606f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 607f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 608f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 609f2bfacf9SZhong Kaihua }; 610f2bfacf9SZhong Kaihua 611f2bfacf9SZhong Kaihua gpio12: gpio@f7028000 { 612f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 613f2bfacf9SZhong Kaihua reg = <0x0 0xf7028000 0x0 0x1000>; 614f2bfacf9SZhong Kaihua interrupts = <0 64 0x4>; 615f2bfacf9SZhong Kaihua gpio-controller; 616f2bfacf9SZhong Kaihua #gpio-cells = <2>; 617379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 618f2bfacf9SZhong Kaihua interrupt-controller; 619f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 620f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 621f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 622f2bfacf9SZhong Kaihua }; 623f2bfacf9SZhong Kaihua 624f2bfacf9SZhong Kaihua gpio13: gpio@f7029000 { 625f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 626f2bfacf9SZhong Kaihua reg = <0x0 0xf7029000 0x0 0x1000>; 627f2bfacf9SZhong Kaihua interrupts = <0 65 0x4>; 628f2bfacf9SZhong Kaihua gpio-controller; 629379e9bf5SZhong Kaihua #gpio-cells = <2>; 630379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 48 8>; 631f2bfacf9SZhong Kaihua interrupt-controller; 632f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 633f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 634f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 635f2bfacf9SZhong Kaihua }; 636f2bfacf9SZhong Kaihua 637f2bfacf9SZhong Kaihua gpio14: gpio@f702a000 { 638f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 639f2bfacf9SZhong Kaihua reg = <0x0 0xf702a000 0x0 0x1000>; 640f2bfacf9SZhong Kaihua interrupts = <0 66 0x4>; 641f2bfacf9SZhong Kaihua gpio-controller; 642f2bfacf9SZhong Kaihua #gpio-cells = <2>; 643379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 56 8>; 644f2bfacf9SZhong Kaihua interrupt-controller; 645f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 646f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 647f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 648f2bfacf9SZhong Kaihua }; 649f2bfacf9SZhong Kaihua 650f2bfacf9SZhong Kaihua gpio15: gpio@f702b000 { 651f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 652f2bfacf9SZhong Kaihua reg = <0x0 0xf702b000 0x0 0x1000>; 653f2bfacf9SZhong Kaihua interrupts = <0 67 0x4>; 654f2bfacf9SZhong Kaihua gpio-controller; 655f2bfacf9SZhong Kaihua #gpio-cells = <2>; 656379e9bf5SZhong Kaihua gpio-ranges = < 657379e9bf5SZhong Kaihua &pmx0 0 74 6 658379e9bf5SZhong Kaihua &pmx0 6 122 1 659379e9bf5SZhong Kaihua &pmx0 7 126 1 660379e9bf5SZhong Kaihua >; 661f2bfacf9SZhong Kaihua interrupt-controller; 662f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 663f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 664f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 665f2bfacf9SZhong Kaihua }; 666f2bfacf9SZhong Kaihua 667f2bfacf9SZhong Kaihua gpio16: gpio@f702c000 { 668f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 669f2bfacf9SZhong Kaihua reg = <0x0 0xf702c000 0x0 0x1000>; 670f2bfacf9SZhong Kaihua interrupts = <0 68 0x4>; 671f2bfacf9SZhong Kaihua gpio-controller; 672f2bfacf9SZhong Kaihua #gpio-cells = <2>; 673379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 127 8>; 674f2bfacf9SZhong Kaihua interrupt-controller; 675f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 676f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 677f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 678f2bfacf9SZhong Kaihua }; 679f2bfacf9SZhong Kaihua 680f2bfacf9SZhong Kaihua gpio17: gpio@f702d000 { 681f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 682f2bfacf9SZhong Kaihua reg = <0x0 0xf702d000 0x0 0x1000>; 683f2bfacf9SZhong Kaihua interrupts = <0 69 0x4>; 684f2bfacf9SZhong Kaihua gpio-controller; 685f2bfacf9SZhong Kaihua #gpio-cells = <2>; 686379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 135 8>; 687f2bfacf9SZhong Kaihua interrupt-controller; 688f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 689f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 690f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 691f2bfacf9SZhong Kaihua }; 692f2bfacf9SZhong Kaihua 693f2bfacf9SZhong Kaihua gpio18: gpio@f702e000 { 694f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 695f2bfacf9SZhong Kaihua reg = <0x0 0xf702e000 0x0 0x1000>; 696f2bfacf9SZhong Kaihua interrupts = <0 70 0x4>; 697f2bfacf9SZhong Kaihua gpio-controller; 698f2bfacf9SZhong Kaihua #gpio-cells = <2>; 699379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 143 8>; 700f2bfacf9SZhong Kaihua interrupt-controller; 701f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 702f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 703f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 704f2bfacf9SZhong Kaihua }; 705f2bfacf9SZhong Kaihua 706f2bfacf9SZhong Kaihua gpio19: gpio@f702f000 { 707f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 708f2bfacf9SZhong Kaihua reg = <0x0 0xf702f000 0x0 0x1000>; 709f2bfacf9SZhong Kaihua interrupts = <0 71 0x4>; 710f2bfacf9SZhong Kaihua gpio-controller; 711f2bfacf9SZhong Kaihua #gpio-cells = <2>; 712379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 151 8>; 713f2bfacf9SZhong Kaihua interrupt-controller; 714f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 715f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 716f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 717f2bfacf9SZhong Kaihua }; 71860dac1b1SZhong Kaihua 71960dac1b1SZhong Kaihua spi0: spi@f7106000 { 72060dac1b1SZhong Kaihua compatible = "arm,pl022", "arm,primecell"; 72160dac1b1SZhong Kaihua reg = <0x0 0xf7106000 0x0 0x1000>; 72260dac1b1SZhong Kaihua interrupts = <0 50 4>; 72360dac1b1SZhong Kaihua bus-id = <0>; 72460dac1b1SZhong Kaihua enable-dma = <0>; 72560dac1b1SZhong Kaihua clocks = <&sys_ctrl HI6220_SPI_CLK>; 72660dac1b1SZhong Kaihua clock-names = "apb_pclk"; 72760dac1b1SZhong Kaihua pinctrl-names = "default"; 72860dac1b1SZhong Kaihua pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 72960dac1b1SZhong Kaihua num-cs = <1>; 73060dac1b1SZhong Kaihua cs-gpios = <&gpio6 2 0>; 73160dac1b1SZhong Kaihua status = "disabled"; 73260dac1b1SZhong Kaihua }; 7335ff3a4ddSXinwei Kong 7345ff3a4ddSXinwei Kong i2c0: i2c@f7100000 { 7355ff3a4ddSXinwei Kong compatible = "snps,designware-i2c"; 7365ff3a4ddSXinwei Kong reg = <0x0 0xf7100000 0x0 0x1000>; 7375ff3a4ddSXinwei Kong interrupts = <0 44 4>; 7385ff3a4ddSXinwei Kong clocks = <&sys_ctrl HI6220_I2C0_CLK>; 7395ff3a4ddSXinwei Kong i2c-sda-hold-time-ns = <300>; 7405ff3a4ddSXinwei Kong pinctrl-names = "default"; 7415ff3a4ddSXinwei Kong pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 7425ff3a4ddSXinwei Kong status = "disabled"; 7435ff3a4ddSXinwei Kong }; 7445ff3a4ddSXinwei Kong 7455ff3a4ddSXinwei Kong i2c1: i2c@f7101000 { 7465ff3a4ddSXinwei Kong compatible = "snps,designware-i2c"; 7475ff3a4ddSXinwei Kong reg = <0x0 0xf7101000 0x0 0x1000>; 7485ff3a4ddSXinwei Kong clocks = <&sys_ctrl HI6220_I2C1_CLK>; 7495ff3a4ddSXinwei Kong interrupts = <0 45 4>; 7505ff3a4ddSXinwei Kong i2c-sda-hold-time-ns = <300>; 7515ff3a4ddSXinwei Kong pinctrl-names = "default"; 7525ff3a4ddSXinwei Kong pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 7535ff3a4ddSXinwei Kong status = "disabled"; 7545ff3a4ddSXinwei Kong }; 7555ff3a4ddSXinwei Kong 7565ff3a4ddSXinwei Kong i2c2: i2c@f7102000 { 7575ff3a4ddSXinwei Kong compatible = "snps,designware-i2c"; 7585ff3a4ddSXinwei Kong reg = <0x0 0xf7102000 0x0 0x1000>; 7595ff3a4ddSXinwei Kong clocks = <&sys_ctrl HI6220_I2C2_CLK>; 7605ff3a4ddSXinwei Kong interrupts = <0 46 4>; 7615ff3a4ddSXinwei Kong i2c-sda-hold-time-ns = <300>; 7625ff3a4ddSXinwei Kong pinctrl-names = "default"; 7635ff3a4ddSXinwei Kong pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 7645ff3a4ddSXinwei Kong status = "disabled"; 7655ff3a4ddSXinwei Kong }; 766b4b31a7cSZhangfei Gao 767b4b31a7cSZhangfei Gao usb_phy: usbphy { 768b4b31a7cSZhangfei Gao compatible = "hisilicon,hi6220-usb-phy"; 769b4b31a7cSZhangfei Gao #phy-cells = <0>; 7701b32a5ffSUlf Hansson phy-supply = <®_5v_hub>; 771b4b31a7cSZhangfei Gao hisilicon,peripheral-syscon = <&sys_ctrl>; 772b4b31a7cSZhangfei Gao }; 773b4b31a7cSZhangfei Gao 774b4b31a7cSZhangfei Gao usb: usb@f72c0000 { 775b4b31a7cSZhangfei Gao compatible = "hisilicon,hi6220-usb"; 776b4b31a7cSZhangfei Gao reg = <0x0 0xf72c0000 0x0 0x40000>; 777b4b31a7cSZhangfei Gao phys = <&usb_phy>; 778b4b31a7cSZhangfei Gao phy-names = "usb2-phy"; 779b4b31a7cSZhangfei Gao clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 780b4b31a7cSZhangfei Gao clock-names = "otg"; 781b4b31a7cSZhangfei Gao dr_mode = "otg"; 782b4b31a7cSZhangfei Gao g-rx-fifo-size = <512>; 783b4b31a7cSZhangfei Gao g-np-tx-fifo-size = <128>; 784341b26b7SShawn Guo g-tx-fifo-size = <128 128 128 128 128 128 128 128 785341b26b7SShawn Guo 16 16 16 16 16 16 16>; 786b4b31a7cSZhangfei Gao interrupts = <0 77 0x4>; 787b4b31a7cSZhangfei Gao }; 78886073570SLeo Yan 78986073570SLeo Yan mailbox: mailbox@f7510000 { 79086073570SLeo Yan compatible = "hisilicon,hi6220-mbox"; 79186073570SLeo Yan reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 79286073570SLeo Yan <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 79386073570SLeo Yan interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 79486073570SLeo Yan #mbox-cells = <3>; 79586073570SLeo Yan }; 796d6b259d4SXinwei Kong 797d6b259d4SXinwei Kong dwmmc_0: dwmmc0@f723d000 { 798d6b259d4SXinwei Kong compatible = "hisilicon,hi6220-dw-mshc"; 799d6b259d4SXinwei Kong reg = <0x0 0xf723d000 0x0 0x1000>; 800d6b259d4SXinwei Kong interrupts = <0x0 0x48 0x4>; 801d6b259d4SXinwei Kong clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; 802d6b259d4SXinwei Kong clock-names = "ciu", "biu"; 80394914fc8SGuodong Xu resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; 8040fbdf995SDaniel Lezcano reset-names = "reset"; 805d6b259d4SXinwei Kong pinctrl-names = "default"; 806d6b259d4SXinwei Kong pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func 807d6b259d4SXinwei Kong &emmc_cfg_func &emmc_rst_cfg_func>; 808d6b259d4SXinwei Kong }; 809d6b259d4SXinwei Kong 810d6b259d4SXinwei Kong dwmmc_1: dwmmc1@f723e000 { 811d6b259d4SXinwei Kong compatible = "hisilicon,hi6220-dw-mshc"; 812d6b259d4SXinwei Kong hisilicon,peripheral-syscon = <&ao_ctrl>; 813d6b259d4SXinwei Kong reg = <0x0 0xf723e000 0x0 0x1000>; 814d6b259d4SXinwei Kong interrupts = <0x0 0x49 0x4>; 815d6b259d4SXinwei Kong #address-cells = <0x1>; 816d6b259d4SXinwei Kong #size-cells = <0x0>; 817d6b259d4SXinwei Kong clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; 818d6b259d4SXinwei Kong clock-names = "ciu", "biu"; 81994914fc8SGuodong Xu resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; 8200fbdf995SDaniel Lezcano reset-names = "reset"; 821d6b259d4SXinwei Kong pinctrl-names = "default", "idle"; 822d6b259d4SXinwei Kong pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; 823d6b259d4SXinwei Kong pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; 824d6b259d4SXinwei Kong }; 825d6b259d4SXinwei Kong 826d6b259d4SXinwei Kong dwmmc_2: dwmmc2@f723f000 { 827d6b259d4SXinwei Kong compatible = "hisilicon,hi6220-dw-mshc"; 828d6b259d4SXinwei Kong reg = <0x0 0xf723f000 0x0 0x1000>; 829d6b259d4SXinwei Kong interrupts = <0x0 0x4a 0x4>; 830d6b259d4SXinwei Kong clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; 831d6b259d4SXinwei Kong clock-names = "ciu", "biu"; 83294914fc8SGuodong Xu resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; 8330fbdf995SDaniel Lezcano reset-names = "reset"; 834d6b259d4SXinwei Kong pinctrl-names = "default", "idle"; 835d6b259d4SXinwei Kong pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; 836d6b259d4SXinwei Kong pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; 837d6b259d4SXinwei Kong }; 8382158ab08SLeo Yan 8396bbec98eSDmitry Shmidt watchdog0: watchdog@f8005000 { 8406bbec98eSDmitry Shmidt compatible = "arm,sp805-wdt", "arm,primecell"; 8416bbec98eSDmitry Shmidt reg = <0x0 0xf8005000 0x0 0x1000>; 8426bbec98eSDmitry Shmidt interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8436bbec98eSDmitry Shmidt clocks = <&ao_ctrl HI6220_WDT0_PCLK>; 8446bbec98eSDmitry Shmidt clock-names = "apb_pclk"; 8456bbec98eSDmitry Shmidt }; 8466bbec98eSDmitry Shmidt 8472158ab08SLeo Yan tsensor: tsensor@0,f7030700 { 8482158ab08SLeo Yan compatible = "hisilicon,tsensor"; 8492158ab08SLeo Yan reg = <0x0 0xf7030700 0x0 0x1000>; 8502158ab08SLeo Yan interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 8512158ab08SLeo Yan clocks = <&sys_ctrl 22>; 8522158ab08SLeo Yan clock-names = "thermal_clk"; 8532158ab08SLeo Yan #thermal-sensor-cells = <1>; 8542158ab08SLeo Yan }; 855cd0b69ecSLeo Yan 8560cf6a8e2SJohn Stultz i2s0: i2s@f7118000{ 8570cf6a8e2SJohn Stultz compatible = "hisilicon,hi6210-i2s"; 8580cf6a8e2SJohn Stultz reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ 8590cf6a8e2SJohn Stultz interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */ 8600cf6a8e2SJohn Stultz clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, 8610cf6a8e2SJohn Stultz <&sys_ctrl HI6220_BBPPLL0_DIV>; 8620cf6a8e2SJohn Stultz clock-names = "dacodec", "i2s-base"; 8630cf6a8e2SJohn Stultz dmas = <&dma0 15 &dma0 14>; 8640cf6a8e2SJohn Stultz dma-names = "rx", "tx"; 8650cf6a8e2SJohn Stultz hisilicon,sysctrl-syscon = <&sys_ctrl>; 8660cf6a8e2SJohn Stultz #sound-dai-cells = <1>; 8670cf6a8e2SJohn Stultz }; 8680cf6a8e2SJohn Stultz 869cd0b69ecSLeo Yan thermal-zones { 870cd0b69ecSLeo Yan 871cd0b69ecSLeo Yan cls0: cls0 { 872cd0b69ecSLeo Yan polling-delay = <1000>; 873cd0b69ecSLeo Yan polling-delay-passive = <100>; 874cd0b69ecSLeo Yan sustainable-power = <3326>; 875cd0b69ecSLeo Yan 876cd0b69ecSLeo Yan /* sensor ID */ 877cd0b69ecSLeo Yan thermal-sensors = <&tsensor 2>; 878cd0b69ecSLeo Yan 879cd0b69ecSLeo Yan trips { 880cd0b69ecSLeo Yan threshold: trip-point@0 { 881cd0b69ecSLeo Yan temperature = <65000>; 882cd0b69ecSLeo Yan hysteresis = <0>; 883cd0b69ecSLeo Yan type = "passive"; 884cd0b69ecSLeo Yan }; 885cd0b69ecSLeo Yan 886cd0b69ecSLeo Yan target: trip-point@1 { 887cd0b69ecSLeo Yan temperature = <75000>; 888cd0b69ecSLeo Yan hysteresis = <0>; 889cd0b69ecSLeo Yan type = "passive"; 890cd0b69ecSLeo Yan }; 891cd0b69ecSLeo Yan }; 892cd0b69ecSLeo Yan 893cd0b69ecSLeo Yan cooling-maps { 894cd0b69ecSLeo Yan map0 { 895cd0b69ecSLeo Yan trip = <&target>; 8966ad5506eSViresh Kumar cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 8976ad5506eSViresh Kumar <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 8986ad5506eSViresh Kumar <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 8996ad5506eSViresh Kumar <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 9006ad5506eSViresh Kumar <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 9016ad5506eSViresh Kumar <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 9026ad5506eSViresh Kumar <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 9036ad5506eSViresh Kumar <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 904cd0b69ecSLeo Yan }; 905cd0b69ecSLeo Yan }; 906cd0b69ecSLeo Yan }; 907cd0b69ecSLeo Yan }; 9083814b61bSXinliang Liu 9093814b61bSXinliang Liu ade: ade@f4100000 { 9103814b61bSXinliang Liu compatible = "hisilicon,hi6220-ade"; 9113814b61bSXinliang Liu reg = <0x0 0xf4100000 0x0 0x7800>; 9123814b61bSXinliang Liu reg-names = "ade_base"; 9133814b61bSXinliang Liu hisilicon,noc-syscon = <&medianoc_ade>; 9143814b61bSXinliang Liu resets = <&media_ctrl MEDIA_ADE>; 9153814b61bSXinliang Liu interrupts = <0 115 4>; /* ldi interrupt */ 9163814b61bSXinliang Liu 9173814b61bSXinliang Liu clocks = <&media_ctrl HI6220_ADE_CORE>, 9183814b61bSXinliang Liu <&media_ctrl HI6220_CODEC_JPEG>, 9193814b61bSXinliang Liu <&media_ctrl HI6220_ADE_PIX_SRC>; 9203814b61bSXinliang Liu /*clock name*/ 9213814b61bSXinliang Liu clock-names = "clk_ade_core", 9223814b61bSXinliang Liu "clk_codec_jpeg", 9233814b61bSXinliang Liu "clk_ade_pix"; 9243814b61bSXinliang Liu 9253814b61bSXinliang Liu assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, 9263814b61bSXinliang Liu <&media_ctrl HI6220_CODEC_JPEG>; 9273814b61bSXinliang Liu assigned-clock-rates = <360000000>, <288000000>; 9283814b61bSXinliang Liu dma-coherent; 9293814b61bSXinliang Liu status = "disabled"; 9303814b61bSXinliang Liu 9313814b61bSXinliang Liu port { 9323814b61bSXinliang Liu ade_out: endpoint { 9333814b61bSXinliang Liu remote-endpoint = <&dsi_in>; 9343814b61bSXinliang Liu }; 9353814b61bSXinliang Liu }; 9363814b61bSXinliang Liu }; 9373814b61bSXinliang Liu 9383814b61bSXinliang Liu dsi: dsi@f4107800 { 9393814b61bSXinliang Liu compatible = "hisilicon,hi6220-dsi"; 9403814b61bSXinliang Liu reg = <0x0 0xf4107800 0x0 0x100>; 9413814b61bSXinliang Liu clocks = <&media_ctrl HI6220_DSI_PCLK>; 9423814b61bSXinliang Liu clock-names = "pclk"; 9433814b61bSXinliang Liu status = "disabled"; 9443814b61bSXinliang Liu 9453814b61bSXinliang Liu ports { 9463814b61bSXinliang Liu #address-cells = <1>; 9473814b61bSXinliang Liu #size-cells = <0>; 9483814b61bSXinliang Liu 9493814b61bSXinliang Liu /* 0 for input port */ 9503814b61bSXinliang Liu port@0 { 9513814b61bSXinliang Liu reg = <0>; 9523814b61bSXinliang Liu dsi_in: endpoint { 9533814b61bSXinliang Liu remote-endpoint = <&ade_out>; 9543814b61bSXinliang Liu }; 9553814b61bSXinliang Liu }; 9563814b61bSXinliang Liu }; 9573814b61bSXinliang Liu }; 9584fcf9a62SLeo Yan 9594fcf9a62SLeo Yan debug@f6590000 { 9604fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9614fcf9a62SLeo Yan reg = <0 0xf6590000 0 0x1000>; 9624fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9634fcf9a62SLeo Yan clock-names = "apb_pclk"; 9644fcf9a62SLeo Yan cpu = <&cpu0>; 9654fcf9a62SLeo Yan }; 9664fcf9a62SLeo Yan 9674fcf9a62SLeo Yan debug@f6592000 { 9684fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9694fcf9a62SLeo Yan reg = <0 0xf6592000 0 0x1000>; 9704fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9714fcf9a62SLeo Yan clock-names = "apb_pclk"; 9724fcf9a62SLeo Yan cpu = <&cpu1>; 9734fcf9a62SLeo Yan }; 9744fcf9a62SLeo Yan 9754fcf9a62SLeo Yan debug@f6594000 { 9764fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9774fcf9a62SLeo Yan reg = <0 0xf6594000 0 0x1000>; 9784fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9794fcf9a62SLeo Yan clock-names = "apb_pclk"; 9804fcf9a62SLeo Yan cpu = <&cpu2>; 9814fcf9a62SLeo Yan }; 9824fcf9a62SLeo Yan 9834fcf9a62SLeo Yan debug@f6596000 { 9844fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9854fcf9a62SLeo Yan reg = <0 0xf6596000 0 0x1000>; 9864fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9874fcf9a62SLeo Yan clock-names = "apb_pclk"; 9884fcf9a62SLeo Yan cpu = <&cpu3>; 9894fcf9a62SLeo Yan }; 9904fcf9a62SLeo Yan 9914fcf9a62SLeo Yan debug@f65d0000 { 9924fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 9934fcf9a62SLeo Yan reg = <0 0xf65d0000 0 0x1000>; 9944fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 9954fcf9a62SLeo Yan clock-names = "apb_pclk"; 9964fcf9a62SLeo Yan cpu = <&cpu4>; 9974fcf9a62SLeo Yan }; 9984fcf9a62SLeo Yan 9994fcf9a62SLeo Yan debug@f65d2000 { 10004fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 10014fcf9a62SLeo Yan reg = <0 0xf65d2000 0 0x1000>; 10024fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 10034fcf9a62SLeo Yan clock-names = "apb_pclk"; 10044fcf9a62SLeo Yan cpu = <&cpu5>; 10054fcf9a62SLeo Yan }; 10064fcf9a62SLeo Yan 10074fcf9a62SLeo Yan debug@f65d4000 { 10084fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 10094fcf9a62SLeo Yan reg = <0 0xf65d4000 0 0x1000>; 10104fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 10114fcf9a62SLeo Yan clock-names = "apb_pclk"; 10124fcf9a62SLeo Yan cpu = <&cpu6>; 10134fcf9a62SLeo Yan }; 10144fcf9a62SLeo Yan 10154fcf9a62SLeo Yan debug@f65d6000 { 10164fcf9a62SLeo Yan compatible = "arm,coresight-cpu-debug","arm,primecell"; 10174fcf9a62SLeo Yan reg = <0 0xf65d6000 0 0x1000>; 10184fcf9a62SLeo Yan clocks = <&sys_ctrl HI6220_DAPB_CLK>; 10194fcf9a62SLeo Yan clock-names = "apb_pclk"; 10204fcf9a62SLeo Yan cpu = <&cpu7>; 10214fcf9a62SLeo Yan }; 102286e8f528SBintian Wang }; 102386e8f528SBintian Wang}; 10240b798427SLi Pengcheng 10250b798427SLi Pengcheng#include "hi6220-coresight.dtsi" 1026