186e8f528SBintian Wang/* 286e8f528SBintian Wang * dts file for Hisilicon Hi6220 SoC 386e8f528SBintian Wang * 486e8f528SBintian Wang * Copyright (C) 2015, Hisilicon Ltd. 586e8f528SBintian Wang */ 686e8f528SBintian Wang 786e8f528SBintian Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 8a362ec8fSTyler Baker#include <dt-bindings/clock/hi6220-clock.h> 9379e9bf5SZhong Kaihua#include <dt-bindings/pinctrl/hisi.h> 10cd0b69ecSLeo Yan#include <dt-bindings/thermal/thermal.h> 1186e8f528SBintian Wang 1286e8f528SBintian Wang/ { 1386e8f528SBintian Wang compatible = "hisilicon,hi6220"; 1486e8f528SBintian Wang interrupt-parent = <&gic>; 1586e8f528SBintian Wang #address-cells = <2>; 1686e8f528SBintian Wang #size-cells = <2>; 1786e8f528SBintian Wang 1886e8f528SBintian Wang psci { 1986e8f528SBintian Wang compatible = "arm,psci-0.2"; 2086e8f528SBintian Wang method = "smc"; 2186e8f528SBintian Wang }; 2286e8f528SBintian Wang 2386e8f528SBintian Wang cpus { 2486e8f528SBintian Wang #address-cells = <2>; 2586e8f528SBintian Wang #size-cells = <0>; 2686e8f528SBintian Wang 2786e8f528SBintian Wang cpu-map { 2886e8f528SBintian Wang cluster0 { 2986e8f528SBintian Wang core0 { 3086e8f528SBintian Wang cpu = <&cpu0>; 3186e8f528SBintian Wang }; 3286e8f528SBintian Wang core1 { 3386e8f528SBintian Wang cpu = <&cpu1>; 3486e8f528SBintian Wang }; 3586e8f528SBintian Wang core2 { 3686e8f528SBintian Wang cpu = <&cpu2>; 3786e8f528SBintian Wang }; 3886e8f528SBintian Wang core3 { 3986e8f528SBintian Wang cpu = <&cpu3>; 4086e8f528SBintian Wang }; 4186e8f528SBintian Wang }; 4286e8f528SBintian Wang cluster1 { 4386e8f528SBintian Wang core0 { 4486e8f528SBintian Wang cpu = <&cpu4>; 4586e8f528SBintian Wang }; 4686e8f528SBintian Wang core1 { 4786e8f528SBintian Wang cpu = <&cpu5>; 4886e8f528SBintian Wang }; 4986e8f528SBintian Wang core2 { 5086e8f528SBintian Wang cpu = <&cpu6>; 5186e8f528SBintian Wang }; 5286e8f528SBintian Wang core3 { 5386e8f528SBintian Wang cpu = <&cpu7>; 5486e8f528SBintian Wang }; 5586e8f528SBintian Wang }; 5686e8f528SBintian Wang }; 5786e8f528SBintian Wang 5858fa29bfSLeo Yan idle-states { 5958fa29bfSLeo Yan entry-method = "psci"; 6058fa29bfSLeo Yan 6158fa29bfSLeo Yan CPU_SLEEP: cpu-sleep { 6258fa29bfSLeo Yan compatible = "arm,idle-state"; 6358fa29bfSLeo Yan local-timer-stop; 6458fa29bfSLeo Yan arm,psci-suspend-param = <0x0010000>; 6558fa29bfSLeo Yan entry-latency-us = <700>; 6658fa29bfSLeo Yan exit-latency-us = <250>; 6758fa29bfSLeo Yan min-residency-us = <1000>; 6858fa29bfSLeo Yan }; 6958fa29bfSLeo Yan 7058fa29bfSLeo Yan CLUSTER_SLEEP: cluster-sleep { 7158fa29bfSLeo Yan compatible = "arm,idle-state"; 7258fa29bfSLeo Yan local-timer-stop; 7358fa29bfSLeo Yan arm,psci-suspend-param = <0x1010000>; 7458fa29bfSLeo Yan entry-latency-us = <1000>; 7558fa29bfSLeo Yan exit-latency-us = <700>; 7658fa29bfSLeo Yan min-residency-us = <2700>; 7758fa29bfSLeo Yan wakeup-latency-us = <1500>; 7858fa29bfSLeo Yan }; 7958fa29bfSLeo Yan }; 8058fa29bfSLeo Yan 8186e8f528SBintian Wang cpu0: cpu@0 { 8286e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 8386e8f528SBintian Wang device_type = "cpu"; 8486e8f528SBintian Wang reg = <0x0 0x0>; 8586e8f528SBintian Wang enable-method = "psci"; 8664851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 8799860540SLeo Yan clocks = <&stub_clock 0>; 8899860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 8999860540SLeo Yan cooling-min-level = <4>; 9099860540SLeo Yan cooling-max-level = <0>; 9199860540SLeo Yan #cooling-cells = <2>; /* min followed by max */ 9258fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 93cd0b69ecSLeo Yan dynamic-power-coefficient = <311>; 9486e8f528SBintian Wang }; 9586e8f528SBintian Wang 9686e8f528SBintian Wang cpu1: cpu@1 { 9786e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 9886e8f528SBintian Wang device_type = "cpu"; 9986e8f528SBintian Wang reg = <0x0 0x1>; 10086e8f528SBintian Wang enable-method = "psci"; 10164851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 10299860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 10358fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 10486e8f528SBintian Wang }; 10586e8f528SBintian Wang 10686e8f528SBintian Wang cpu2: cpu@2 { 10786e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 10886e8f528SBintian Wang device_type = "cpu"; 10986e8f528SBintian Wang reg = <0x0 0x2>; 11086e8f528SBintian Wang enable-method = "psci"; 11164851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 11299860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 11358fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 11486e8f528SBintian Wang }; 11586e8f528SBintian Wang 11686e8f528SBintian Wang cpu3: cpu@3 { 11786e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 11886e8f528SBintian Wang device_type = "cpu"; 11986e8f528SBintian Wang reg = <0x0 0x3>; 12086e8f528SBintian Wang enable-method = "psci"; 12164851603SLeo Yan next-level-cache = <&CLUSTER0_L2>; 12299860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 12358fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 12486e8f528SBintian Wang }; 12586e8f528SBintian Wang 12686e8f528SBintian Wang cpu4: cpu@100 { 12786e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 12886e8f528SBintian Wang device_type = "cpu"; 12986e8f528SBintian Wang reg = <0x0 0x100>; 13086e8f528SBintian Wang enable-method = "psci"; 13164851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 13299860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 13358fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 13486e8f528SBintian Wang }; 13586e8f528SBintian Wang 13686e8f528SBintian Wang cpu5: cpu@101 { 13786e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 13886e8f528SBintian Wang device_type = "cpu"; 13986e8f528SBintian Wang reg = <0x0 0x101>; 14086e8f528SBintian Wang enable-method = "psci"; 14164851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 14299860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 14358fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 14486e8f528SBintian Wang }; 14586e8f528SBintian Wang 14686e8f528SBintian Wang cpu6: cpu@102 { 14786e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 14886e8f528SBintian Wang device_type = "cpu"; 14986e8f528SBintian Wang reg = <0x0 0x102>; 15086e8f528SBintian Wang enable-method = "psci"; 15164851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 15299860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 15358fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 15486e8f528SBintian Wang }; 15586e8f528SBintian Wang 15686e8f528SBintian Wang cpu7: cpu@103 { 15786e8f528SBintian Wang compatible = "arm,cortex-a53", "arm,armv8"; 15886e8f528SBintian Wang device_type = "cpu"; 15986e8f528SBintian Wang reg = <0x0 0x103>; 16086e8f528SBintian Wang enable-method = "psci"; 16164851603SLeo Yan next-level-cache = <&CLUSTER1_L2>; 16299860540SLeo Yan operating-points-v2 = <&cpu_opp_table>; 16358fa29bfSLeo Yan cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 16486e8f528SBintian Wang }; 16564851603SLeo Yan 16664851603SLeo Yan CLUSTER0_L2: l2-cache0 { 16764851603SLeo Yan compatible = "cache"; 16864851603SLeo Yan }; 16964851603SLeo Yan 17064851603SLeo Yan CLUSTER1_L2: l2-cache1 { 17164851603SLeo Yan compatible = "cache"; 17264851603SLeo Yan }; 17386e8f528SBintian Wang }; 17486e8f528SBintian Wang 17599860540SLeo Yan cpu_opp_table: cpu_opp_table { 17699860540SLeo Yan compatible = "operating-points-v2"; 17799860540SLeo Yan opp-shared; 17899860540SLeo Yan 17999860540SLeo Yan opp00 { 18099860540SLeo Yan opp-hz = /bits/ 64 <208000000>; 18199860540SLeo Yan opp-microvolt = <1040000>; 18299860540SLeo Yan clock-latency-ns = <500000>; 18399860540SLeo Yan }; 18499860540SLeo Yan opp01 { 18599860540SLeo Yan opp-hz = /bits/ 64 <432000000>; 18699860540SLeo Yan opp-microvolt = <1040000>; 18799860540SLeo Yan clock-latency-ns = <500000>; 18899860540SLeo Yan }; 18999860540SLeo Yan opp02 { 19099860540SLeo Yan opp-hz = /bits/ 64 <729000000>; 19199860540SLeo Yan opp-microvolt = <1090000>; 19299860540SLeo Yan clock-latency-ns = <500000>; 19399860540SLeo Yan }; 19499860540SLeo Yan opp03 { 19599860540SLeo Yan opp-hz = /bits/ 64 <960000000>; 19699860540SLeo Yan opp-microvolt = <1180000>; 19799860540SLeo Yan clock-latency-ns = <500000>; 19899860540SLeo Yan }; 19999860540SLeo Yan opp04 { 20099860540SLeo Yan opp-hz = /bits/ 64 <1200000000>; 20199860540SLeo Yan opp-microvolt = <1330000>; 20299860540SLeo Yan clock-latency-ns = <500000>; 20399860540SLeo Yan }; 20499860540SLeo Yan }; 20599860540SLeo Yan 20686e8f528SBintian Wang gic: interrupt-controller@f6801000 { 20786e8f528SBintian Wang compatible = "arm,gic-400"; 20886e8f528SBintian Wang reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 20986e8f528SBintian Wang <0x0 0xf6802000 0 0x2000>, /* GICC */ 21086e8f528SBintian Wang <0x0 0xf6804000 0 0x2000>, /* GICH */ 21186e8f528SBintian Wang <0x0 0xf6806000 0 0x2000>; /* GICV */ 21286e8f528SBintian Wang #address-cells = <0>; 21386e8f528SBintian Wang #interrupt-cells = <3>; 21486e8f528SBintian Wang interrupt-controller; 21586e8f528SBintian Wang interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 21686e8f528SBintian Wang }; 21786e8f528SBintian Wang 21886e8f528SBintian Wang timer { 21986e8f528SBintian Wang compatible = "arm,armv8-timer"; 22086e8f528SBintian Wang interrupt-parent = <&gic>; 22186e8f528SBintian Wang interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 22286e8f528SBintian Wang <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 22386e8f528SBintian Wang <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 22486e8f528SBintian Wang <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 22586e8f528SBintian Wang }; 22686e8f528SBintian Wang 22786e8f528SBintian Wang soc { 22886e8f528SBintian Wang compatible = "simple-bus"; 22986e8f528SBintian Wang #address-cells = <2>; 23086e8f528SBintian Wang #size-cells = <2>; 23186e8f528SBintian Wang ranges; 23286e8f528SBintian Wang 23399860540SLeo Yan sram: sram@fff80000 { 23499860540SLeo Yan compatible = "hisilicon,hi6220-sramctrl", "syscon"; 23599860540SLeo Yan reg = <0x0 0xfff80000 0x0 0x12000>; 23699860540SLeo Yan }; 23799860540SLeo Yan 23886e8f528SBintian Wang ao_ctrl: ao_ctrl@f7800000 { 23986e8f528SBintian Wang compatible = "hisilicon,hi6220-aoctrl", "syscon"; 24086e8f528SBintian Wang reg = <0x0 0xf7800000 0x0 0x2000>; 24186e8f528SBintian Wang #clock-cells = <1>; 24286e8f528SBintian Wang }; 24386e8f528SBintian Wang 24486e8f528SBintian Wang sys_ctrl: sys_ctrl@f7030000 { 24586e8f528SBintian Wang compatible = "hisilicon,hi6220-sysctrl", "syscon"; 24686e8f528SBintian Wang reg = <0x0 0xf7030000 0x0 0x2000>; 24786e8f528SBintian Wang #clock-cells = <1>; 2483e14cd4cSChen Feng #reset-cells = <1>; 24986e8f528SBintian Wang }; 25086e8f528SBintian Wang 25186e8f528SBintian Wang media_ctrl: media_ctrl@f4410000 { 25286e8f528SBintian Wang compatible = "hisilicon,hi6220-mediactrl", "syscon"; 25386e8f528SBintian Wang reg = <0x0 0xf4410000 0x0 0x1000>; 25486e8f528SBintian Wang #clock-cells = <1>; 25586e8f528SBintian Wang }; 25686e8f528SBintian Wang 25786e8f528SBintian Wang pm_ctrl: pm_ctrl@f7032000 { 25886e8f528SBintian Wang compatible = "hisilicon,hi6220-pmctrl", "syscon"; 25986e8f528SBintian Wang reg = <0x0 0xf7032000 0x0 0x1000>; 26086e8f528SBintian Wang #clock-cells = <1>; 26186e8f528SBintian Wang }; 26286e8f528SBintian Wang 26399860540SLeo Yan stub_clock: stub_clock { 26499860540SLeo Yan compatible = "hisilicon,hi6220-stub-clk"; 26599860540SLeo Yan hisilicon,hi6220-clk-sram = <&sram>; 26699860540SLeo Yan #clock-cells = <1>; 26799860540SLeo Yan mbox-names = "mbox-tx"; 26899860540SLeo Yan mboxes = <&mailbox 1 0 11>; 26999860540SLeo Yan }; 27099860540SLeo Yan 27186e8f528SBintian Wang uart0: uart@f8015000 { /* console */ 27286e8f528SBintian Wang compatible = "arm,pl011", "arm,primecell"; 27386e8f528SBintian Wang reg = <0x0 0xf8015000 0x0 0x1000>; 27486e8f528SBintian Wang interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 275a362ec8fSTyler Baker clocks = <&ao_ctrl HI6220_UART0_PCLK>, 276a362ec8fSTyler Baker <&ao_ctrl HI6220_UART0_PCLK>; 27786e8f528SBintian Wang clock-names = "uartclk", "apb_pclk"; 27886e8f528SBintian Wang }; 279a362ec8fSTyler Baker 280a362ec8fSTyler Baker uart1: uart@f7111000 { 281a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 282a362ec8fSTyler Baker reg = <0x0 0xf7111000 0x0 0x1000>; 283a362ec8fSTyler Baker interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 284a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART1_PCLK>, 285a362ec8fSTyler Baker <&sys_ctrl HI6220_UART1_PCLK>; 286a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 287c2aad932SGuodong Xu pinctrl-names = "default"; 288c2aad932SGuodong Xu pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; 289a362ec8fSTyler Baker status = "disabled"; 290a362ec8fSTyler Baker }; 291a362ec8fSTyler Baker 292a362ec8fSTyler Baker uart2: uart@f7112000 { 293a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 294a362ec8fSTyler Baker reg = <0x0 0xf7112000 0x0 0x1000>; 295a362ec8fSTyler Baker interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 296a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART2_PCLK>, 297a362ec8fSTyler Baker <&sys_ctrl HI6220_UART2_PCLK>; 298a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 299c2aad932SGuodong Xu pinctrl-names = "default"; 300c2aad932SGuodong Xu pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 301a362ec8fSTyler Baker status = "disabled"; 302a362ec8fSTyler Baker }; 303a362ec8fSTyler Baker 304a362ec8fSTyler Baker uart3: uart@f7113000 { 305a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 306a362ec8fSTyler Baker reg = <0x0 0xf7113000 0x0 0x1000>; 307a362ec8fSTyler Baker interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 308a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART3_PCLK>, 309a362ec8fSTyler Baker <&sys_ctrl HI6220_UART3_PCLK>; 310a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 311c2aad932SGuodong Xu pinctrl-names = "default"; 312c2aad932SGuodong Xu pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 313c2aad932SGuodong Xu status = "disabled"; 314a362ec8fSTyler Baker }; 315a362ec8fSTyler Baker 316a362ec8fSTyler Baker uart4: uart@f7114000 { 317a362ec8fSTyler Baker compatible = "arm,pl011", "arm,primecell"; 318a362ec8fSTyler Baker reg = <0x0 0xf7114000 0x0 0x1000>; 319a362ec8fSTyler Baker interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 320a362ec8fSTyler Baker clocks = <&sys_ctrl HI6220_UART4_PCLK>, 321a362ec8fSTyler Baker <&sys_ctrl HI6220_UART4_PCLK>; 322a362ec8fSTyler Baker clock-names = "uartclk", "apb_pclk"; 323c2aad932SGuodong Xu pinctrl-names = "default"; 324c2aad932SGuodong Xu pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 325a362ec8fSTyler Baker status = "disabled"; 326a362ec8fSTyler Baker }; 3279e927031SLeo Yan 3289e927031SLeo Yan dual_timer0: timer@f8008000 { 3299e927031SLeo Yan compatible = "arm,sp804", "arm,primecell"; 3309e927031SLeo Yan reg = <0x0 0xf8008000 0x0 0x1000>; 3319e927031SLeo Yan interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 3329e927031SLeo Yan <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 3339e927031SLeo Yan clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, 3349e927031SLeo Yan <&ao_ctrl HI6220_TIMER0_PCLK>, 3359e927031SLeo Yan <&ao_ctrl HI6220_TIMER0_PCLK>; 3369e927031SLeo Yan clock-names = "timer1", "timer2", "apb_pclk"; 3379e927031SLeo Yan }; 338f2bfacf9SZhong Kaihua 339379e9bf5SZhong Kaihua pmx0: pinmux@f7010000 { 340379e9bf5SZhong Kaihua compatible = "pinctrl-single"; 341379e9bf5SZhong Kaihua reg = <0x0 0xf7010000 0x0 0x27c>; 342379e9bf5SZhong Kaihua #address-cells = <1>; 343379e9bf5SZhong Kaihua #size-cells = <1>; 344379e9bf5SZhong Kaihua #gpio-range-cells = <3>; 345379e9bf5SZhong Kaihua pinctrl-single,register-width = <32>; 346379e9bf5SZhong Kaihua pinctrl-single,function-mask = <7>; 347379e9bf5SZhong Kaihua pinctrl-single,gpio-range = < 348379e9bf5SZhong Kaihua &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 349379e9bf5SZhong Kaihua &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 350379e9bf5SZhong Kaihua &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 351379e9bf5SZhong Kaihua &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 352379e9bf5SZhong Kaihua &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 353379e9bf5SZhong Kaihua &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 354379e9bf5SZhong Kaihua &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 355379e9bf5SZhong Kaihua &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 356379e9bf5SZhong Kaihua &range 0 1 MUX_M1 /* gpio 10: [0] */ 357379e9bf5SZhong Kaihua &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 358379e9bf5SZhong Kaihua &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 359379e9bf5SZhong Kaihua &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 360379e9bf5SZhong Kaihua &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 361379e9bf5SZhong Kaihua &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 362379e9bf5SZhong Kaihua &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 363379e9bf5SZhong Kaihua &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 364379e9bf5SZhong Kaihua &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 365379e9bf5SZhong Kaihua &range 122 1 MUX_M1 /* gpio 15: [6] */ 366379e9bf5SZhong Kaihua &range 126 1 MUX_M1 /* gpio 15: [7] */ 367379e9bf5SZhong Kaihua &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 368379e9bf5SZhong Kaihua &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 369379e9bf5SZhong Kaihua &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 370379e9bf5SZhong Kaihua &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 371379e9bf5SZhong Kaihua >; 372379e9bf5SZhong Kaihua range: gpio-range { 373379e9bf5SZhong Kaihua #pinctrl-single,gpio-range-cells = <3>; 374379e9bf5SZhong Kaihua }; 375379e9bf5SZhong Kaihua }; 376379e9bf5SZhong Kaihua 377379e9bf5SZhong Kaihua pmx1: pinmux@f7010800 { 378379e9bf5SZhong Kaihua compatible = "pinconf-single"; 379379e9bf5SZhong Kaihua reg = <0x0 0xf7010800 0x0 0x28c>; 380379e9bf5SZhong Kaihua #address-cells = <1>; 381379e9bf5SZhong Kaihua #size-cells = <1>; 382379e9bf5SZhong Kaihua pinctrl-single,register-width = <32>; 383379e9bf5SZhong Kaihua }; 384379e9bf5SZhong Kaihua 385379e9bf5SZhong Kaihua pmx2: pinmux@f8001800 { 386379e9bf5SZhong Kaihua compatible = "pinconf-single"; 387379e9bf5SZhong Kaihua reg = <0x0 0xf8001800 0x0 0x78>; 388379e9bf5SZhong Kaihua #address-cells = <1>; 389379e9bf5SZhong Kaihua #size-cells = <1>; 390379e9bf5SZhong Kaihua pinctrl-single,register-width = <32>; 391379e9bf5SZhong Kaihua }; 392379e9bf5SZhong Kaihua 393f2bfacf9SZhong Kaihua gpio0: gpio@f8011000 { 394f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 395f2bfacf9SZhong Kaihua reg = <0x0 0xf8011000 0x0 0x1000>; 396f2bfacf9SZhong Kaihua interrupts = <0 52 0x4>; 397f2bfacf9SZhong Kaihua gpio-controller; 398f2bfacf9SZhong Kaihua #gpio-cells = <2>; 399f2bfacf9SZhong Kaihua interrupt-controller; 400f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 401f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 402f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 403f2bfacf9SZhong Kaihua }; 404f2bfacf9SZhong Kaihua 405f2bfacf9SZhong Kaihua gpio1: gpio@f8012000 { 406f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 407f2bfacf9SZhong Kaihua reg = <0x0 0xf8012000 0x0 0x1000>; 408f2bfacf9SZhong Kaihua interrupts = <0 53 0x4>; 409f2bfacf9SZhong Kaihua gpio-controller; 410f2bfacf9SZhong Kaihua #gpio-cells = <2>; 411f2bfacf9SZhong Kaihua interrupt-controller; 412f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 413f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 414f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 415f2bfacf9SZhong Kaihua }; 416f2bfacf9SZhong Kaihua 417f2bfacf9SZhong Kaihua gpio2: gpio@f8013000 { 418f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 419f2bfacf9SZhong Kaihua reg = <0x0 0xf8013000 0x0 0x1000>; 420f2bfacf9SZhong Kaihua interrupts = <0 54 0x4>; 421f2bfacf9SZhong Kaihua gpio-controller; 422f2bfacf9SZhong Kaihua #gpio-cells = <2>; 423f2bfacf9SZhong Kaihua interrupt-controller; 424f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 425f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 426f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 427f2bfacf9SZhong Kaihua }; 428f2bfacf9SZhong Kaihua 429f2bfacf9SZhong Kaihua gpio3: gpio@f8014000 { 430f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 431f2bfacf9SZhong Kaihua reg = <0x0 0xf8014000 0x0 0x1000>; 432f2bfacf9SZhong Kaihua interrupts = <0 55 0x4>; 433f2bfacf9SZhong Kaihua gpio-controller; 434f2bfacf9SZhong Kaihua #gpio-cells = <2>; 435379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 80 8>; 436f2bfacf9SZhong Kaihua interrupt-controller; 437f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 438f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 439f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 440f2bfacf9SZhong Kaihua }; 441f2bfacf9SZhong Kaihua 442f2bfacf9SZhong Kaihua gpio4: gpio@f7020000 { 443f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 444f2bfacf9SZhong Kaihua reg = <0x0 0xf7020000 0x0 0x1000>; 445f2bfacf9SZhong Kaihua interrupts = <0 56 0x4>; 446f2bfacf9SZhong Kaihua gpio-controller; 447f2bfacf9SZhong Kaihua #gpio-cells = <2>; 448379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 88 8>; 449f2bfacf9SZhong Kaihua interrupt-controller; 450f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 451f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 452f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 453f2bfacf9SZhong Kaihua }; 454f2bfacf9SZhong Kaihua 455f2bfacf9SZhong Kaihua gpio5: gpio@f7021000 { 456f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 457f2bfacf9SZhong Kaihua reg = <0x0 0xf7021000 0x0 0x1000>; 458f2bfacf9SZhong Kaihua interrupts = <0 57 0x4>; 459f2bfacf9SZhong Kaihua gpio-controller; 460f2bfacf9SZhong Kaihua #gpio-cells = <2>; 461379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 96 8>; 462f2bfacf9SZhong Kaihua interrupt-controller; 463f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 464f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 465f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 466f2bfacf9SZhong Kaihua }; 467f2bfacf9SZhong Kaihua 468f2bfacf9SZhong Kaihua gpio6: gpio@f7022000 { 469f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 470f2bfacf9SZhong Kaihua reg = <0x0 0xf7022000 0x0 0x1000>; 471f2bfacf9SZhong Kaihua interrupts = <0 58 0x4>; 472f2bfacf9SZhong Kaihua gpio-controller; 473f2bfacf9SZhong Kaihua #gpio-cells = <2>; 474379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 104 8>; 475f2bfacf9SZhong Kaihua interrupt-controller; 476f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 477f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 478f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 479f2bfacf9SZhong Kaihua }; 480f2bfacf9SZhong Kaihua 481f2bfacf9SZhong Kaihua gpio7: gpio@f7023000 { 482f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 483f2bfacf9SZhong Kaihua reg = <0x0 0xf7023000 0x0 0x1000>; 484f2bfacf9SZhong Kaihua interrupts = <0 59 0x4>; 485f2bfacf9SZhong Kaihua gpio-controller; 486f2bfacf9SZhong Kaihua #gpio-cells = <2>; 487379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 112 8>; 488f2bfacf9SZhong Kaihua interrupt-controller; 489f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 490f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 491f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 492f2bfacf9SZhong Kaihua }; 493f2bfacf9SZhong Kaihua 494f2bfacf9SZhong Kaihua gpio8: gpio@f7024000 { 495f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 496f2bfacf9SZhong Kaihua reg = <0x0 0xf7024000 0x0 0x1000>; 497f2bfacf9SZhong Kaihua interrupts = <0 60 0x4>; 498f2bfacf9SZhong Kaihua gpio-controller; 499f2bfacf9SZhong Kaihua #gpio-cells = <2>; 500379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 501f2bfacf9SZhong Kaihua interrupt-controller; 502f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 503f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 504f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 505f2bfacf9SZhong Kaihua }; 506f2bfacf9SZhong Kaihua 507f2bfacf9SZhong Kaihua gpio9: gpio@f7025000 { 508f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 509f2bfacf9SZhong Kaihua reg = <0x0 0xf7025000 0x0 0x1000>; 510f2bfacf9SZhong Kaihua interrupts = <0 61 0x4>; 511f2bfacf9SZhong Kaihua gpio-controller; 512f2bfacf9SZhong Kaihua #gpio-cells = <2>; 513379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 8 8>; 514f2bfacf9SZhong Kaihua interrupt-controller; 515f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 516f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 517f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 518f2bfacf9SZhong Kaihua }; 519f2bfacf9SZhong Kaihua 520f2bfacf9SZhong Kaihua gpio10: gpio@f7026000 { 521f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 522f2bfacf9SZhong Kaihua reg = <0x0 0xf7026000 0x0 0x1000>; 523f2bfacf9SZhong Kaihua interrupts = <0 62 0x4>; 524f2bfacf9SZhong Kaihua gpio-controller; 525f2bfacf9SZhong Kaihua #gpio-cells = <2>; 526379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 527f2bfacf9SZhong Kaihua interrupt-controller; 528f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 529f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 530f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 531f2bfacf9SZhong Kaihua }; 532f2bfacf9SZhong Kaihua 533f2bfacf9SZhong Kaihua gpio11: gpio@f7027000 { 534f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 535f2bfacf9SZhong Kaihua reg = <0x0 0xf7027000 0x0 0x1000>; 536f2bfacf9SZhong Kaihua interrupts = <0 63 0x4>; 537f2bfacf9SZhong Kaihua gpio-controller; 538f2bfacf9SZhong Kaihua #gpio-cells = <2>; 539379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 540f2bfacf9SZhong Kaihua interrupt-controller; 541f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 542f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 543f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 544f2bfacf9SZhong Kaihua }; 545f2bfacf9SZhong Kaihua 546f2bfacf9SZhong Kaihua gpio12: gpio@f7028000 { 547f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 548f2bfacf9SZhong Kaihua reg = <0x0 0xf7028000 0x0 0x1000>; 549f2bfacf9SZhong Kaihua interrupts = <0 64 0x4>; 550f2bfacf9SZhong Kaihua gpio-controller; 551f2bfacf9SZhong Kaihua #gpio-cells = <2>; 552379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 553f2bfacf9SZhong Kaihua interrupt-controller; 554f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 555f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 556f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 557f2bfacf9SZhong Kaihua }; 558f2bfacf9SZhong Kaihua 559f2bfacf9SZhong Kaihua gpio13: gpio@f7029000 { 560f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 561f2bfacf9SZhong Kaihua reg = <0x0 0xf7029000 0x0 0x1000>; 562f2bfacf9SZhong Kaihua interrupts = <0 65 0x4>; 563f2bfacf9SZhong Kaihua gpio-controller; 564379e9bf5SZhong Kaihua #gpio-cells = <2>; 565379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 48 8>; 566f2bfacf9SZhong Kaihua interrupt-controller; 567f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 568f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 569f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 570f2bfacf9SZhong Kaihua }; 571f2bfacf9SZhong Kaihua 572f2bfacf9SZhong Kaihua gpio14: gpio@f702a000 { 573f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 574f2bfacf9SZhong Kaihua reg = <0x0 0xf702a000 0x0 0x1000>; 575f2bfacf9SZhong Kaihua interrupts = <0 66 0x4>; 576f2bfacf9SZhong Kaihua gpio-controller; 577f2bfacf9SZhong Kaihua #gpio-cells = <2>; 578379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 56 8>; 579f2bfacf9SZhong Kaihua interrupt-controller; 580f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 581f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 582f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 583f2bfacf9SZhong Kaihua }; 584f2bfacf9SZhong Kaihua 585f2bfacf9SZhong Kaihua gpio15: gpio@f702b000 { 586f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 587f2bfacf9SZhong Kaihua reg = <0x0 0xf702b000 0x0 0x1000>; 588f2bfacf9SZhong Kaihua interrupts = <0 67 0x4>; 589f2bfacf9SZhong Kaihua gpio-controller; 590f2bfacf9SZhong Kaihua #gpio-cells = <2>; 591379e9bf5SZhong Kaihua gpio-ranges = < 592379e9bf5SZhong Kaihua &pmx0 0 74 6 593379e9bf5SZhong Kaihua &pmx0 6 122 1 594379e9bf5SZhong Kaihua &pmx0 7 126 1 595379e9bf5SZhong Kaihua >; 596f2bfacf9SZhong Kaihua interrupt-controller; 597f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 598f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 599f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 600f2bfacf9SZhong Kaihua }; 601f2bfacf9SZhong Kaihua 602f2bfacf9SZhong Kaihua gpio16: gpio@f702c000 { 603f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 604f2bfacf9SZhong Kaihua reg = <0x0 0xf702c000 0x0 0x1000>; 605f2bfacf9SZhong Kaihua interrupts = <0 68 0x4>; 606f2bfacf9SZhong Kaihua gpio-controller; 607f2bfacf9SZhong Kaihua #gpio-cells = <2>; 608379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 127 8>; 609f2bfacf9SZhong Kaihua interrupt-controller; 610f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 611f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 612f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 613f2bfacf9SZhong Kaihua }; 614f2bfacf9SZhong Kaihua 615f2bfacf9SZhong Kaihua gpio17: gpio@f702d000 { 616f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 617f2bfacf9SZhong Kaihua reg = <0x0 0xf702d000 0x0 0x1000>; 618f2bfacf9SZhong Kaihua interrupts = <0 69 0x4>; 619f2bfacf9SZhong Kaihua gpio-controller; 620f2bfacf9SZhong Kaihua #gpio-cells = <2>; 621379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 135 8>; 622f2bfacf9SZhong Kaihua interrupt-controller; 623f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 624f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 625f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 626f2bfacf9SZhong Kaihua }; 627f2bfacf9SZhong Kaihua 628f2bfacf9SZhong Kaihua gpio18: gpio@f702e000 { 629f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 630f2bfacf9SZhong Kaihua reg = <0x0 0xf702e000 0x0 0x1000>; 631f2bfacf9SZhong Kaihua interrupts = <0 70 0x4>; 632f2bfacf9SZhong Kaihua gpio-controller; 633f2bfacf9SZhong Kaihua #gpio-cells = <2>; 634379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 143 8>; 635f2bfacf9SZhong Kaihua interrupt-controller; 636f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 637f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 638f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 639f2bfacf9SZhong Kaihua }; 640f2bfacf9SZhong Kaihua 641f2bfacf9SZhong Kaihua gpio19: gpio@f702f000 { 642f2bfacf9SZhong Kaihua compatible = "arm,pl061", "arm,primecell"; 643f2bfacf9SZhong Kaihua reg = <0x0 0xf702f000 0x0 0x1000>; 644f2bfacf9SZhong Kaihua interrupts = <0 71 0x4>; 645f2bfacf9SZhong Kaihua gpio-controller; 646f2bfacf9SZhong Kaihua #gpio-cells = <2>; 647379e9bf5SZhong Kaihua gpio-ranges = <&pmx0 0 151 8>; 648f2bfacf9SZhong Kaihua interrupt-controller; 649f2bfacf9SZhong Kaihua #interrupt-cells = <2>; 650f2bfacf9SZhong Kaihua clocks = <&ao_ctrl 2>; 651f2bfacf9SZhong Kaihua clock-names = "apb_pclk"; 652f2bfacf9SZhong Kaihua }; 65360dac1b1SZhong Kaihua 65460dac1b1SZhong Kaihua spi0: spi@f7106000 { 65560dac1b1SZhong Kaihua compatible = "arm,pl022", "arm,primecell"; 65660dac1b1SZhong Kaihua reg = <0x0 0xf7106000 0x0 0x1000>; 65760dac1b1SZhong Kaihua interrupts = <0 50 4>; 65860dac1b1SZhong Kaihua bus-id = <0>; 65960dac1b1SZhong Kaihua enable-dma = <0>; 66060dac1b1SZhong Kaihua clocks = <&sys_ctrl HI6220_SPI_CLK>; 66160dac1b1SZhong Kaihua clock-names = "apb_pclk"; 66260dac1b1SZhong Kaihua pinctrl-names = "default"; 66360dac1b1SZhong Kaihua pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 66460dac1b1SZhong Kaihua num-cs = <1>; 66560dac1b1SZhong Kaihua cs-gpios = <&gpio6 2 0>; 66660dac1b1SZhong Kaihua status = "disabled"; 66760dac1b1SZhong Kaihua }; 6685ff3a4ddSXinwei Kong 6695ff3a4ddSXinwei Kong i2c0: i2c@f7100000 { 6705ff3a4ddSXinwei Kong compatible = "snps,designware-i2c"; 6715ff3a4ddSXinwei Kong reg = <0x0 0xf7100000 0x0 0x1000>; 6725ff3a4ddSXinwei Kong interrupts = <0 44 4>; 6735ff3a4ddSXinwei Kong clocks = <&sys_ctrl HI6220_I2C0_CLK>; 6745ff3a4ddSXinwei Kong i2c-sda-hold-time-ns = <300>; 6755ff3a4ddSXinwei Kong pinctrl-names = "default"; 6765ff3a4ddSXinwei Kong pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 6775ff3a4ddSXinwei Kong status = "disabled"; 6785ff3a4ddSXinwei Kong }; 6795ff3a4ddSXinwei Kong 6805ff3a4ddSXinwei Kong i2c1: i2c@f7101000 { 6815ff3a4ddSXinwei Kong compatible = "snps,designware-i2c"; 6825ff3a4ddSXinwei Kong reg = <0x0 0xf7101000 0x0 0x1000>; 6835ff3a4ddSXinwei Kong clocks = <&sys_ctrl HI6220_I2C1_CLK>; 6845ff3a4ddSXinwei Kong interrupts = <0 45 4>; 6855ff3a4ddSXinwei Kong i2c-sda-hold-time-ns = <300>; 6865ff3a4ddSXinwei Kong pinctrl-names = "default"; 6875ff3a4ddSXinwei Kong pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 6885ff3a4ddSXinwei Kong status = "disabled"; 6895ff3a4ddSXinwei Kong }; 6905ff3a4ddSXinwei Kong 6915ff3a4ddSXinwei Kong i2c2: i2c@f7102000 { 6925ff3a4ddSXinwei Kong compatible = "snps,designware-i2c"; 6935ff3a4ddSXinwei Kong reg = <0x0 0xf7102000 0x0 0x1000>; 6945ff3a4ddSXinwei Kong clocks = <&sys_ctrl HI6220_I2C2_CLK>; 6955ff3a4ddSXinwei Kong interrupts = <0 46 4>; 6965ff3a4ddSXinwei Kong i2c-sda-hold-time-ns = <300>; 6975ff3a4ddSXinwei Kong pinctrl-names = "default"; 6985ff3a4ddSXinwei Kong pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 6995ff3a4ddSXinwei Kong status = "disabled"; 7005ff3a4ddSXinwei Kong }; 701b4b31a7cSZhangfei Gao 702b4b31a7cSZhangfei Gao fixed_5v_hub: regulator@0 { 703b4b31a7cSZhangfei Gao compatible = "regulator-fixed"; 704b4b31a7cSZhangfei Gao regulator-name = "fixed_5v_hub"; 705b4b31a7cSZhangfei Gao regulator-min-microvolt = <5000000>; 706b4b31a7cSZhangfei Gao regulator-max-microvolt = <5000000>; 707b4b31a7cSZhangfei Gao regulator-boot-on; 708b4b31a7cSZhangfei Gao gpio = <&gpio0 7 0>; 709b4b31a7cSZhangfei Gao regulator-always-on; 710b4b31a7cSZhangfei Gao }; 711b4b31a7cSZhangfei Gao 712b4b31a7cSZhangfei Gao usb_phy: usbphy { 713b4b31a7cSZhangfei Gao compatible = "hisilicon,hi6220-usb-phy"; 714b4b31a7cSZhangfei Gao #phy-cells = <0>; 715b4b31a7cSZhangfei Gao phy-supply = <&fixed_5v_hub>; 716b4b31a7cSZhangfei Gao hisilicon,peripheral-syscon = <&sys_ctrl>; 717b4b31a7cSZhangfei Gao }; 718b4b31a7cSZhangfei Gao 719b4b31a7cSZhangfei Gao usb: usb@f72c0000 { 720b4b31a7cSZhangfei Gao compatible = "hisilicon,hi6220-usb"; 721b4b31a7cSZhangfei Gao reg = <0x0 0xf72c0000 0x0 0x40000>; 722b4b31a7cSZhangfei Gao phys = <&usb_phy>; 723b4b31a7cSZhangfei Gao phy-names = "usb2-phy"; 724b4b31a7cSZhangfei Gao clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 725b4b31a7cSZhangfei Gao clock-names = "otg"; 726b4b31a7cSZhangfei Gao dr_mode = "otg"; 727b4b31a7cSZhangfei Gao g-use-dma; 728b4b31a7cSZhangfei Gao g-rx-fifo-size = <512>; 729b4b31a7cSZhangfei Gao g-np-tx-fifo-size = <128>; 730b4b31a7cSZhangfei Gao g-tx-fifo-size = <128 128 128 128 128 128>; 731b4b31a7cSZhangfei Gao interrupts = <0 77 0x4>; 732b4b31a7cSZhangfei Gao }; 73386073570SLeo Yan 73486073570SLeo Yan mailbox: mailbox@f7510000 { 73586073570SLeo Yan compatible = "hisilicon,hi6220-mbox"; 73686073570SLeo Yan reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 73786073570SLeo Yan <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 73886073570SLeo Yan interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 73986073570SLeo Yan #mbox-cells = <3>; 74086073570SLeo Yan }; 741d6b259d4SXinwei Kong 742d6b259d4SXinwei Kong dwmmc_0: dwmmc0@f723d000 { 743d6b259d4SXinwei Kong compatible = "hisilicon,hi6220-dw-mshc"; 744d6b259d4SXinwei Kong num-slots = <0x1>; 745d6b259d4SXinwei Kong cap-mmc-highspeed; 746d6b259d4SXinwei Kong non-removable; 747d6b259d4SXinwei Kong reg = <0x0 0xf723d000 0x0 0x1000>; 748d6b259d4SXinwei Kong interrupts = <0x0 0x48 0x4>; 749d6b259d4SXinwei Kong clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; 750d6b259d4SXinwei Kong clock-names = "ciu", "biu"; 751d6b259d4SXinwei Kong bus-width = <0x8>; 752d6b259d4SXinwei Kong vmmc-supply = <&ldo19>; 753d6b259d4SXinwei Kong pinctrl-names = "default"; 754d6b259d4SXinwei Kong pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func 755d6b259d4SXinwei Kong &emmc_cfg_func &emmc_rst_cfg_func>; 756d6b259d4SXinwei Kong }; 757d6b259d4SXinwei Kong 758d6b259d4SXinwei Kong dwmmc_1: dwmmc1@f723e000 { 759d6b259d4SXinwei Kong compatible = "hisilicon,hi6220-dw-mshc"; 760d6b259d4SXinwei Kong num-slots = <0x1>; 761d6b259d4SXinwei Kong card-detect-delay = <200>; 762d6b259d4SXinwei Kong hisilicon,peripheral-syscon = <&ao_ctrl>; 763d6b259d4SXinwei Kong cap-sd-highspeed; 764d6b259d4SXinwei Kong reg = <0x0 0xf723e000 0x0 0x1000>; 765d6b259d4SXinwei Kong interrupts = <0x0 0x49 0x4>; 766d6b259d4SXinwei Kong #address-cells = <0x1>; 767d6b259d4SXinwei Kong #size-cells = <0x0>; 768d6b259d4SXinwei Kong clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; 769d6b259d4SXinwei Kong clock-names = "ciu", "biu"; 770d6b259d4SXinwei Kong vqmmc-supply = <&ldo7>; 771d6b259d4SXinwei Kong vmmc-supply = <&ldo10>; 772d6b259d4SXinwei Kong bus-width = <0x4>; 773d6b259d4SXinwei Kong disable-wp; 774d6b259d4SXinwei Kong cd-gpios = <&gpio1 0 1>; 775d6b259d4SXinwei Kong pinctrl-names = "default", "idle"; 776d6b259d4SXinwei Kong pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; 777d6b259d4SXinwei Kong pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; 778d6b259d4SXinwei Kong }; 779d6b259d4SXinwei Kong 780d6b259d4SXinwei Kong dwmmc_2: dwmmc2@f723f000 { 781d6b259d4SXinwei Kong compatible = "hisilicon,hi6220-dw-mshc"; 782d6b259d4SXinwei Kong num-slots = <0x1>; 783d6b259d4SXinwei Kong reg = <0x0 0xf723f000 0x0 0x1000>; 784d6b259d4SXinwei Kong interrupts = <0x0 0x4a 0x4>; 785d6b259d4SXinwei Kong clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; 786d6b259d4SXinwei Kong clock-names = "ciu", "biu"; 787d6b259d4SXinwei Kong bus-width = <0x4>; 788d6b259d4SXinwei Kong broken-cd; 789d6b259d4SXinwei Kong pinctrl-names = "default", "idle"; 790d6b259d4SXinwei Kong pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; 791d6b259d4SXinwei Kong pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; 792d6b259d4SXinwei Kong }; 7932158ab08SLeo Yan 7942158ab08SLeo Yan tsensor: tsensor@0,f7030700 { 7952158ab08SLeo Yan compatible = "hisilicon,tsensor"; 7962158ab08SLeo Yan reg = <0x0 0xf7030700 0x0 0x1000>; 7972158ab08SLeo Yan interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 7982158ab08SLeo Yan clocks = <&sys_ctrl 22>; 7992158ab08SLeo Yan clock-names = "thermal_clk"; 8002158ab08SLeo Yan #thermal-sensor-cells = <1>; 8012158ab08SLeo Yan }; 802cd0b69ecSLeo Yan 803cd0b69ecSLeo Yan thermal-zones { 804cd0b69ecSLeo Yan 805cd0b69ecSLeo Yan cls0: cls0 { 806cd0b69ecSLeo Yan polling-delay = <1000>; 807cd0b69ecSLeo Yan polling-delay-passive = <100>; 808cd0b69ecSLeo Yan sustainable-power = <3326>; 809cd0b69ecSLeo Yan 810cd0b69ecSLeo Yan /* sensor ID */ 811cd0b69ecSLeo Yan thermal-sensors = <&tsensor 2>; 812cd0b69ecSLeo Yan 813cd0b69ecSLeo Yan trips { 814cd0b69ecSLeo Yan threshold: trip-point@0 { 815cd0b69ecSLeo Yan temperature = <65000>; 816cd0b69ecSLeo Yan hysteresis = <0>; 817cd0b69ecSLeo Yan type = "passive"; 818cd0b69ecSLeo Yan }; 819cd0b69ecSLeo Yan 820cd0b69ecSLeo Yan target: trip-point@1 { 821cd0b69ecSLeo Yan temperature = <75000>; 822cd0b69ecSLeo Yan hysteresis = <0>; 823cd0b69ecSLeo Yan type = "passive"; 824cd0b69ecSLeo Yan }; 825cd0b69ecSLeo Yan }; 826cd0b69ecSLeo Yan 827cd0b69ecSLeo Yan cooling-maps { 828cd0b69ecSLeo Yan map0 { 829cd0b69ecSLeo Yan trip = <&target>; 830cd0b69ecSLeo Yan cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 831cd0b69ecSLeo Yan }; 832cd0b69ecSLeo Yan }; 833cd0b69ecSLeo Yan }; 834cd0b69ecSLeo Yan }; 83586e8f528SBintian Wang }; 83686e8f528SBintian Wang}; 837