1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DTS File for HiSilicon Hi3798cv200 SoC.
4 *
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
6 */
7
8#include <dt-bindings/clock/histb-clock.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/reset/ti-syscon.h>
13
14/ {
15	compatible = "hisilicon,hi3798cv200";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	psci {
21		compatible = "arm,psci-0.2";
22		method = "smc";
23	};
24
25	cpus {
26		#address-cells = <2>;
27		#size-cells = <0>;
28
29		cpu@0 {
30			compatible = "arm,cortex-a53";
31			device_type = "cpu";
32			reg = <0x0 0x0>;
33			enable-method = "psci";
34		};
35
36		cpu@1 {
37			compatible = "arm,cortex-a53";
38			device_type = "cpu";
39			reg = <0x0 0x1>;
40			enable-method = "psci";
41		};
42
43		cpu@2 {
44			compatible = "arm,cortex-a53";
45			device_type = "cpu";
46			reg = <0x0 0x2>;
47			enable-method = "psci";
48		};
49
50		cpu@3 {
51			compatible = "arm,cortex-a53";
52			device_type = "cpu";
53			reg = <0x0 0x3>;
54			enable-method = "psci";
55		};
56	};
57
58	gic: interrupt-controller@f1001000 {
59		compatible = "arm,gic-400";
60		reg = <0x0 0xf1001000 0x0 0x1000>,  /* GICD */
61		      <0x0 0xf1002000 0x0 0x100>;   /* GICC */
62		#address-cells = <0>;
63		#interrupt-cells = <3>;
64		interrupt-controller;
65	};
66
67	timer {
68		compatible = "arm,armv8-timer";
69		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
70			      IRQ_TYPE_LEVEL_LOW)>,
71			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
72			      IRQ_TYPE_LEVEL_LOW)>,
73			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
74			      IRQ_TYPE_LEVEL_LOW)>,
75			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
76			      IRQ_TYPE_LEVEL_LOW)>;
77	};
78
79	soc: soc@f0000000 {
80		compatible = "simple-bus";
81		#address-cells = <1>;
82		#size-cells = <1>;
83		ranges = <0x0 0x0 0xf0000000 0x10000000>;
84
85		crg: clock-reset-controller@8a22000 {
86			compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
87			reg = <0x8a22000 0x1000>;
88			#clock-cells = <1>;
89			#reset-cells = <2>;
90
91			gmacphyrst: reset-controller {
92				compatible = "ti,syscon-reset";
93				#reset-cells = <1>;
94				ti,reset-bits =
95					<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
96					 DEASSERT_SET|STATUS_NONE)>,
97					<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
98					 DEASSERT_SET|STATUS_NONE)>;
99			};
100		};
101
102		sysctrl: system-controller@8000000 {
103			compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
104			reg = <0x8000000 0x1000>;
105			#clock-cells = <1>;
106			#reset-cells = <2>;
107		};
108
109		perictrl: peripheral-controller@8a20000 {
110			compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
111				     "simple-mfd";
112			reg = <0x8a20000 0x1000>;
113			#address-cells = <1>;
114			#size-cells = <1>;
115			ranges = <0x0 0x8a20000 0x1000>;
116
117			usb2_phy1: usb2-phy@120 {
118				compatible = "hisilicon,hi3798cv200-usb2-phy";
119				reg = <0x120 0x4>;
120				clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
121				resets = <&crg 0xbc 4>;
122				#address-cells = <1>;
123				#size-cells = <0>;
124
125				usb2_phy1_port0: phy@0 {
126					reg = <0>;
127					#phy-cells = <0>;
128					resets = <&crg 0xbc 8>;
129				};
130
131				usb2_phy1_port1: phy@1 {
132					reg = <1>;
133					#phy-cells = <0>;
134					resets = <&crg 0xbc 9>;
135				};
136			};
137
138			usb2_phy2: usb2-phy@124 {
139				compatible = "hisilicon,hi3798cv200-usb2-phy";
140				reg = <0x124 0x4>;
141				clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
142				resets = <&crg 0xbc 6>;
143				#address-cells = <1>;
144				#size-cells = <0>;
145
146				usb2_phy2_port0: phy@0 {
147					reg = <0>;
148					#phy-cells = <0>;
149					resets = <&crg 0xbc 10>;
150				};
151			};
152
153			combphy0: phy@850 {
154				compatible = "hisilicon,hi3798cv200-combphy";
155				reg = <0x850 0x8>;
156				#phy-cells = <1>;
157				clocks = <&crg HISTB_COMBPHY0_CLK>;
158				resets = <&crg 0x188 4>;
159				assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
160				assigned-clock-rates = <100000000>;
161				hisilicon,fixed-mode = <PHY_TYPE_USB3>;
162			};
163
164			combphy1: phy@858 {
165				compatible = "hisilicon,hi3798cv200-combphy";
166				reg = <0x858 0x8>;
167				#phy-cells = <1>;
168				clocks = <&crg HISTB_COMBPHY1_CLK>;
169				resets = <&crg 0x188 12>;
170				assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
171				assigned-clock-rates = <100000000>;
172				hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
173			};
174		};
175
176		pmx0: pinconf@8a21000 {
177			compatible = "pinconf-single";
178			reg = <0x8a21000 0x180>;
179			pinctrl-single,register-width = <32>;
180			pinctrl-single,function-mask = <7>;
181			pinctrl-single,gpio-range = <
182				&range 0  8 2  /* GPIO 0 */
183				&range 8  1 0  /* GPIO 1 */
184				&range 9  4 2
185				&range 13 1 0
186				&range 14 1 1
187				&range 15 1 0
188				&range 16 5 0  /* GPIO 2 */
189				&range 21 3 1
190				&range 24 4 1  /* GPIO 3 */
191				&range 28 2 2
192				&range 86 1 1
193				&range 87 1 0
194				&range 30 4 2  /* GPIO 4 */
195				&range 34 3 0
196				&range 37 1 2
197				&range 38 3 2  /* GPIO 6 */
198				&range 41 5 0
199				&range 46 8 1  /* GPIO 7 */
200				&range 54 8 1  /* GPIO 8 */
201				&range 64 7 1  /* GPIO 9 */
202				&range 71 1 0
203				&range 72 6 1  /* GPIO 10 */
204				&range 78 1 0
205				&range 79 1 1
206				&range 80 6 1  /* GPIO 11 */
207				&range 70 2 1
208				&range 88 8 0  /* GPIO 12 */
209			>;
210
211			range: gpio-range {
212				#pinctrl-single,gpio-range-cells = <3>;
213			};
214		};
215
216		uart0: serial@8b00000 {
217			compatible = "arm,pl011", "arm,primecell";
218			reg = <0x8b00000 0x1000>;
219			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
220			clocks = <&sysctrl HISTB_UART0_CLK>;
221			clock-names = "apb_pclk";
222			status = "disabled";
223		};
224
225		uart2: serial@8b02000 {
226			compatible = "arm,pl011", "arm,primecell";
227			reg = <0x8b02000 0x1000>;
228			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
229			clocks = <&crg HISTB_UART2_CLK>;
230			clock-names = "apb_pclk";
231			status = "disabled";
232		};
233
234		i2c0: i2c@8b10000 {
235			compatible = "hisilicon,hix5hd2-i2c";
236			reg = <0x8b10000 0x1000>;
237			#address-cells = <1>;
238			#size-cells = <0>;
239			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
240			clock-frequency = <400000>;
241			clocks = <&crg HISTB_I2C0_CLK>;
242			status = "disabled";
243		};
244
245		i2c1: i2c@8b11000 {
246			compatible = "hisilicon,hix5hd2-i2c";
247			reg = <0x8b11000 0x1000>;
248			#address-cells = <1>;
249			#size-cells = <0>;
250			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
251			clock-frequency = <400000>;
252			clocks = <&crg HISTB_I2C1_CLK>;
253			status = "disabled";
254		};
255
256		i2c2: i2c@8b12000 {
257			compatible = "hisilicon,hix5hd2-i2c";
258			reg = <0x8b12000 0x1000>;
259			#address-cells = <1>;
260			#size-cells = <0>;
261			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
262			clock-frequency = <400000>;
263			clocks = <&crg HISTB_I2C2_CLK>;
264			status = "disabled";
265		};
266
267		i2c3: i2c@8b13000 {
268			compatible = "hisilicon,hix5hd2-i2c";
269			reg = <0x8b13000 0x1000>;
270			#address-cells = <1>;
271			#size-cells = <0>;
272			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
273			clock-frequency = <400000>;
274			clocks = <&crg HISTB_I2C3_CLK>;
275			status = "disabled";
276		};
277
278		i2c4: i2c@8b14000 {
279			compatible = "hisilicon,hix5hd2-i2c";
280			reg = <0x8b14000 0x1000>;
281			#address-cells = <1>;
282			#size-cells = <0>;
283			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
284			clock-frequency = <400000>;
285			clocks = <&crg HISTB_I2C4_CLK>;
286			status = "disabled";
287		};
288
289		spi0: spi@8b1a000 {
290			compatible = "arm,pl022", "arm,primecell";
291			reg = <0x8b1a000 0x1000>;
292			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
293			num-cs = <1>;
294			cs-gpios = <&gpio7 1 0>;
295			clocks = <&crg HISTB_SPI0_CLK>;
296			clock-names = "apb_pclk";
297			#address-cells = <1>;
298			#size-cells = <0>;
299			status = "disabled";
300		};
301
302		sd0: mmc@9820000 {
303			compatible = "snps,dw-mshc";
304			reg = <0x9820000 0x10000>;
305			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
306			clocks = <&crg HISTB_SDIO0_CIU_CLK>,
307				 <&crg HISTB_SDIO0_BIU_CLK>;
308			clock-names = "ciu", "biu";
309			resets = <&crg 0x9c 4>;
310			reset-names = "reset";
311			status = "disabled";
312		};
313
314		emmc: mmc@9830000 {
315			compatible = "hisilicon,hi3798cv200-dw-mshc";
316			reg = <0x9830000 0x10000>;
317			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
318			clocks = <&crg HISTB_MMC_CIU_CLK>,
319				 <&crg HISTB_MMC_BIU_CLK>,
320				 <&crg HISTB_MMC_SAMPLE_CLK>,
321				 <&crg HISTB_MMC_DRV_CLK>;
322			clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
323			resets = <&crg 0xa0 4>;
324			reset-names = "reset";
325			status = "disabled";
326		};
327
328		gpio0: gpio@8b20000 {
329			compatible = "arm,pl061", "arm,primecell";
330			reg = <0x8b20000 0x1000>;
331			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
332			gpio-controller;
333			#gpio-cells = <2>;
334			interrupt-controller;
335			#interrupt-cells = <2>;
336			gpio-ranges = <&pmx0 0 0 8>;
337			clocks = <&crg HISTB_APB_CLK>;
338			clock-names = "apb_pclk";
339			status = "disabled";
340		};
341
342		gpio1: gpio@8b21000 {
343			compatible = "arm,pl061", "arm,primecell";
344			reg = <0x8b21000 0x1000>;
345			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
346			gpio-controller;
347			#gpio-cells = <2>;
348			interrupt-controller;
349			#interrupt-cells = <2>;
350			gpio-ranges = <
351				&pmx0 0 8 1
352				&pmx0 1 9 4
353				&pmx0 5 13 1
354				&pmx0 6 14 1
355				&pmx0 7 15 1
356			>;
357			clocks = <&crg HISTB_APB_CLK>;
358			clock-names = "apb_pclk";
359			status = "disabled";
360		};
361
362		gpio2: gpio@8b22000 {
363			compatible = "arm,pl061", "arm,primecell";
364			reg = <0x8b22000 0x1000>;
365			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
366			gpio-controller;
367			#gpio-cells = <2>;
368			interrupt-controller;
369			#interrupt-cells = <2>;
370			gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
371			clocks = <&crg HISTB_APB_CLK>;
372			clock-names = "apb_pclk";
373			status = "disabled";
374		};
375
376		gpio3: gpio@8b23000 {
377			compatible = "arm,pl061", "arm,primecell";
378			reg = <0x8b23000 0x1000>;
379			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
380			gpio-controller;
381			#gpio-cells = <2>;
382			interrupt-controller;
383			#interrupt-cells = <2>;
384			gpio-ranges = <
385				&pmx0 0 24 4
386				&pmx0 4 28 2
387				&pmx0 6 86 1
388				&pmx0 7 87 1
389			>;
390			clocks = <&crg HISTB_APB_CLK>;
391			clock-names = "apb_pclk";
392			status = "disabled";
393		};
394
395		gpio4: gpio@8b24000 {
396			compatible = "arm,pl061", "arm,primecell";
397			reg = <0x8b24000 0x1000>;
398			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
399			gpio-controller;
400			#gpio-cells = <2>;
401			interrupt-controller;
402			#interrupt-cells = <2>;
403			gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
404			clocks = <&crg HISTB_APB_CLK>;
405			clock-names = "apb_pclk";
406			status = "disabled";
407		};
408
409		gpio5: gpio@8004000 {
410			compatible = "arm,pl061", "arm,primecell";
411			reg = <0x8004000 0x1000>;
412			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
413			gpio-controller;
414			#gpio-cells = <2>;
415			interrupt-controller;
416			#interrupt-cells = <2>;
417			clocks = <&crg HISTB_APB_CLK>;
418			clock-names = "apb_pclk";
419			status = "disabled";
420		};
421
422		gpio6: gpio@8b26000 {
423			compatible = "arm,pl061", "arm,primecell";
424			reg = <0x8b26000 0x1000>;
425			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
426			gpio-controller;
427			#gpio-cells = <2>;
428			interrupt-controller;
429			#interrupt-cells = <2>;
430			gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
431			clocks = <&crg HISTB_APB_CLK>;
432			clock-names = "apb_pclk";
433			status = "disabled";
434		};
435
436		gpio7: gpio@8b27000 {
437			compatible = "arm,pl061", "arm,primecell";
438			reg = <0x8b27000 0x1000>;
439			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
440			gpio-controller;
441			#gpio-cells = <2>;
442			interrupt-controller;
443			#interrupt-cells = <2>;
444			gpio-ranges = <&pmx0 0 46 8>;
445			clocks = <&crg HISTB_APB_CLK>;
446			clock-names = "apb_pclk";
447			status = "disabled";
448		};
449
450		gpio8: gpio@8b28000 {
451			compatible = "arm,pl061", "arm,primecell";
452			reg = <0x8b28000 0x1000>;
453			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
454			gpio-controller;
455			#gpio-cells = <2>;
456			interrupt-controller;
457			#interrupt-cells = <2>;
458			gpio-ranges = <&pmx0 0 54 8>;
459			clocks = <&crg HISTB_APB_CLK>;
460			clock-names = "apb_pclk";
461			status = "disabled";
462		};
463
464		gpio9: gpio@8b29000 {
465			compatible = "arm,pl061", "arm,primecell";
466			reg = <0x8b29000 0x1000>;
467			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
468			gpio-controller;
469			#gpio-cells = <2>;
470			interrupt-controller;
471			#interrupt-cells = <2>;
472			gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
473			clocks = <&crg HISTB_APB_CLK>;
474			clock-names = "apb_pclk";
475			status = "disabled";
476		};
477
478		gpio10: gpio@8b2a000 {
479			compatible = "arm,pl061", "arm,primecell";
480			reg = <0x8b2a000 0x1000>;
481			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
482			gpio-controller;
483			#gpio-cells = <2>;
484			interrupt-controller;
485			#interrupt-cells = <2>;
486			gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
487			clocks = <&crg HISTB_APB_CLK>;
488			clock-names = "apb_pclk";
489			status = "disabled";
490		};
491
492		gpio11: gpio@8b2b000 {
493			compatible = "arm,pl061", "arm,primecell";
494			reg = <0x8b2b000 0x1000>;
495			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
496			gpio-controller;
497			#gpio-cells = <2>;
498			interrupt-controller;
499			#interrupt-cells = <2>;
500			gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
501			clocks = <&crg HISTB_APB_CLK>;
502			clock-names = "apb_pclk";
503			status = "disabled";
504		};
505
506		gpio12: gpio@8b2c000 {
507			compatible = "arm,pl061", "arm,primecell";
508			reg = <0x8b2c000 0x1000>;
509			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
510			gpio-controller;
511			#gpio-cells = <2>;
512			interrupt-controller;
513			#interrupt-cells = <2>;
514			gpio-ranges = <&pmx0 0 88 8>;
515			clocks = <&crg HISTB_APB_CLK>;
516			clock-names = "apb_pclk";
517			status = "disabled";
518		};
519
520		gmac0: ethernet@9840000 {
521			compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
522			reg = <0x9840000 0x1000>,
523			      <0x984300c 0x4>;
524			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
525			clocks = <&crg HISTB_ETH0_MAC_CLK>,
526				 <&crg HISTB_ETH0_MACIF_CLK>;
527			clock-names = "mac_core", "mac_ifc";
528			resets = <&crg 0xcc 8>,
529				 <&crg 0xcc 10>,
530				 <&gmacphyrst 0>;
531			reset-names = "mac_core", "mac_ifc", "phy";
532			status = "disabled";
533		};
534
535		gmac1: ethernet@9841000 {
536			compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
537			reg = <0x9841000 0x1000>,
538			      <0x9843010 0x4>;
539			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
540			clocks = <&crg HISTB_ETH1_MAC_CLK>,
541				 <&crg HISTB_ETH1_MACIF_CLK>;
542			clock-names = "mac_core", "mac_ifc";
543			resets = <&crg 0xcc 9>,
544				 <&crg 0xcc 11>,
545				 <&gmacphyrst 1>;
546			reset-names = "mac_core", "mac_ifc", "phy";
547			status = "disabled";
548		};
549
550		ir: ir@8001000 {
551			compatible = "hisilicon,hix5hd2-ir";
552			reg = <0x8001000 0x1000>;
553			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
554			clocks = <&sysctrl HISTB_IR_CLK>;
555			status = "disabled";
556		};
557
558		pcie: pcie@9860000 {
559			compatible = "hisilicon,hi3798cv200-pcie";
560			reg = <0x9860000 0x1000>,
561			      <0x0 0x2000>,
562			      <0x2000000 0x01000000>;
563			reg-names = "control", "rc-dbi", "config";
564			#address-cells = <3>;
565			#size-cells = <2>;
566			device_type = "pci";
567			bus-range = <0x00 0xff>;
568			num-lanes = <1>;
569			ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
570				  0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
571			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
572			interrupt-names = "msi";
573			#interrupt-cells = <1>;
574			interrupt-map-mask = <0 0 0 0>;
575			interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
576			clocks = <&crg HISTB_PCIE_AUX_CLK>,
577				 <&crg HISTB_PCIE_PIPE_CLK>,
578				 <&crg HISTB_PCIE_SYS_CLK>,
579				 <&crg HISTB_PCIE_BUS_CLK>;
580			clock-names = "aux", "pipe", "sys", "bus";
581			resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
582			reset-names = "soft", "sys", "bus";
583			phys = <&combphy1 PHY_TYPE_PCIE>;
584			phy-names = "phy";
585			status = "disabled";
586		};
587
588		ohci: ohci@9880000 {
589			compatible = "generic-ohci";
590			reg = <0x9880000 0x10000>;
591			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
592			clocks = <&crg HISTB_USB2_BUS_CLK>,
593				 <&crg HISTB_USB2_12M_CLK>,
594				 <&crg HISTB_USB2_48M_CLK>;
595			clock-names = "bus", "clk12", "clk48";
596			resets = <&crg 0xb8 12>;
597			reset-names = "bus";
598			phys = <&usb2_phy1_port0>;
599			phy-names = "usb";
600			status = "disabled";
601		};
602
603		ehci: ehci@9890000 {
604			compatible = "generic-ehci";
605			reg = <0x9890000 0x10000>;
606			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
607			clocks = <&crg HISTB_USB2_BUS_CLK>,
608				 <&crg HISTB_USB2_PHY_CLK>,
609				 <&crg HISTB_USB2_UTMI_CLK>;
610			clock-names = "bus", "phy", "utmi";
611			resets = <&crg 0xb8 12>,
612				 <&crg 0xb8 16>,
613				 <&crg 0xb8 13>;
614			reset-names = "bus", "phy", "utmi";
615			phys = <&usb2_phy1_port0>;
616			phy-names = "usb";
617			status = "disabled";
618		};
619	};
620};
621