1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3660 SoC 4 * 5 * Copyright (C) 2016, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/hi3660-clock.h> 10 11/ { 12 compatible = "hisilicon,hi3660"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 psci { 18 compatible = "arm,psci-0.2"; 19 method = "smc"; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 core2 { 35 cpu = <&cpu2>; 36 }; 37 core3 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 device_type = "cpu"; 60 reg = <0x0 0x0>; 61 enable-method = "psci"; 62 next-level-cache = <&A53_L2>; 63 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 64 }; 65 66 cpu1: cpu@1 { 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 device_type = "cpu"; 69 reg = <0x0 0x1>; 70 enable-method = "psci"; 71 next-level-cache = <&A53_L2>; 72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 73 }; 74 75 cpu2: cpu@2 { 76 compatible = "arm,cortex-a53", "arm,armv8"; 77 device_type = "cpu"; 78 reg = <0x0 0x2>; 79 enable-method = "psci"; 80 next-level-cache = <&A53_L2>; 81 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 82 }; 83 84 cpu3: cpu@3 { 85 compatible = "arm,cortex-a53", "arm,armv8"; 86 device_type = "cpu"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&A53_L2>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 91 }; 92 93 cpu4: cpu@100 { 94 compatible = "arm,cortex-a73", "arm,armv8"; 95 device_type = "cpu"; 96 reg = <0x0 0x100>; 97 enable-method = "psci"; 98 next-level-cache = <&A73_L2>; 99 cpu-idle-states = < 100 &CPU_NAP 101 &CPU_SLEEP 102 &CLUSTER_SLEEP_1 103 >; 104 }; 105 106 cpu5: cpu@101 { 107 compatible = "arm,cortex-a73", "arm,armv8"; 108 device_type = "cpu"; 109 reg = <0x0 0x101>; 110 enable-method = "psci"; 111 next-level-cache = <&A73_L2>; 112 cpu-idle-states = < 113 &CPU_NAP 114 &CPU_SLEEP 115 &CLUSTER_SLEEP_1 116 >; 117 }; 118 119 cpu6: cpu@102 { 120 compatible = "arm,cortex-a73", "arm,armv8"; 121 device_type = "cpu"; 122 reg = <0x0 0x102>; 123 enable-method = "psci"; 124 next-level-cache = <&A73_L2>; 125 cpu-idle-states = < 126 &CPU_NAP 127 &CPU_SLEEP 128 &CLUSTER_SLEEP_1 129 >; 130 }; 131 132 cpu7: cpu@103 { 133 compatible = "arm,cortex-a73", "arm,armv8"; 134 device_type = "cpu"; 135 reg = <0x0 0x103>; 136 enable-method = "psci"; 137 next-level-cache = <&A73_L2>; 138 cpu-idle-states = < 139 &CPU_NAP 140 &CPU_SLEEP 141 &CLUSTER_SLEEP_1 142 >; 143 }; 144 145 idle-states { 146 entry-method = "psci"; 147 148 CPU_NAP: cpu-nap { 149 compatible = "arm,idle-state"; 150 arm,psci-suspend-param = <0x0000001>; 151 entry-latency-us = <7>; 152 exit-latency-us = <2>; 153 min-residency-us = <15>; 154 }; 155 156 CPU_SLEEP: cpu-sleep { 157 compatible = "arm,idle-state"; 158 local-timer-stop; 159 arm,psci-suspend-param = <0x0010000>; 160 entry-latency-us = <40>; 161 exit-latency-us = <70>; 162 min-residency-us = <3000>; 163 }; 164 165 CLUSTER_SLEEP_0: cluster-sleep-0 { 166 compatible = "arm,idle-state"; 167 local-timer-stop; 168 arm,psci-suspend-param = <0x1010000>; 169 entry-latency-us = <500>; 170 exit-latency-us = <5000>; 171 min-residency-us = <20000>; 172 }; 173 174 CLUSTER_SLEEP_1: cluster-sleep-1 { 175 compatible = "arm,idle-state"; 176 local-timer-stop; 177 arm,psci-suspend-param = <0x1010000>; 178 entry-latency-us = <1000>; 179 exit-latency-us = <5000>; 180 min-residency-us = <20000>; 181 }; 182 }; 183 184 A53_L2: l2-cache0 { 185 compatible = "cache"; 186 }; 187 188 A73_L2: l2-cache1 { 189 compatible = "cache"; 190 }; 191 }; 192 193 gic: interrupt-controller@e82b0000 { 194 compatible = "arm,gic-400"; 195 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 196 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 197 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 198 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 199 #address-cells = <0>; 200 #interrupt-cells = <3>; 201 interrupt-controller; 202 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 203 IRQ_TYPE_LEVEL_HIGH)>; 204 }; 205 206 a53-pmu { 207 compatible = "arm,cortex-a53-pmu"; 208 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-affinity = <&cpu0>, 213 <&cpu1>, 214 <&cpu2>, 215 <&cpu3>; 216 }; 217 218 a73-pmu { 219 compatible = "arm,cortex-a73-pmu"; 220 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 224 interrupt-affinity = <&cpu4>, 225 <&cpu5>, 226 <&cpu6>, 227 <&cpu7>; 228 }; 229 230 timer { 231 compatible = "arm,armv8-timer"; 232 interrupt-parent = <&gic>; 233 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 234 IRQ_TYPE_LEVEL_LOW)>, 235 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 236 IRQ_TYPE_LEVEL_LOW)>, 237 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 238 IRQ_TYPE_LEVEL_LOW)>, 239 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 240 IRQ_TYPE_LEVEL_LOW)>; 241 }; 242 243 soc { 244 compatible = "simple-bus"; 245 #address-cells = <2>; 246 #size-cells = <2>; 247 ranges; 248 249 crg_ctrl: crg_ctrl@fff35000 { 250 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 251 reg = <0x0 0xfff35000 0x0 0x1000>; 252 #clock-cells = <1>; 253 }; 254 255 crg_rst: crg_rst_controller { 256 compatible = "hisilicon,hi3660-reset"; 257 #reset-cells = <2>; 258 hisi,rst-syscon = <&crg_ctrl>; 259 }; 260 261 262 pctrl: pctrl@e8a09000 { 263 compatible = "hisilicon,hi3660-pctrl", "syscon"; 264 reg = <0x0 0xe8a09000 0x0 0x2000>; 265 #clock-cells = <1>; 266 }; 267 268 pmuctrl: crg_ctrl@fff34000 { 269 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 270 reg = <0x0 0xfff34000 0x0 0x1000>; 271 #clock-cells = <1>; 272 }; 273 274 sctrl: sctrl@fff0a000 { 275 compatible = "hisilicon,hi3660-sctrl", "syscon"; 276 reg = <0x0 0xfff0a000 0x0 0x1000>; 277 #clock-cells = <1>; 278 }; 279 280 iomcu: iomcu@ffd7e000 { 281 compatible = "hisilicon,hi3660-iomcu", "syscon"; 282 reg = <0x0 0xffd7e000 0x0 0x1000>; 283 #clock-cells = <1>; 284 285 }; 286 287 iomcu_rst: reset { 288 compatible = "hisilicon,hi3660-reset"; 289 hisi,rst-syscon = <&iomcu>; 290 #reset-cells = <2>; 291 }; 292 293 dual_timer0: timer@fff14000 { 294 compatible = "arm,sp804", "arm,primecell"; 295 reg = <0x0 0xfff14000 0x0 0x1000>; 296 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&crg_ctrl HI3660_OSC32K>, 299 <&crg_ctrl HI3660_OSC32K>, 300 <&crg_ctrl HI3660_OSC32K>; 301 clock-names = "timer1", "timer2", "apb_pclk"; 302 }; 303 304 i2c0: i2c@ffd71000 { 305 compatible = "snps,designware-i2c"; 306 reg = <0x0 0xffd71000 0x0 0x1000>; 307 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clock-frequency = <400000>; 311 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 312 resets = <&iomcu_rst 0x20 3>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 315 status = "disabled"; 316 }; 317 318 i2c1: i2c@ffd72000 { 319 compatible = "snps,designware-i2c"; 320 reg = <0x0 0xffd72000 0x0 0x1000>; 321 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 clock-frequency = <400000>; 325 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 326 resets = <&iomcu_rst 0x20 4>; 327 pinctrl-names = "default"; 328 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 329 status = "disabled"; 330 }; 331 332 i2c3: i2c@fdf0c000 { 333 compatible = "snps,designware-i2c"; 334 reg = <0x0 0xfdf0c000 0x0 0x1000>; 335 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 clock-frequency = <400000>; 339 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 340 resets = <&crg_rst 0x78 7>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 343 status = "disabled"; 344 }; 345 346 i2c7: i2c@fdf0b000 { 347 compatible = "snps,designware-i2c"; 348 reg = <0x0 0xfdf0b000 0x0 0x1000>; 349 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 clock-frequency = <400000>; 353 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 354 resets = <&crg_rst 0x60 14>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 357 status = "disabled"; 358 }; 359 360 uart0: serial@fdf02000 { 361 compatible = "arm,pl011", "arm,primecell"; 362 reg = <0x0 0xfdf02000 0x0 0x1000>; 363 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 365 <&crg_ctrl HI3660_PCLK>; 366 clock-names = "uartclk", "apb_pclk"; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 369 status = "disabled"; 370 }; 371 372 uart1: serial@fdf00000 { 373 compatible = "arm,pl011", "arm,primecell"; 374 reg = <0x0 0xfdf00000 0x0 0x1000>; 375 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 377 <&crg_ctrl HI3660_CLK_GATE_UART1>; 378 clock-names = "uartclk", "apb_pclk"; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 381 status = "disabled"; 382 }; 383 384 uart2: serial@fdf03000 { 385 compatible = "arm,pl011", "arm,primecell"; 386 reg = <0x0 0xfdf03000 0x0 0x1000>; 387 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 389 <&crg_ctrl HI3660_PCLK>; 390 clock-names = "uartclk", "apb_pclk"; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 393 status = "disabled"; 394 }; 395 396 uart3: serial@ffd74000 { 397 compatible = "arm,pl011", "arm,primecell"; 398 reg = <0x0 0xffd74000 0x0 0x1000>; 399 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 401 <&crg_ctrl HI3660_PCLK>; 402 clock-names = "uartclk", "apb_pclk"; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 405 status = "disabled"; 406 }; 407 408 uart4: serial@fdf01000 { 409 compatible = "arm,pl011", "arm,primecell"; 410 reg = <0x0 0xfdf01000 0x0 0x1000>; 411 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 413 <&crg_ctrl HI3660_CLK_GATE_UART4>; 414 clock-names = "uartclk", "apb_pclk"; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 417 status = "disabled"; 418 }; 419 420 uart5: serial@fdf05000 { 421 compatible = "arm,pl011", "arm,primecell"; 422 reg = <0x0 0xfdf05000 0x0 0x1000>; 423 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 425 <&crg_ctrl HI3660_CLK_GATE_UART5>; 426 clock-names = "uartclk", "apb_pclk"; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 429 status = "disabled"; 430 }; 431 432 uart6: serial@fff32000 { 433 compatible = "arm,pl011", "arm,primecell"; 434 reg = <0x0 0xfff32000 0x0 0x1000>; 435 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&crg_ctrl HI3660_CLK_UART6>, 437 <&crg_ctrl HI3660_PCLK>; 438 clock-names = "uartclk", "apb_pclk"; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 441 status = "disabled"; 442 }; 443 444 dma0: dma@fdf30000 { 445 compatible = "hisilicon,k3-dma-1.0"; 446 reg = <0x0 0xfdf30000 0x0 0x1000>; 447 #dma-cells = <1>; 448 dma-channels = <16>; 449 dma-requests = <32>; 450 dma-min-chan = <1>; 451 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 453 dma-no-cci; 454 dma-type = "hi3660_dma"; 455 }; 456 457 rtc0: rtc@fff04000 { 458 compatible = "arm,pl031", "arm,primecell"; 459 reg = <0x0 0Xfff04000 0x0 0x1000>; 460 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&crg_ctrl HI3660_PCLK>; 462 clock-names = "apb_pclk"; 463 }; 464 465 gpio0: gpio@e8a0b000 { 466 compatible = "arm,pl061", "arm,primecell"; 467 reg = <0 0xe8a0b000 0 0x1000>; 468 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 469 gpio-controller; 470 #gpio-cells = <2>; 471 gpio-ranges = <&pmx0 1 0 7>; 472 interrupt-controller; 473 #interrupt-cells = <2>; 474 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 475 clock-names = "apb_pclk"; 476 }; 477 478 gpio1: gpio@e8a0c000 { 479 compatible = "arm,pl061", "arm,primecell"; 480 reg = <0 0xe8a0c000 0 0x1000>; 481 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 482 gpio-controller; 483 #gpio-cells = <2>; 484 gpio-ranges = <&pmx0 1 7 7>; 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 488 clock-names = "apb_pclk"; 489 }; 490 491 gpio2: gpio@e8a0d000 { 492 compatible = "arm,pl061", "arm,primecell"; 493 reg = <0 0xe8a0d000 0 0x1000>; 494 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 gpio-ranges = <&pmx0 0 14 8>; 498 interrupt-controller; 499 #interrupt-cells = <2>; 500 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 501 clock-names = "apb_pclk"; 502 }; 503 504 gpio3: gpio@e8a0e000 { 505 compatible = "arm,pl061", "arm,primecell"; 506 reg = <0 0xe8a0e000 0 0x1000>; 507 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 gpio-ranges = <&pmx0 0 22 8>; 511 interrupt-controller; 512 #interrupt-cells = <2>; 513 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 514 clock-names = "apb_pclk"; 515 }; 516 517 gpio4: gpio@e8a0f000 { 518 compatible = "arm,pl061", "arm,primecell"; 519 reg = <0 0xe8a0f000 0 0x1000>; 520 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 521 gpio-controller; 522 #gpio-cells = <2>; 523 gpio-ranges = <&pmx0 0 30 8>; 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 527 clock-names = "apb_pclk"; 528 }; 529 530 gpio5: gpio@e8a10000 { 531 compatible = "arm,pl061", "arm,primecell"; 532 reg = <0 0xe8a10000 0 0x1000>; 533 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 534 gpio-controller; 535 #gpio-cells = <2>; 536 gpio-ranges = <&pmx0 0 38 8>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 540 clock-names = "apb_pclk"; 541 }; 542 543 gpio6: gpio@e8a11000 { 544 compatible = "arm,pl061", "arm,primecell"; 545 reg = <0 0xe8a11000 0 0x1000>; 546 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 547 gpio-controller; 548 #gpio-cells = <2>; 549 gpio-ranges = <&pmx0 0 46 8>; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 553 clock-names = "apb_pclk"; 554 }; 555 556 gpio7: gpio@e8a12000 { 557 compatible = "arm,pl061", "arm,primecell"; 558 reg = <0 0xe8a12000 0 0x1000>; 559 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 560 gpio-controller; 561 #gpio-cells = <2>; 562 gpio-ranges = <&pmx0 0 54 8>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 566 clock-names = "apb_pclk"; 567 }; 568 569 gpio8: gpio@e8a13000 { 570 compatible = "arm,pl061", "arm,primecell"; 571 reg = <0 0xe8a13000 0 0x1000>; 572 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 573 gpio-controller; 574 #gpio-cells = <2>; 575 gpio-ranges = <&pmx0 0 62 8>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 579 clock-names = "apb_pclk"; 580 }; 581 582 gpio9: gpio@e8a14000 { 583 compatible = "arm,pl061", "arm,primecell"; 584 reg = <0 0xe8a14000 0 0x1000>; 585 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 586 gpio-controller; 587 #gpio-cells = <2>; 588 gpio-ranges = <&pmx0 0 70 8>; 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 592 clock-names = "apb_pclk"; 593 }; 594 595 gpio10: gpio@e8a15000 { 596 compatible = "arm,pl061", "arm,primecell"; 597 reg = <0 0xe8a15000 0 0x1000>; 598 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 599 gpio-controller; 600 #gpio-cells = <2>; 601 gpio-ranges = <&pmx0 0 78 8>; 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 605 clock-names = "apb_pclk"; 606 }; 607 608 gpio11: gpio@e8a16000 { 609 compatible = "arm,pl061", "arm,primecell"; 610 reg = <0 0xe8a16000 0 0x1000>; 611 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 612 gpio-controller; 613 #gpio-cells = <2>; 614 gpio-ranges = <&pmx0 0 86 8>; 615 interrupt-controller; 616 #interrupt-cells = <2>; 617 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 618 clock-names = "apb_pclk"; 619 }; 620 621 gpio12: gpio@e8a17000 { 622 compatible = "arm,pl061", "arm,primecell"; 623 reg = <0 0xe8a17000 0 0x1000>; 624 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 625 gpio-controller; 626 #gpio-cells = <2>; 627 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 628 interrupt-controller; 629 #interrupt-cells = <2>; 630 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 631 clock-names = "apb_pclk"; 632 }; 633 634 gpio13: gpio@e8a18000 { 635 compatible = "arm,pl061", "arm,primecell"; 636 reg = <0 0xe8a18000 0 0x1000>; 637 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 638 gpio-controller; 639 #gpio-cells = <2>; 640 gpio-ranges = <&pmx0 0 102 8>; 641 interrupt-controller; 642 #interrupt-cells = <2>; 643 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 644 clock-names = "apb_pclk"; 645 }; 646 647 gpio14: gpio@e8a19000 { 648 compatible = "arm,pl061", "arm,primecell"; 649 reg = <0 0xe8a19000 0 0x1000>; 650 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 651 gpio-controller; 652 #gpio-cells = <2>; 653 gpio-ranges = <&pmx0 0 110 8>; 654 interrupt-controller; 655 #interrupt-cells = <2>; 656 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 657 clock-names = "apb_pclk"; 658 }; 659 660 gpio15: gpio@e8a1a000 { 661 compatible = "arm,pl061", "arm,primecell"; 662 reg = <0 0xe8a1a000 0 0x1000>; 663 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 664 gpio-controller; 665 #gpio-cells = <2>; 666 gpio-ranges = <&pmx0 0 118 6>; 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 670 clock-names = "apb_pclk"; 671 }; 672 673 gpio16: gpio@e8a1b000 { 674 compatible = "arm,pl061", "arm,primecell"; 675 reg = <0 0xe8a1b000 0 0x1000>; 676 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 677 gpio-controller; 678 #gpio-cells = <2>; 679 interrupt-controller; 680 #interrupt-cells = <2>; 681 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 682 clock-names = "apb_pclk"; 683 }; 684 685 gpio17: gpio@e8a1c000 { 686 compatible = "arm,pl061", "arm,primecell"; 687 reg = <0 0xe8a1c000 0 0x1000>; 688 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 689 gpio-controller; 690 #gpio-cells = <2>; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 694 clock-names = "apb_pclk"; 695 }; 696 697 gpio18: gpio@ff3b4000 { 698 compatible = "arm,pl061", "arm,primecell"; 699 reg = <0 0xff3b4000 0 0x1000>; 700 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 701 gpio-controller; 702 #gpio-cells = <2>; 703 gpio-ranges = <&pmx2 0 0 8>; 704 interrupt-controller; 705 #interrupt-cells = <2>; 706 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 707 clock-names = "apb_pclk"; 708 }; 709 710 gpio19: gpio@ff3b5000 { 711 compatible = "arm,pl061", "arm,primecell"; 712 reg = <0 0xff3b5000 0 0x1000>; 713 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 714 gpio-controller; 715 #gpio-cells = <2>; 716 gpio-ranges = <&pmx2 0 8 4>; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 720 clock-names = "apb_pclk"; 721 }; 722 723 gpio20: gpio@e8a1f000 { 724 compatible = "arm,pl061", "arm,primecell"; 725 reg = <0 0xe8a1f000 0 0x1000>; 726 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 727 gpio-controller; 728 #gpio-cells = <2>; 729 gpio-ranges = <&pmx1 0 0 6>; 730 interrupt-controller; 731 #interrupt-cells = <2>; 732 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 733 clock-names = "apb_pclk"; 734 }; 735 736 gpio21: gpio@e8a20000 { 737 compatible = "arm,pl061", "arm,primecell"; 738 reg = <0 0xe8a20000 0 0x1000>; 739 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 740 gpio-controller; 741 #gpio-cells = <2>; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 gpio-ranges = <&pmx3 0 0 6>; 745 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 746 clock-names = "apb_pclk"; 747 }; 748 749 gpio22: gpio@fff0b000 { 750 compatible = "arm,pl061", "arm,primecell"; 751 reg = <0 0xfff0b000 0 0x1000>; 752 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 753 gpio-controller; 754 #gpio-cells = <2>; 755 /* GPIO176 */ 756 gpio-ranges = <&pmx4 2 0 6>; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 760 clock-names = "apb_pclk"; 761 }; 762 763 gpio23: gpio@fff0c000 { 764 compatible = "arm,pl061", "arm,primecell"; 765 reg = <0 0xfff0c000 0 0x1000>; 766 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 767 gpio-controller; 768 #gpio-cells = <2>; 769 /* GPIO184 */ 770 gpio-ranges = <&pmx4 0 6 7>; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 774 clock-names = "apb_pclk"; 775 }; 776 777 gpio24: gpio@fff0d000 { 778 compatible = "arm,pl061", "arm,primecell"; 779 reg = <0 0xfff0d000 0 0x1000>; 780 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 781 gpio-controller; 782 #gpio-cells = <2>; 783 /* GPIO192 */ 784 gpio-ranges = <&pmx4 0 13 8>; 785 interrupt-controller; 786 #interrupt-cells = <2>; 787 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 788 clock-names = "apb_pclk"; 789 }; 790 791 gpio25: gpio@fff0e000 { 792 compatible = "arm,pl061", "arm,primecell"; 793 reg = <0 0xfff0e000 0 0x1000>; 794 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 795 gpio-controller; 796 #gpio-cells = <2>; 797 /* GPIO200 */ 798 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 802 clock-names = "apb_pclk"; 803 }; 804 805 gpio26: gpio@fff0f000 { 806 compatible = "arm,pl061", "arm,primecell"; 807 reg = <0 0xfff0f000 0 0x1000>; 808 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 809 gpio-controller; 810 #gpio-cells = <2>; 811 /* GPIO208 */ 812 gpio-ranges = <&pmx4 0 28 8>; 813 interrupt-controller; 814 #interrupt-cells = <2>; 815 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 816 clock-names = "apb_pclk"; 817 }; 818 819 gpio27: gpio@fff10000 { 820 compatible = "arm,pl061", "arm,primecell"; 821 reg = <0 0xfff10000 0 0x1000>; 822 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 823 gpio-controller; 824 #gpio-cells = <2>; 825 /* GPIO216 */ 826 gpio-ranges = <&pmx4 0 36 6>; 827 interrupt-controller; 828 #interrupt-cells = <2>; 829 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 830 clock-names = "apb_pclk"; 831 }; 832 833 gpio28: gpio@fff1d000 { 834 compatible = "arm,pl061", "arm,primecell"; 835 reg = <0 0xfff1d000 0 0x1000>; 836 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 837 gpio-controller; 838 #gpio-cells = <2>; 839 interrupt-controller; 840 #interrupt-cells = <2>; 841 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 842 clock-names = "apb_pclk"; 843 }; 844 845 spi2: spi@ffd68000 { 846 compatible = "arm,pl022", "arm,primecell"; 847 reg = <0x0 0xffd68000 0x0 0x1000>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 852 clock-names = "apb_pclk"; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&spi2_pmx_func>; 855 num-cs = <1>; 856 cs-gpios = <&gpio27 2 0>; 857 status = "disabled"; 858 }; 859 860 spi3: spi@ff3b3000 { 861 compatible = "arm,pl022", "arm,primecell"; 862 reg = <0x0 0xff3b3000 0x0 0x1000>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 867 clock-names = "apb_pclk"; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&spi3_pmx_func>; 870 num-cs = <1>; 871 cs-gpios = <&gpio18 5 0>; 872 status = "disabled"; 873 }; 874 875 pcie@f4000000 { 876 compatible = "hisilicon,kirin960-pcie"; 877 reg = <0x0 0xf4000000 0x0 0x1000>, 878 <0x0 0xff3fe000 0x0 0x1000>, 879 <0x0 0xf3f20000 0x0 0x40000>, 880 <0x0 0xf5000000 0x0 0x2000>; 881 reg-names = "dbi", "apb", "phy", "config"; 882 bus-range = <0x0 0x1>; 883 #address-cells = <3>; 884 #size-cells = <2>; 885 device_type = "pci"; 886 ranges = <0x02000000 0x0 0x00000000 887 0x0 0xf6000000 888 0x0 0x02000000>; 889 num-lanes = <1>; 890 #interrupt-cells = <1>; 891 interrupt-map-mask = <0xf800 0 0 7>; 892 interrupt-map = <0x0 0 0 1 893 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 894 <0x0 0 0 2 895 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 896 <0x0 0 0 3 897 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 898 <0x0 0 0 4 899 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 901 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 902 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 903 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 904 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 905 clock-names = "pcie_phy_ref", "pcie_aux", 906 "pcie_apb_phy", "pcie_apb_sys", 907 "pcie_aclk"; 908 reset-gpios = <&gpio11 1 0 >; 909 }; 910 911 /* SD */ 912 dwmmc1: dwmmc1@ff37f000 { 913 #address-cells = <1>; 914 #size-cells = <0>; 915 cd-inverted; 916 compatible = "hisilicon,hi3660-dw-mshc"; 917 num-slots = <1>; 918 bus-width = <0x4>; 919 disable-wp; 920 cap-sd-highspeed; 921 supports-highspeed; 922 card-detect-delay = <200>; 923 reg = <0x0 0xff37f000 0x0 0x1000>; 924 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 926 <&crg_ctrl HI3660_HCLK_GATE_SD>; 927 clock-names = "ciu", "biu"; 928 clock-frequency = <3200000>; 929 resets = <&crg_rst 0x94 18>; 930 reset-names = "reset"; 931 cd-gpios = <&gpio25 3 0>; 932 hisilicon,peripheral-syscon = <&sctrl>; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&sd_pmx_func 935 &sd_clk_cfg_func 936 &sd_cfg_func>; 937 sd-uhs-sdr12; 938 sd-uhs-sdr25; 939 sd-uhs-sdr50; 940 sd-uhs-sdr104; 941 status = "disabled"; 942 943 slot@0 { 944 reg = <0x0>; 945 bus-width = <4>; 946 disable-wp; 947 }; 948 }; 949 950 /* SDIO */ 951 dwmmc2: dwmmc2@ff3ff000 { 952 compatible = "hisilicon,hi3660-dw-mshc"; 953 reg = <0x0 0xff3ff000 0x0 0x1000>; 954 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 955 num-slots = <1>; 956 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 957 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 958 clock-names = "ciu", "biu"; 959 resets = <&crg_rst 0x94 20>; 960 reset-names = "reset"; 961 card-detect-delay = <200>; 962 supports-highspeed; 963 keep-power-in-suspend; 964 pinctrl-names = "default"; 965 pinctrl-0 = <&sdio_pmx_func 966 &sdio_clk_cfg_func 967 &sdio_cfg_func>; 968 status = "disabled"; 969 }; 970 971 watchdog0: watchdog@e8a06000 { 972 compatible = "arm,sp805-wdt", "arm,primecell"; 973 reg = <0x0 0xe8a06000 0x0 0x1000>; 974 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&crg_ctrl HI3660_OSC32K>; 976 clock-names = "apb_pclk"; 977 }; 978 979 watchdog1: watchdog@e8a07000 { 980 compatible = "arm,sp805-wdt", "arm,primecell"; 981 reg = <0x0 0xe8a07000 0x0 0x1000>; 982 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&crg_ctrl HI3660_OSC32K>; 984 clock-names = "apb_pclk"; 985 }; 986 987 tsensor: tsensor@fff30000 { 988 compatible = "hisilicon,hi3660-tsensor"; 989 reg = <0x0 0xfff30000 0x0 0x1000>; 990 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 991 #thermal-sensor-cells = <1>; 992 }; 993 }; 994}; 995