1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3660 SoC 4 * 5 * Copyright (C) 2016, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/hi3660-clock.h> 10 11/ { 12 compatible = "hisilicon,hi3660"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 psci { 18 compatible = "arm,psci-0.2"; 19 method = "smc"; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 core2 { 35 cpu = <&cpu2>; 36 }; 37 core3 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 device_type = "cpu"; 60 reg = <0x0 0x0>; 61 enable-method = "psci"; 62 next-level-cache = <&A53_L2>; 63 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 64 capacity-dmips-mhz = <592>; 65 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 66 operating-points-v2 = <&cluster0_opp>; 67 }; 68 69 cpu1: cpu@1 { 70 compatible = "arm,cortex-a53", "arm,armv8"; 71 device_type = "cpu"; 72 reg = <0x0 0x1>; 73 enable-method = "psci"; 74 next-level-cache = <&A53_L2>; 75 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 76 capacity-dmips-mhz = <592>; 77 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 78 operating-points-v2 = <&cluster0_opp>; 79 }; 80 81 cpu2: cpu@2 { 82 compatible = "arm,cortex-a53", "arm,armv8"; 83 device_type = "cpu"; 84 reg = <0x0 0x2>; 85 enable-method = "psci"; 86 next-level-cache = <&A53_L2>; 87 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 88 capacity-dmips-mhz = <592>; 89 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 90 operating-points-v2 = <&cluster0_opp>; 91 }; 92 93 cpu3: cpu@3 { 94 compatible = "arm,cortex-a53", "arm,armv8"; 95 device_type = "cpu"; 96 reg = <0x0 0x3>; 97 enable-method = "psci"; 98 next-level-cache = <&A53_L2>; 99 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 100 capacity-dmips-mhz = <592>; 101 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 102 operating-points-v2 = <&cluster0_opp>; 103 }; 104 105 cpu4: cpu@100 { 106 compatible = "arm,cortex-a73", "arm,armv8"; 107 device_type = "cpu"; 108 reg = <0x0 0x100>; 109 enable-method = "psci"; 110 next-level-cache = <&A73_L2>; 111 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 112 capacity-dmips-mhz = <1024>; 113 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 114 operating-points-v2 = <&cluster1_opp>; 115 }; 116 117 cpu5: cpu@101 { 118 compatible = "arm,cortex-a73", "arm,armv8"; 119 device_type = "cpu"; 120 reg = <0x0 0x101>; 121 enable-method = "psci"; 122 next-level-cache = <&A73_L2>; 123 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 124 capacity-dmips-mhz = <1024>; 125 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 126 operating-points-v2 = <&cluster1_opp>; 127 }; 128 129 cpu6: cpu@102 { 130 compatible = "arm,cortex-a73", "arm,armv8"; 131 device_type = "cpu"; 132 reg = <0x0 0x102>; 133 enable-method = "psci"; 134 next-level-cache = <&A73_L2>; 135 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 136 capacity-dmips-mhz = <1024>; 137 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 138 operating-points-v2 = <&cluster1_opp>; 139 }; 140 141 cpu7: cpu@103 { 142 compatible = "arm,cortex-a73", "arm,armv8"; 143 device_type = "cpu"; 144 reg = <0x0 0x103>; 145 enable-method = "psci"; 146 next-level-cache = <&A73_L2>; 147 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 148 capacity-dmips-mhz = <1024>; 149 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 150 operating-points-v2 = <&cluster1_opp>; 151 }; 152 153 idle-states { 154 entry-method = "psci"; 155 156 CPU_SLEEP: cpu-sleep { 157 compatible = "arm,idle-state"; 158 local-timer-stop; 159 arm,psci-suspend-param = <0x0010000>; 160 entry-latency-us = <40>; 161 exit-latency-us = <70>; 162 min-residency-us = <3000>; 163 }; 164 165 CLUSTER_SLEEP_0: cluster-sleep-0 { 166 compatible = "arm,idle-state"; 167 local-timer-stop; 168 arm,psci-suspend-param = <0x1010000>; 169 entry-latency-us = <500>; 170 exit-latency-us = <5000>; 171 min-residency-us = <20000>; 172 }; 173 174 CLUSTER_SLEEP_1: cluster-sleep-1 { 175 compatible = "arm,idle-state"; 176 local-timer-stop; 177 arm,psci-suspend-param = <0x1010000>; 178 entry-latency-us = <1000>; 179 exit-latency-us = <5000>; 180 min-residency-us = <20000>; 181 }; 182 }; 183 184 A53_L2: l2-cache0 { 185 compatible = "cache"; 186 }; 187 188 A73_L2: l2-cache1 { 189 compatible = "cache"; 190 }; 191 }; 192 193 cluster0_opp: opp_table0 { 194 compatible = "operating-points-v2"; 195 opp-shared; 196 197 opp00 { 198 opp-hz = /bits/ 64 <533000000>; 199 opp-microvolt = <700000>; 200 clock-latency-ns = <300000>; 201 }; 202 203 opp01 { 204 opp-hz = /bits/ 64 <999000000>; 205 opp-microvolt = <800000>; 206 clock-latency-ns = <300000>; 207 }; 208 209 opp02 { 210 opp-hz = /bits/ 64 <1402000000>; 211 opp-microvolt = <900000>; 212 clock-latency-ns = <300000>; 213 }; 214 215 opp03 { 216 opp-hz = /bits/ 64 <1709000000>; 217 opp-microvolt = <1000000>; 218 clock-latency-ns = <300000>; 219 }; 220 221 opp04 { 222 opp-hz = /bits/ 64 <1844000000>; 223 opp-microvolt = <1100000>; 224 clock-latency-ns = <300000>; 225 }; 226 }; 227 228 cluster1_opp: opp_table1 { 229 compatible = "operating-points-v2"; 230 opp-shared; 231 232 opp10 { 233 opp-hz = /bits/ 64 <903000000>; 234 opp-microvolt = <700000>; 235 clock-latency-ns = <300000>; 236 }; 237 238 opp11 { 239 opp-hz = /bits/ 64 <1421000000>; 240 opp-microvolt = <800000>; 241 clock-latency-ns = <300000>; 242 }; 243 244 opp12 { 245 opp-hz = /bits/ 64 <1805000000>; 246 opp-microvolt = <900000>; 247 clock-latency-ns = <300000>; 248 }; 249 250 opp13 { 251 opp-hz = /bits/ 64 <2112000000>; 252 opp-microvolt = <1000000>; 253 clock-latency-ns = <300000>; 254 }; 255 256 opp14 { 257 opp-hz = /bits/ 64 <2362000000>; 258 opp-microvolt = <1100000>; 259 clock-latency-ns = <300000>; 260 }; 261 }; 262 263 gic: interrupt-controller@e82b0000 { 264 compatible = "arm,gic-400"; 265 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 266 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 267 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 268 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 269 #address-cells = <0>; 270 #interrupt-cells = <3>; 271 interrupt-controller; 272 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 273 IRQ_TYPE_LEVEL_HIGH)>; 274 }; 275 276 a53-pmu { 277 compatible = "arm,cortex-a53-pmu"; 278 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 282 interrupt-affinity = <&cpu0>, 283 <&cpu1>, 284 <&cpu2>, 285 <&cpu3>; 286 }; 287 288 a73-pmu { 289 compatible = "arm,cortex-a73-pmu"; 290 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 294 interrupt-affinity = <&cpu4>, 295 <&cpu5>, 296 <&cpu6>, 297 <&cpu7>; 298 }; 299 300 timer { 301 compatible = "arm,armv8-timer"; 302 interrupt-parent = <&gic>; 303 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 304 IRQ_TYPE_LEVEL_LOW)>, 305 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 306 IRQ_TYPE_LEVEL_LOW)>, 307 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 308 IRQ_TYPE_LEVEL_LOW)>, 309 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 310 IRQ_TYPE_LEVEL_LOW)>; 311 }; 312 313 soc { 314 compatible = "simple-bus"; 315 #address-cells = <2>; 316 #size-cells = <2>; 317 ranges; 318 319 crg_ctrl: crg_ctrl@fff35000 { 320 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 321 reg = <0x0 0xfff35000 0x0 0x1000>; 322 #clock-cells = <1>; 323 }; 324 325 crg_rst: crg_rst_controller { 326 compatible = "hisilicon,hi3660-reset"; 327 #reset-cells = <2>; 328 hisi,rst-syscon = <&crg_ctrl>; 329 }; 330 331 332 pctrl: pctrl@e8a09000 { 333 compatible = "hisilicon,hi3660-pctrl", "syscon"; 334 reg = <0x0 0xe8a09000 0x0 0x2000>; 335 #clock-cells = <1>; 336 }; 337 338 pmuctrl: crg_ctrl@fff34000 { 339 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 340 reg = <0x0 0xfff34000 0x0 0x1000>; 341 #clock-cells = <1>; 342 }; 343 344 sctrl: sctrl@fff0a000 { 345 compatible = "hisilicon,hi3660-sctrl", "syscon"; 346 reg = <0x0 0xfff0a000 0x0 0x1000>; 347 #clock-cells = <1>; 348 }; 349 350 iomcu: iomcu@ffd7e000 { 351 compatible = "hisilicon,hi3660-iomcu", "syscon"; 352 reg = <0x0 0xffd7e000 0x0 0x1000>; 353 #clock-cells = <1>; 354 355 }; 356 357 iomcu_rst: reset { 358 compatible = "hisilicon,hi3660-reset"; 359 hisi,rst-syscon = <&iomcu>; 360 #reset-cells = <2>; 361 }; 362 363 mailbox: mailbox@e896b000 { 364 compatible = "hisilicon,hi3660-mbox"; 365 reg = <0x0 0xe896b000 0x0 0x1000>; 366 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 368 #mbox-cells = <3>; 369 }; 370 371 stub_clock: stub_clock@e896b500 { 372 compatible = "hisilicon,hi3660-stub-clk"; 373 reg = <0x0 0xe896b500 0x0 0x0100>; 374 #clock-cells = <1>; 375 mboxes = <&mailbox 13 3 0>; 376 }; 377 378 dual_timer0: timer@fff14000 { 379 compatible = "arm,sp804", "arm,primecell"; 380 reg = <0x0 0xfff14000 0x0 0x1000>; 381 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&crg_ctrl HI3660_OSC32K>, 384 <&crg_ctrl HI3660_OSC32K>, 385 <&crg_ctrl HI3660_OSC32K>; 386 clock-names = "timer1", "timer2", "apb_pclk"; 387 }; 388 389 i2c0: i2c@ffd71000 { 390 compatible = "snps,designware-i2c"; 391 reg = <0x0 0xffd71000 0x0 0x1000>; 392 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 clock-frequency = <400000>; 396 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 397 resets = <&iomcu_rst 0x20 3>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 400 status = "disabled"; 401 }; 402 403 i2c1: i2c@ffd72000 { 404 compatible = "snps,designware-i2c"; 405 reg = <0x0 0xffd72000 0x0 0x1000>; 406 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 clock-frequency = <400000>; 410 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 411 resets = <&iomcu_rst 0x20 4>; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 414 status = "disabled"; 415 }; 416 417 i2c3: i2c@fdf0c000 { 418 compatible = "snps,designware-i2c"; 419 reg = <0x0 0xfdf0c000 0x0 0x1000>; 420 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 clock-frequency = <400000>; 424 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 425 resets = <&crg_rst 0x78 7>; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 428 status = "disabled"; 429 }; 430 431 i2c7: i2c@fdf0b000 { 432 compatible = "snps,designware-i2c"; 433 reg = <0x0 0xfdf0b000 0x0 0x1000>; 434 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 clock-frequency = <400000>; 438 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 439 resets = <&crg_rst 0x60 14>; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 442 status = "disabled"; 443 }; 444 445 uart0: serial@fdf02000 { 446 compatible = "arm,pl011", "arm,primecell"; 447 reg = <0x0 0xfdf02000 0x0 0x1000>; 448 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 450 <&crg_ctrl HI3660_PCLK>; 451 clock-names = "uartclk", "apb_pclk"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 454 status = "disabled"; 455 }; 456 457 uart1: serial@fdf00000 { 458 compatible = "arm,pl011", "arm,primecell"; 459 reg = <0x0 0xfdf00000 0x0 0x1000>; 460 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 462 <&crg_ctrl HI3660_CLK_GATE_UART1>; 463 clock-names = "uartclk", "apb_pclk"; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 466 status = "disabled"; 467 }; 468 469 uart2: serial@fdf03000 { 470 compatible = "arm,pl011", "arm,primecell"; 471 reg = <0x0 0xfdf03000 0x0 0x1000>; 472 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 474 <&crg_ctrl HI3660_PCLK>; 475 clock-names = "uartclk", "apb_pclk"; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 478 status = "disabled"; 479 }; 480 481 uart3: serial@ffd74000 { 482 compatible = "arm,pl011", "arm,primecell"; 483 reg = <0x0 0xffd74000 0x0 0x1000>; 484 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 486 <&crg_ctrl HI3660_PCLK>; 487 clock-names = "uartclk", "apb_pclk"; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 490 status = "disabled"; 491 }; 492 493 uart4: serial@fdf01000 { 494 compatible = "arm,pl011", "arm,primecell"; 495 reg = <0x0 0xfdf01000 0x0 0x1000>; 496 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 498 <&crg_ctrl HI3660_CLK_GATE_UART4>; 499 clock-names = "uartclk", "apb_pclk"; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 502 status = "disabled"; 503 }; 504 505 uart5: serial@fdf05000 { 506 compatible = "arm,pl011", "arm,primecell"; 507 reg = <0x0 0xfdf05000 0x0 0x1000>; 508 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 510 <&crg_ctrl HI3660_CLK_GATE_UART5>; 511 clock-names = "uartclk", "apb_pclk"; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 514 status = "disabled"; 515 }; 516 517 uart6: serial@fff32000 { 518 compatible = "arm,pl011", "arm,primecell"; 519 reg = <0x0 0xfff32000 0x0 0x1000>; 520 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&crg_ctrl HI3660_CLK_UART6>, 522 <&crg_ctrl HI3660_PCLK>; 523 clock-names = "uartclk", "apb_pclk"; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 526 status = "disabled"; 527 }; 528 529 dma0: dma@fdf30000 { 530 compatible = "hisilicon,k3-dma-1.0"; 531 reg = <0x0 0xfdf30000 0x0 0x1000>; 532 #dma-cells = <1>; 533 dma-channels = <16>; 534 dma-requests = <32>; 535 dma-min-chan = <1>; 536 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 538 dma-no-cci; 539 dma-type = "hi3660_dma"; 540 }; 541 542 rtc0: rtc@fff04000 { 543 compatible = "arm,pl031", "arm,primecell"; 544 reg = <0x0 0Xfff04000 0x0 0x1000>; 545 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&crg_ctrl HI3660_PCLK>; 547 clock-names = "apb_pclk"; 548 }; 549 550 gpio0: gpio@e8a0b000 { 551 compatible = "arm,pl061", "arm,primecell"; 552 reg = <0 0xe8a0b000 0 0x1000>; 553 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 554 gpio-controller; 555 #gpio-cells = <2>; 556 gpio-ranges = <&pmx0 1 0 7>; 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 560 clock-names = "apb_pclk"; 561 }; 562 563 gpio1: gpio@e8a0c000 { 564 compatible = "arm,pl061", "arm,primecell"; 565 reg = <0 0xe8a0c000 0 0x1000>; 566 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 567 gpio-controller; 568 #gpio-cells = <2>; 569 gpio-ranges = <&pmx0 1 7 7>; 570 interrupt-controller; 571 #interrupt-cells = <2>; 572 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 573 clock-names = "apb_pclk"; 574 }; 575 576 gpio2: gpio@e8a0d000 { 577 compatible = "arm,pl061", "arm,primecell"; 578 reg = <0 0xe8a0d000 0 0x1000>; 579 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 580 gpio-controller; 581 #gpio-cells = <2>; 582 gpio-ranges = <&pmx0 0 14 8>; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 586 clock-names = "apb_pclk"; 587 }; 588 589 gpio3: gpio@e8a0e000 { 590 compatible = "arm,pl061", "arm,primecell"; 591 reg = <0 0xe8a0e000 0 0x1000>; 592 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 593 gpio-controller; 594 #gpio-cells = <2>; 595 gpio-ranges = <&pmx0 0 22 8>; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 599 clock-names = "apb_pclk"; 600 }; 601 602 gpio4: gpio@e8a0f000 { 603 compatible = "arm,pl061", "arm,primecell"; 604 reg = <0 0xe8a0f000 0 0x1000>; 605 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 606 gpio-controller; 607 #gpio-cells = <2>; 608 gpio-ranges = <&pmx0 0 30 8>; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 612 clock-names = "apb_pclk"; 613 }; 614 615 gpio5: gpio@e8a10000 { 616 compatible = "arm,pl061", "arm,primecell"; 617 reg = <0 0xe8a10000 0 0x1000>; 618 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 619 gpio-controller; 620 #gpio-cells = <2>; 621 gpio-ranges = <&pmx0 0 38 8>; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 625 clock-names = "apb_pclk"; 626 }; 627 628 gpio6: gpio@e8a11000 { 629 compatible = "arm,pl061", "arm,primecell"; 630 reg = <0 0xe8a11000 0 0x1000>; 631 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 632 gpio-controller; 633 #gpio-cells = <2>; 634 gpio-ranges = <&pmx0 0 46 8>; 635 interrupt-controller; 636 #interrupt-cells = <2>; 637 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 638 clock-names = "apb_pclk"; 639 }; 640 641 gpio7: gpio@e8a12000 { 642 compatible = "arm,pl061", "arm,primecell"; 643 reg = <0 0xe8a12000 0 0x1000>; 644 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 645 gpio-controller; 646 #gpio-cells = <2>; 647 gpio-ranges = <&pmx0 0 54 8>; 648 interrupt-controller; 649 #interrupt-cells = <2>; 650 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 651 clock-names = "apb_pclk"; 652 }; 653 654 gpio8: gpio@e8a13000 { 655 compatible = "arm,pl061", "arm,primecell"; 656 reg = <0 0xe8a13000 0 0x1000>; 657 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 658 gpio-controller; 659 #gpio-cells = <2>; 660 gpio-ranges = <&pmx0 0 62 8>; 661 interrupt-controller; 662 #interrupt-cells = <2>; 663 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 664 clock-names = "apb_pclk"; 665 }; 666 667 gpio9: gpio@e8a14000 { 668 compatible = "arm,pl061", "arm,primecell"; 669 reg = <0 0xe8a14000 0 0x1000>; 670 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 671 gpio-controller; 672 #gpio-cells = <2>; 673 gpio-ranges = <&pmx0 0 70 8>; 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 677 clock-names = "apb_pclk"; 678 }; 679 680 gpio10: gpio@e8a15000 { 681 compatible = "arm,pl061", "arm,primecell"; 682 reg = <0 0xe8a15000 0 0x1000>; 683 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 684 gpio-controller; 685 #gpio-cells = <2>; 686 gpio-ranges = <&pmx0 0 78 8>; 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 690 clock-names = "apb_pclk"; 691 }; 692 693 gpio11: gpio@e8a16000 { 694 compatible = "arm,pl061", "arm,primecell"; 695 reg = <0 0xe8a16000 0 0x1000>; 696 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 697 gpio-controller; 698 #gpio-cells = <2>; 699 gpio-ranges = <&pmx0 0 86 8>; 700 interrupt-controller; 701 #interrupt-cells = <2>; 702 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 703 clock-names = "apb_pclk"; 704 }; 705 706 gpio12: gpio@e8a17000 { 707 compatible = "arm,pl061", "arm,primecell"; 708 reg = <0 0xe8a17000 0 0x1000>; 709 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 710 gpio-controller; 711 #gpio-cells = <2>; 712 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 716 clock-names = "apb_pclk"; 717 }; 718 719 gpio13: gpio@e8a18000 { 720 compatible = "arm,pl061", "arm,primecell"; 721 reg = <0 0xe8a18000 0 0x1000>; 722 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 723 gpio-controller; 724 #gpio-cells = <2>; 725 gpio-ranges = <&pmx0 0 102 8>; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 729 clock-names = "apb_pclk"; 730 }; 731 732 gpio14: gpio@e8a19000 { 733 compatible = "arm,pl061", "arm,primecell"; 734 reg = <0 0xe8a19000 0 0x1000>; 735 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 736 gpio-controller; 737 #gpio-cells = <2>; 738 gpio-ranges = <&pmx0 0 110 8>; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 742 clock-names = "apb_pclk"; 743 }; 744 745 gpio15: gpio@e8a1a000 { 746 compatible = "arm,pl061", "arm,primecell"; 747 reg = <0 0xe8a1a000 0 0x1000>; 748 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 749 gpio-controller; 750 #gpio-cells = <2>; 751 gpio-ranges = <&pmx0 0 118 6>; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 755 clock-names = "apb_pclk"; 756 }; 757 758 gpio16: gpio@e8a1b000 { 759 compatible = "arm,pl061", "arm,primecell"; 760 reg = <0 0xe8a1b000 0 0x1000>; 761 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 762 gpio-controller; 763 #gpio-cells = <2>; 764 interrupt-controller; 765 #interrupt-cells = <2>; 766 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 767 clock-names = "apb_pclk"; 768 }; 769 770 gpio17: gpio@e8a1c000 { 771 compatible = "arm,pl061", "arm,primecell"; 772 reg = <0 0xe8a1c000 0 0x1000>; 773 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 774 gpio-controller; 775 #gpio-cells = <2>; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 779 clock-names = "apb_pclk"; 780 }; 781 782 gpio18: gpio@ff3b4000 { 783 compatible = "arm,pl061", "arm,primecell"; 784 reg = <0 0xff3b4000 0 0x1000>; 785 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 786 gpio-controller; 787 #gpio-cells = <2>; 788 gpio-ranges = <&pmx2 0 0 8>; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 792 clock-names = "apb_pclk"; 793 }; 794 795 gpio19: gpio@ff3b5000 { 796 compatible = "arm,pl061", "arm,primecell"; 797 reg = <0 0xff3b5000 0 0x1000>; 798 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 799 gpio-controller; 800 #gpio-cells = <2>; 801 gpio-ranges = <&pmx2 0 8 4>; 802 interrupt-controller; 803 #interrupt-cells = <2>; 804 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 805 clock-names = "apb_pclk"; 806 }; 807 808 gpio20: gpio@e8a1f000 { 809 compatible = "arm,pl061", "arm,primecell"; 810 reg = <0 0xe8a1f000 0 0x1000>; 811 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 812 gpio-controller; 813 #gpio-cells = <2>; 814 gpio-ranges = <&pmx1 0 0 6>; 815 interrupt-controller; 816 #interrupt-cells = <2>; 817 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 818 clock-names = "apb_pclk"; 819 }; 820 821 gpio21: gpio@e8a20000 { 822 compatible = "arm,pl061", "arm,primecell"; 823 reg = <0 0xe8a20000 0 0x1000>; 824 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 825 gpio-controller; 826 #gpio-cells = <2>; 827 interrupt-controller; 828 #interrupt-cells = <2>; 829 gpio-ranges = <&pmx3 0 0 6>; 830 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 831 clock-names = "apb_pclk"; 832 }; 833 834 gpio22: gpio@fff0b000 { 835 compatible = "arm,pl061", "arm,primecell"; 836 reg = <0 0xfff0b000 0 0x1000>; 837 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 838 gpio-controller; 839 #gpio-cells = <2>; 840 /* GPIO176 */ 841 gpio-ranges = <&pmx4 2 0 6>; 842 interrupt-controller; 843 #interrupt-cells = <2>; 844 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 845 clock-names = "apb_pclk"; 846 }; 847 848 gpio23: gpio@fff0c000 { 849 compatible = "arm,pl061", "arm,primecell"; 850 reg = <0 0xfff0c000 0 0x1000>; 851 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 852 gpio-controller; 853 #gpio-cells = <2>; 854 /* GPIO184 */ 855 gpio-ranges = <&pmx4 0 6 7>; 856 interrupt-controller; 857 #interrupt-cells = <2>; 858 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 859 clock-names = "apb_pclk"; 860 }; 861 862 gpio24: gpio@fff0d000 { 863 compatible = "arm,pl061", "arm,primecell"; 864 reg = <0 0xfff0d000 0 0x1000>; 865 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 866 gpio-controller; 867 #gpio-cells = <2>; 868 /* GPIO192 */ 869 gpio-ranges = <&pmx4 0 13 8>; 870 interrupt-controller; 871 #interrupt-cells = <2>; 872 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 873 clock-names = "apb_pclk"; 874 }; 875 876 gpio25: gpio@fff0e000 { 877 compatible = "arm,pl061", "arm,primecell"; 878 reg = <0 0xfff0e000 0 0x1000>; 879 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 880 gpio-controller; 881 #gpio-cells = <2>; 882 /* GPIO200 */ 883 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 884 interrupt-controller; 885 #interrupt-cells = <2>; 886 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 887 clock-names = "apb_pclk"; 888 }; 889 890 gpio26: gpio@fff0f000 { 891 compatible = "arm,pl061", "arm,primecell"; 892 reg = <0 0xfff0f000 0 0x1000>; 893 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 894 gpio-controller; 895 #gpio-cells = <2>; 896 /* GPIO208 */ 897 gpio-ranges = <&pmx4 0 28 8>; 898 interrupt-controller; 899 #interrupt-cells = <2>; 900 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 901 clock-names = "apb_pclk"; 902 }; 903 904 gpio27: gpio@fff10000 { 905 compatible = "arm,pl061", "arm,primecell"; 906 reg = <0 0xfff10000 0 0x1000>; 907 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 908 gpio-controller; 909 #gpio-cells = <2>; 910 /* GPIO216 */ 911 gpio-ranges = <&pmx4 0 36 6>; 912 interrupt-controller; 913 #interrupt-cells = <2>; 914 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 915 clock-names = "apb_pclk"; 916 }; 917 918 gpio28: gpio@fff1d000 { 919 compatible = "arm,pl061", "arm,primecell"; 920 reg = <0 0xfff1d000 0 0x1000>; 921 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 922 gpio-controller; 923 #gpio-cells = <2>; 924 interrupt-controller; 925 #interrupt-cells = <2>; 926 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 927 clock-names = "apb_pclk"; 928 }; 929 930 spi2: spi@ffd68000 { 931 compatible = "arm,pl022", "arm,primecell"; 932 reg = <0x0 0xffd68000 0x0 0x1000>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 937 clock-names = "apb_pclk"; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&spi2_pmx_func>; 940 num-cs = <1>; 941 cs-gpios = <&gpio27 2 0>; 942 status = "disabled"; 943 }; 944 945 spi3: spi@ff3b3000 { 946 compatible = "arm,pl022", "arm,primecell"; 947 reg = <0x0 0xff3b3000 0x0 0x1000>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 952 clock-names = "apb_pclk"; 953 pinctrl-names = "default"; 954 pinctrl-0 = <&spi3_pmx_func>; 955 num-cs = <1>; 956 cs-gpios = <&gpio18 5 0>; 957 status = "disabled"; 958 }; 959 960 pcie@f4000000 { 961 compatible = "hisilicon,kirin960-pcie"; 962 reg = <0x0 0xf4000000 0x0 0x1000>, 963 <0x0 0xff3fe000 0x0 0x1000>, 964 <0x0 0xf3f20000 0x0 0x40000>, 965 <0x0 0xf5000000 0x0 0x2000>; 966 reg-names = "dbi", "apb", "phy", "config"; 967 bus-range = <0x0 0x1>; 968 #address-cells = <3>; 969 #size-cells = <2>; 970 device_type = "pci"; 971 ranges = <0x02000000 0x0 0x00000000 972 0x0 0xf6000000 973 0x0 0x02000000>; 974 num-lanes = <1>; 975 #interrupt-cells = <1>; 976 interrupt-map-mask = <0xf800 0 0 7>; 977 interrupt-map = <0x0 0 0 1 978 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 979 <0x0 0 0 2 980 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 981 <0x0 0 0 3 982 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 983 <0x0 0 0 4 984 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 986 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 987 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 988 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 989 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 990 clock-names = "pcie_phy_ref", "pcie_aux", 991 "pcie_apb_phy", "pcie_apb_sys", 992 "pcie_aclk"; 993 reset-gpios = <&gpio11 1 0 >; 994 }; 995 996 /* SD */ 997 dwmmc1: dwmmc1@ff37f000 { 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 cd-inverted; 1001 compatible = "hisilicon,hi3660-dw-mshc"; 1002 bus-width = <0x4>; 1003 disable-wp; 1004 cap-sd-highspeed; 1005 supports-highspeed; 1006 card-detect-delay = <200>; 1007 reg = <0x0 0xff37f000 0x0 0x1000>; 1008 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 1010 <&crg_ctrl HI3660_HCLK_GATE_SD>; 1011 clock-names = "ciu", "biu"; 1012 clock-frequency = <3200000>; 1013 resets = <&crg_rst 0x94 18>; 1014 reset-names = "reset"; 1015 cd-gpios = <&gpio25 3 0>; 1016 hisilicon,peripheral-syscon = <&sctrl>; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&sd_pmx_func 1019 &sd_clk_cfg_func 1020 &sd_cfg_func>; 1021 sd-uhs-sdr12; 1022 sd-uhs-sdr25; 1023 sd-uhs-sdr50; 1024 sd-uhs-sdr104; 1025 status = "disabled"; 1026 1027 slot@0 { 1028 reg = <0x0>; 1029 bus-width = <4>; 1030 disable-wp; 1031 }; 1032 }; 1033 1034 /* SDIO */ 1035 dwmmc2: dwmmc2@ff3ff000 { 1036 compatible = "hisilicon,hi3660-dw-mshc"; 1037 reg = <0x0 0xff3ff000 0x0 0x1000>; 1038 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 1040 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 1041 clock-names = "ciu", "biu"; 1042 resets = <&crg_rst 0x94 20>; 1043 reset-names = "reset"; 1044 card-detect-delay = <200>; 1045 supports-highspeed; 1046 keep-power-in-suspend; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&sdio_pmx_func 1049 &sdio_clk_cfg_func 1050 &sdio_cfg_func>; 1051 status = "disabled"; 1052 }; 1053 1054 watchdog0: watchdog@e8a06000 { 1055 compatible = "arm,sp805-wdt", "arm,primecell"; 1056 reg = <0x0 0xe8a06000 0x0 0x1000>; 1057 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&crg_ctrl HI3660_OSC32K>; 1059 clock-names = "apb_pclk"; 1060 }; 1061 1062 watchdog1: watchdog@e8a07000 { 1063 compatible = "arm,sp805-wdt", "arm,primecell"; 1064 reg = <0x0 0xe8a07000 0x0 0x1000>; 1065 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&crg_ctrl HI3660_OSC32K>; 1067 clock-names = "apb_pclk"; 1068 }; 1069 1070 tsensor: tsensor@fff30000 { 1071 compatible = "hisilicon,hi3660-tsensor"; 1072 reg = <0x0 0xfff30000 0x0 0x1000>; 1073 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1074 #thermal-sensor-cells = <1>; 1075 }; 1076 }; 1077}; 1078