1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3660 SoC 4 * 5 * Copyright (C) 2016, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/hi3660-clock.h> 10 11/ { 12 compatible = "hisilicon,hi3660"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 psci { 18 compatible = "arm,psci-0.2"; 19 method = "smc"; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 core2 { 35 cpu = <&cpu2>; 36 }; 37 core3 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 device_type = "cpu"; 60 reg = <0x0 0x0>; 61 enable-method = "psci"; 62 next-level-cache = <&A53_L2>; 63 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 64 capacity-dmips-mhz = <592>; 65 }; 66 67 cpu1: cpu@1 { 68 compatible = "arm,cortex-a53", "arm,armv8"; 69 device_type = "cpu"; 70 reg = <0x0 0x1>; 71 enable-method = "psci"; 72 next-level-cache = <&A53_L2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 74 capacity-dmips-mhz = <592>; 75 }; 76 77 cpu2: cpu@2 { 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 device_type = "cpu"; 80 reg = <0x0 0x2>; 81 enable-method = "psci"; 82 next-level-cache = <&A53_L2>; 83 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 84 capacity-dmips-mhz = <592>; 85 }; 86 87 cpu3: cpu@3 { 88 compatible = "arm,cortex-a53", "arm,armv8"; 89 device_type = "cpu"; 90 reg = <0x0 0x3>; 91 enable-method = "psci"; 92 next-level-cache = <&A53_L2>; 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 94 capacity-dmips-mhz = <592>; 95 }; 96 97 cpu4: cpu@100 { 98 compatible = "arm,cortex-a73", "arm,armv8"; 99 device_type = "cpu"; 100 reg = <0x0 0x100>; 101 enable-method = "psci"; 102 next-level-cache = <&A73_L2>; 103 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 104 capacity-dmips-mhz = <1024>; 105 }; 106 107 cpu5: cpu@101 { 108 compatible = "arm,cortex-a73", "arm,armv8"; 109 device_type = "cpu"; 110 reg = <0x0 0x101>; 111 enable-method = "psci"; 112 next-level-cache = <&A73_L2>; 113 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 114 capacity-dmips-mhz = <1024>; 115 }; 116 117 cpu6: cpu@102 { 118 compatible = "arm,cortex-a73", "arm,armv8"; 119 device_type = "cpu"; 120 reg = <0x0 0x102>; 121 enable-method = "psci"; 122 next-level-cache = <&A73_L2>; 123 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 124 capacity-dmips-mhz = <1024>; 125 }; 126 127 cpu7: cpu@103 { 128 compatible = "arm,cortex-a73", "arm,armv8"; 129 device_type = "cpu"; 130 reg = <0x0 0x103>; 131 enable-method = "psci"; 132 next-level-cache = <&A73_L2>; 133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 134 capacity-dmips-mhz = <1024>; 135 }; 136 137 idle-states { 138 entry-method = "psci"; 139 140 CPU_SLEEP: cpu-sleep { 141 compatible = "arm,idle-state"; 142 local-timer-stop; 143 arm,psci-suspend-param = <0x0010000>; 144 entry-latency-us = <40>; 145 exit-latency-us = <70>; 146 min-residency-us = <3000>; 147 }; 148 149 CLUSTER_SLEEP_0: cluster-sleep-0 { 150 compatible = "arm,idle-state"; 151 local-timer-stop; 152 arm,psci-suspend-param = <0x1010000>; 153 entry-latency-us = <500>; 154 exit-latency-us = <5000>; 155 min-residency-us = <20000>; 156 }; 157 158 CLUSTER_SLEEP_1: cluster-sleep-1 { 159 compatible = "arm,idle-state"; 160 local-timer-stop; 161 arm,psci-suspend-param = <0x1010000>; 162 entry-latency-us = <1000>; 163 exit-latency-us = <5000>; 164 min-residency-us = <20000>; 165 }; 166 }; 167 168 A53_L2: l2-cache0 { 169 compatible = "cache"; 170 }; 171 172 A73_L2: l2-cache1 { 173 compatible = "cache"; 174 }; 175 }; 176 177 gic: interrupt-controller@e82b0000 { 178 compatible = "arm,gic-400"; 179 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 180 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 181 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 182 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 183 #address-cells = <0>; 184 #interrupt-cells = <3>; 185 interrupt-controller; 186 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 187 IRQ_TYPE_LEVEL_HIGH)>; 188 }; 189 190 a53-pmu { 191 compatible = "arm,cortex-a53-pmu"; 192 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 196 interrupt-affinity = <&cpu0>, 197 <&cpu1>, 198 <&cpu2>, 199 <&cpu3>; 200 }; 201 202 a73-pmu { 203 compatible = "arm,cortex-a73-pmu"; 204 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-affinity = <&cpu4>, 209 <&cpu5>, 210 <&cpu6>, 211 <&cpu7>; 212 }; 213 214 timer { 215 compatible = "arm,armv8-timer"; 216 interrupt-parent = <&gic>; 217 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 218 IRQ_TYPE_LEVEL_LOW)>, 219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 220 IRQ_TYPE_LEVEL_LOW)>, 221 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 222 IRQ_TYPE_LEVEL_LOW)>, 223 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 224 IRQ_TYPE_LEVEL_LOW)>; 225 }; 226 227 soc { 228 compatible = "simple-bus"; 229 #address-cells = <2>; 230 #size-cells = <2>; 231 ranges; 232 233 crg_ctrl: crg_ctrl@fff35000 { 234 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 235 reg = <0x0 0xfff35000 0x0 0x1000>; 236 #clock-cells = <1>; 237 }; 238 239 crg_rst: crg_rst_controller { 240 compatible = "hisilicon,hi3660-reset"; 241 #reset-cells = <2>; 242 hisi,rst-syscon = <&crg_ctrl>; 243 }; 244 245 246 pctrl: pctrl@e8a09000 { 247 compatible = "hisilicon,hi3660-pctrl", "syscon"; 248 reg = <0x0 0xe8a09000 0x0 0x2000>; 249 #clock-cells = <1>; 250 }; 251 252 pmuctrl: crg_ctrl@fff34000 { 253 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 254 reg = <0x0 0xfff34000 0x0 0x1000>; 255 #clock-cells = <1>; 256 }; 257 258 sctrl: sctrl@fff0a000 { 259 compatible = "hisilicon,hi3660-sctrl", "syscon"; 260 reg = <0x0 0xfff0a000 0x0 0x1000>; 261 #clock-cells = <1>; 262 }; 263 264 iomcu: iomcu@ffd7e000 { 265 compatible = "hisilicon,hi3660-iomcu", "syscon"; 266 reg = <0x0 0xffd7e000 0x0 0x1000>; 267 #clock-cells = <1>; 268 269 }; 270 271 iomcu_rst: reset { 272 compatible = "hisilicon,hi3660-reset"; 273 hisi,rst-syscon = <&iomcu>; 274 #reset-cells = <2>; 275 }; 276 277 mailbox: mailbox@e896b000 { 278 compatible = "hisilicon,hi3660-mbox"; 279 reg = <0x0 0xe896b000 0x0 0x1000>; 280 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 282 #mbox-cells = <3>; 283 }; 284 285 dual_timer0: timer@fff14000 { 286 compatible = "arm,sp804", "arm,primecell"; 287 reg = <0x0 0xfff14000 0x0 0x1000>; 288 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&crg_ctrl HI3660_OSC32K>, 291 <&crg_ctrl HI3660_OSC32K>, 292 <&crg_ctrl HI3660_OSC32K>; 293 clock-names = "timer1", "timer2", "apb_pclk"; 294 }; 295 296 i2c0: i2c@ffd71000 { 297 compatible = "snps,designware-i2c"; 298 reg = <0x0 0xffd71000 0x0 0x1000>; 299 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 clock-frequency = <400000>; 303 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 304 resets = <&iomcu_rst 0x20 3>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 307 status = "disabled"; 308 }; 309 310 i2c1: i2c@ffd72000 { 311 compatible = "snps,designware-i2c"; 312 reg = <0x0 0xffd72000 0x0 0x1000>; 313 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 clock-frequency = <400000>; 317 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 318 resets = <&iomcu_rst 0x20 4>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 321 status = "disabled"; 322 }; 323 324 i2c3: i2c@fdf0c000 { 325 compatible = "snps,designware-i2c"; 326 reg = <0x0 0xfdf0c000 0x0 0x1000>; 327 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 clock-frequency = <400000>; 331 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 332 resets = <&crg_rst 0x78 7>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 335 status = "disabled"; 336 }; 337 338 i2c7: i2c@fdf0b000 { 339 compatible = "snps,designware-i2c"; 340 reg = <0x0 0xfdf0b000 0x0 0x1000>; 341 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 clock-frequency = <400000>; 345 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 346 resets = <&crg_rst 0x60 14>; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 349 status = "disabled"; 350 }; 351 352 uart0: serial@fdf02000 { 353 compatible = "arm,pl011", "arm,primecell"; 354 reg = <0x0 0xfdf02000 0x0 0x1000>; 355 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 357 <&crg_ctrl HI3660_PCLK>; 358 clock-names = "uartclk", "apb_pclk"; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 361 status = "disabled"; 362 }; 363 364 uart1: serial@fdf00000 { 365 compatible = "arm,pl011", "arm,primecell"; 366 reg = <0x0 0xfdf00000 0x0 0x1000>; 367 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 369 <&crg_ctrl HI3660_CLK_GATE_UART1>; 370 clock-names = "uartclk", "apb_pclk"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 373 status = "disabled"; 374 }; 375 376 uart2: serial@fdf03000 { 377 compatible = "arm,pl011", "arm,primecell"; 378 reg = <0x0 0xfdf03000 0x0 0x1000>; 379 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 380 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 381 <&crg_ctrl HI3660_PCLK>; 382 clock-names = "uartclk", "apb_pclk"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 385 status = "disabled"; 386 }; 387 388 uart3: serial@ffd74000 { 389 compatible = "arm,pl011", "arm,primecell"; 390 reg = <0x0 0xffd74000 0x0 0x1000>; 391 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 393 <&crg_ctrl HI3660_PCLK>; 394 clock-names = "uartclk", "apb_pclk"; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 397 status = "disabled"; 398 }; 399 400 uart4: serial@fdf01000 { 401 compatible = "arm,pl011", "arm,primecell"; 402 reg = <0x0 0xfdf01000 0x0 0x1000>; 403 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 405 <&crg_ctrl HI3660_CLK_GATE_UART4>; 406 clock-names = "uartclk", "apb_pclk"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 409 status = "disabled"; 410 }; 411 412 uart5: serial@fdf05000 { 413 compatible = "arm,pl011", "arm,primecell"; 414 reg = <0x0 0xfdf05000 0x0 0x1000>; 415 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 417 <&crg_ctrl HI3660_CLK_GATE_UART5>; 418 clock-names = "uartclk", "apb_pclk"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 421 status = "disabled"; 422 }; 423 424 uart6: serial@fff32000 { 425 compatible = "arm,pl011", "arm,primecell"; 426 reg = <0x0 0xfff32000 0x0 0x1000>; 427 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&crg_ctrl HI3660_CLK_UART6>, 429 <&crg_ctrl HI3660_PCLK>; 430 clock-names = "uartclk", "apb_pclk"; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 433 status = "disabled"; 434 }; 435 436 dma0: dma@fdf30000 { 437 compatible = "hisilicon,k3-dma-1.0"; 438 reg = <0x0 0xfdf30000 0x0 0x1000>; 439 #dma-cells = <1>; 440 dma-channels = <16>; 441 dma-requests = <32>; 442 dma-min-chan = <1>; 443 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 445 dma-no-cci; 446 dma-type = "hi3660_dma"; 447 }; 448 449 rtc0: rtc@fff04000 { 450 compatible = "arm,pl031", "arm,primecell"; 451 reg = <0x0 0Xfff04000 0x0 0x1000>; 452 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&crg_ctrl HI3660_PCLK>; 454 clock-names = "apb_pclk"; 455 }; 456 457 gpio0: gpio@e8a0b000 { 458 compatible = "arm,pl061", "arm,primecell"; 459 reg = <0 0xe8a0b000 0 0x1000>; 460 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 461 gpio-controller; 462 #gpio-cells = <2>; 463 gpio-ranges = <&pmx0 1 0 7>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 467 clock-names = "apb_pclk"; 468 }; 469 470 gpio1: gpio@e8a0c000 { 471 compatible = "arm,pl061", "arm,primecell"; 472 reg = <0 0xe8a0c000 0 0x1000>; 473 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 474 gpio-controller; 475 #gpio-cells = <2>; 476 gpio-ranges = <&pmx0 1 7 7>; 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 480 clock-names = "apb_pclk"; 481 }; 482 483 gpio2: gpio@e8a0d000 { 484 compatible = "arm,pl061", "arm,primecell"; 485 reg = <0 0xe8a0d000 0 0x1000>; 486 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 487 gpio-controller; 488 #gpio-cells = <2>; 489 gpio-ranges = <&pmx0 0 14 8>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 493 clock-names = "apb_pclk"; 494 }; 495 496 gpio3: gpio@e8a0e000 { 497 compatible = "arm,pl061", "arm,primecell"; 498 reg = <0 0xe8a0e000 0 0x1000>; 499 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 500 gpio-controller; 501 #gpio-cells = <2>; 502 gpio-ranges = <&pmx0 0 22 8>; 503 interrupt-controller; 504 #interrupt-cells = <2>; 505 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 506 clock-names = "apb_pclk"; 507 }; 508 509 gpio4: gpio@e8a0f000 { 510 compatible = "arm,pl061", "arm,primecell"; 511 reg = <0 0xe8a0f000 0 0x1000>; 512 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 513 gpio-controller; 514 #gpio-cells = <2>; 515 gpio-ranges = <&pmx0 0 30 8>; 516 interrupt-controller; 517 #interrupt-cells = <2>; 518 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 519 clock-names = "apb_pclk"; 520 }; 521 522 gpio5: gpio@e8a10000 { 523 compatible = "arm,pl061", "arm,primecell"; 524 reg = <0 0xe8a10000 0 0x1000>; 525 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 526 gpio-controller; 527 #gpio-cells = <2>; 528 gpio-ranges = <&pmx0 0 38 8>; 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 532 clock-names = "apb_pclk"; 533 }; 534 535 gpio6: gpio@e8a11000 { 536 compatible = "arm,pl061", "arm,primecell"; 537 reg = <0 0xe8a11000 0 0x1000>; 538 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 539 gpio-controller; 540 #gpio-cells = <2>; 541 gpio-ranges = <&pmx0 0 46 8>; 542 interrupt-controller; 543 #interrupt-cells = <2>; 544 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 545 clock-names = "apb_pclk"; 546 }; 547 548 gpio7: gpio@e8a12000 { 549 compatible = "arm,pl061", "arm,primecell"; 550 reg = <0 0xe8a12000 0 0x1000>; 551 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 552 gpio-controller; 553 #gpio-cells = <2>; 554 gpio-ranges = <&pmx0 0 54 8>; 555 interrupt-controller; 556 #interrupt-cells = <2>; 557 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 558 clock-names = "apb_pclk"; 559 }; 560 561 gpio8: gpio@e8a13000 { 562 compatible = "arm,pl061", "arm,primecell"; 563 reg = <0 0xe8a13000 0 0x1000>; 564 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 565 gpio-controller; 566 #gpio-cells = <2>; 567 gpio-ranges = <&pmx0 0 62 8>; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 571 clock-names = "apb_pclk"; 572 }; 573 574 gpio9: gpio@e8a14000 { 575 compatible = "arm,pl061", "arm,primecell"; 576 reg = <0 0xe8a14000 0 0x1000>; 577 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 578 gpio-controller; 579 #gpio-cells = <2>; 580 gpio-ranges = <&pmx0 0 70 8>; 581 interrupt-controller; 582 #interrupt-cells = <2>; 583 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 584 clock-names = "apb_pclk"; 585 }; 586 587 gpio10: gpio@e8a15000 { 588 compatible = "arm,pl061", "arm,primecell"; 589 reg = <0 0xe8a15000 0 0x1000>; 590 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 591 gpio-controller; 592 #gpio-cells = <2>; 593 gpio-ranges = <&pmx0 0 78 8>; 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 597 clock-names = "apb_pclk"; 598 }; 599 600 gpio11: gpio@e8a16000 { 601 compatible = "arm,pl061", "arm,primecell"; 602 reg = <0 0xe8a16000 0 0x1000>; 603 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 604 gpio-controller; 605 #gpio-cells = <2>; 606 gpio-ranges = <&pmx0 0 86 8>; 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 610 clock-names = "apb_pclk"; 611 }; 612 613 gpio12: gpio@e8a17000 { 614 compatible = "arm,pl061", "arm,primecell"; 615 reg = <0 0xe8a17000 0 0x1000>; 616 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 617 gpio-controller; 618 #gpio-cells = <2>; 619 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 623 clock-names = "apb_pclk"; 624 }; 625 626 gpio13: gpio@e8a18000 { 627 compatible = "arm,pl061", "arm,primecell"; 628 reg = <0 0xe8a18000 0 0x1000>; 629 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 630 gpio-controller; 631 #gpio-cells = <2>; 632 gpio-ranges = <&pmx0 0 102 8>; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 636 clock-names = "apb_pclk"; 637 }; 638 639 gpio14: gpio@e8a19000 { 640 compatible = "arm,pl061", "arm,primecell"; 641 reg = <0 0xe8a19000 0 0x1000>; 642 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 643 gpio-controller; 644 #gpio-cells = <2>; 645 gpio-ranges = <&pmx0 0 110 8>; 646 interrupt-controller; 647 #interrupt-cells = <2>; 648 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 649 clock-names = "apb_pclk"; 650 }; 651 652 gpio15: gpio@e8a1a000 { 653 compatible = "arm,pl061", "arm,primecell"; 654 reg = <0 0xe8a1a000 0 0x1000>; 655 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 656 gpio-controller; 657 #gpio-cells = <2>; 658 gpio-ranges = <&pmx0 0 118 6>; 659 interrupt-controller; 660 #interrupt-cells = <2>; 661 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 662 clock-names = "apb_pclk"; 663 }; 664 665 gpio16: gpio@e8a1b000 { 666 compatible = "arm,pl061", "arm,primecell"; 667 reg = <0 0xe8a1b000 0 0x1000>; 668 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 669 gpio-controller; 670 #gpio-cells = <2>; 671 interrupt-controller; 672 #interrupt-cells = <2>; 673 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 674 clock-names = "apb_pclk"; 675 }; 676 677 gpio17: gpio@e8a1c000 { 678 compatible = "arm,pl061", "arm,primecell"; 679 reg = <0 0xe8a1c000 0 0x1000>; 680 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 681 gpio-controller; 682 #gpio-cells = <2>; 683 interrupt-controller; 684 #interrupt-cells = <2>; 685 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 686 clock-names = "apb_pclk"; 687 }; 688 689 gpio18: gpio@ff3b4000 { 690 compatible = "arm,pl061", "arm,primecell"; 691 reg = <0 0xff3b4000 0 0x1000>; 692 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 693 gpio-controller; 694 #gpio-cells = <2>; 695 gpio-ranges = <&pmx2 0 0 8>; 696 interrupt-controller; 697 #interrupt-cells = <2>; 698 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 699 clock-names = "apb_pclk"; 700 }; 701 702 gpio19: gpio@ff3b5000 { 703 compatible = "arm,pl061", "arm,primecell"; 704 reg = <0 0xff3b5000 0 0x1000>; 705 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 706 gpio-controller; 707 #gpio-cells = <2>; 708 gpio-ranges = <&pmx2 0 8 4>; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 712 clock-names = "apb_pclk"; 713 }; 714 715 gpio20: gpio@e8a1f000 { 716 compatible = "arm,pl061", "arm,primecell"; 717 reg = <0 0xe8a1f000 0 0x1000>; 718 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 719 gpio-controller; 720 #gpio-cells = <2>; 721 gpio-ranges = <&pmx1 0 0 6>; 722 interrupt-controller; 723 #interrupt-cells = <2>; 724 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 725 clock-names = "apb_pclk"; 726 }; 727 728 gpio21: gpio@e8a20000 { 729 compatible = "arm,pl061", "arm,primecell"; 730 reg = <0 0xe8a20000 0 0x1000>; 731 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 732 gpio-controller; 733 #gpio-cells = <2>; 734 interrupt-controller; 735 #interrupt-cells = <2>; 736 gpio-ranges = <&pmx3 0 0 6>; 737 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 738 clock-names = "apb_pclk"; 739 }; 740 741 gpio22: gpio@fff0b000 { 742 compatible = "arm,pl061", "arm,primecell"; 743 reg = <0 0xfff0b000 0 0x1000>; 744 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 745 gpio-controller; 746 #gpio-cells = <2>; 747 /* GPIO176 */ 748 gpio-ranges = <&pmx4 2 0 6>; 749 interrupt-controller; 750 #interrupt-cells = <2>; 751 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 752 clock-names = "apb_pclk"; 753 }; 754 755 gpio23: gpio@fff0c000 { 756 compatible = "arm,pl061", "arm,primecell"; 757 reg = <0 0xfff0c000 0 0x1000>; 758 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 759 gpio-controller; 760 #gpio-cells = <2>; 761 /* GPIO184 */ 762 gpio-ranges = <&pmx4 0 6 7>; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 766 clock-names = "apb_pclk"; 767 }; 768 769 gpio24: gpio@fff0d000 { 770 compatible = "arm,pl061", "arm,primecell"; 771 reg = <0 0xfff0d000 0 0x1000>; 772 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 773 gpio-controller; 774 #gpio-cells = <2>; 775 /* GPIO192 */ 776 gpio-ranges = <&pmx4 0 13 8>; 777 interrupt-controller; 778 #interrupt-cells = <2>; 779 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 780 clock-names = "apb_pclk"; 781 }; 782 783 gpio25: gpio@fff0e000 { 784 compatible = "arm,pl061", "arm,primecell"; 785 reg = <0 0xfff0e000 0 0x1000>; 786 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 787 gpio-controller; 788 #gpio-cells = <2>; 789 /* GPIO200 */ 790 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 791 interrupt-controller; 792 #interrupt-cells = <2>; 793 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 794 clock-names = "apb_pclk"; 795 }; 796 797 gpio26: gpio@fff0f000 { 798 compatible = "arm,pl061", "arm,primecell"; 799 reg = <0 0xfff0f000 0 0x1000>; 800 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 801 gpio-controller; 802 #gpio-cells = <2>; 803 /* GPIO208 */ 804 gpio-ranges = <&pmx4 0 28 8>; 805 interrupt-controller; 806 #interrupt-cells = <2>; 807 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 808 clock-names = "apb_pclk"; 809 }; 810 811 gpio27: gpio@fff10000 { 812 compatible = "arm,pl061", "arm,primecell"; 813 reg = <0 0xfff10000 0 0x1000>; 814 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 815 gpio-controller; 816 #gpio-cells = <2>; 817 /* GPIO216 */ 818 gpio-ranges = <&pmx4 0 36 6>; 819 interrupt-controller; 820 #interrupt-cells = <2>; 821 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 822 clock-names = "apb_pclk"; 823 }; 824 825 gpio28: gpio@fff1d000 { 826 compatible = "arm,pl061", "arm,primecell"; 827 reg = <0 0xfff1d000 0 0x1000>; 828 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 829 gpio-controller; 830 #gpio-cells = <2>; 831 interrupt-controller; 832 #interrupt-cells = <2>; 833 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 834 clock-names = "apb_pclk"; 835 }; 836 837 spi2: spi@ffd68000 { 838 compatible = "arm,pl022", "arm,primecell"; 839 reg = <0x0 0xffd68000 0x0 0x1000>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 844 clock-names = "apb_pclk"; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&spi2_pmx_func>; 847 num-cs = <1>; 848 cs-gpios = <&gpio27 2 0>; 849 status = "disabled"; 850 }; 851 852 spi3: spi@ff3b3000 { 853 compatible = "arm,pl022", "arm,primecell"; 854 reg = <0x0 0xff3b3000 0x0 0x1000>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 859 clock-names = "apb_pclk"; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&spi3_pmx_func>; 862 num-cs = <1>; 863 cs-gpios = <&gpio18 5 0>; 864 status = "disabled"; 865 }; 866 867 pcie@f4000000 { 868 compatible = "hisilicon,kirin960-pcie"; 869 reg = <0x0 0xf4000000 0x0 0x1000>, 870 <0x0 0xff3fe000 0x0 0x1000>, 871 <0x0 0xf3f20000 0x0 0x40000>, 872 <0x0 0xf5000000 0x0 0x2000>; 873 reg-names = "dbi", "apb", "phy", "config"; 874 bus-range = <0x0 0x1>; 875 #address-cells = <3>; 876 #size-cells = <2>; 877 device_type = "pci"; 878 ranges = <0x02000000 0x0 0x00000000 879 0x0 0xf6000000 880 0x0 0x02000000>; 881 num-lanes = <1>; 882 #interrupt-cells = <1>; 883 interrupt-map-mask = <0xf800 0 0 7>; 884 interrupt-map = <0x0 0 0 1 885 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 886 <0x0 0 0 2 887 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 888 <0x0 0 0 3 889 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 890 <0x0 0 0 4 891 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 893 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 894 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 895 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 896 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 897 clock-names = "pcie_phy_ref", "pcie_aux", 898 "pcie_apb_phy", "pcie_apb_sys", 899 "pcie_aclk"; 900 reset-gpios = <&gpio11 1 0 >; 901 }; 902 903 /* SD */ 904 dwmmc1: dwmmc1@ff37f000 { 905 #address-cells = <1>; 906 #size-cells = <0>; 907 cd-inverted; 908 compatible = "hisilicon,hi3660-dw-mshc"; 909 bus-width = <0x4>; 910 disable-wp; 911 cap-sd-highspeed; 912 supports-highspeed; 913 card-detect-delay = <200>; 914 reg = <0x0 0xff37f000 0x0 0x1000>; 915 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 917 <&crg_ctrl HI3660_HCLK_GATE_SD>; 918 clock-names = "ciu", "biu"; 919 clock-frequency = <3200000>; 920 resets = <&crg_rst 0x94 18>; 921 reset-names = "reset"; 922 cd-gpios = <&gpio25 3 0>; 923 hisilicon,peripheral-syscon = <&sctrl>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&sd_pmx_func 926 &sd_clk_cfg_func 927 &sd_cfg_func>; 928 sd-uhs-sdr12; 929 sd-uhs-sdr25; 930 sd-uhs-sdr50; 931 sd-uhs-sdr104; 932 status = "disabled"; 933 934 slot@0 { 935 reg = <0x0>; 936 bus-width = <4>; 937 disable-wp; 938 }; 939 }; 940 941 /* SDIO */ 942 dwmmc2: dwmmc2@ff3ff000 { 943 compatible = "hisilicon,hi3660-dw-mshc"; 944 reg = <0x0 0xff3ff000 0x0 0x1000>; 945 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 947 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 948 clock-names = "ciu", "biu"; 949 resets = <&crg_rst 0x94 20>; 950 reset-names = "reset"; 951 card-detect-delay = <200>; 952 supports-highspeed; 953 keep-power-in-suspend; 954 pinctrl-names = "default"; 955 pinctrl-0 = <&sdio_pmx_func 956 &sdio_clk_cfg_func 957 &sdio_cfg_func>; 958 status = "disabled"; 959 }; 960 961 watchdog0: watchdog@e8a06000 { 962 compatible = "arm,sp805-wdt", "arm,primecell"; 963 reg = <0x0 0xe8a06000 0x0 0x1000>; 964 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&crg_ctrl HI3660_OSC32K>; 966 clock-names = "apb_pclk"; 967 }; 968 969 watchdog1: watchdog@e8a07000 { 970 compatible = "arm,sp805-wdt", "arm,primecell"; 971 reg = <0x0 0xe8a07000 0x0 0x1000>; 972 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&crg_ctrl HI3660_OSC32K>; 974 clock-names = "apb_pclk"; 975 }; 976 977 tsensor: tsensor@fff30000 { 978 compatible = "hisilicon,hi3660-tsensor"; 979 reg = <0x0 0xfff30000 0x0 0x1000>; 980 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 981 #thermal-sensor-cells = <1>; 982 }; 983 }; 984}; 985