1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3660 SoC 4 * 5 * Copyright (C) 2016, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/hi3660-clock.h> 10 11/ { 12 compatible = "hisilicon,hi3660"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 psci { 18 compatible = "arm,psci-0.2"; 19 method = "smc"; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 core2 { 35 cpu = <&cpu2>; 36 }; 37 core3 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 device_type = "cpu"; 60 reg = <0x0 0x0>; 61 enable-method = "psci"; 62 next-level-cache = <&A53_L2>; 63 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 64 capacity-dmips-mhz = <592>; 65 }; 66 67 cpu1: cpu@1 { 68 compatible = "arm,cortex-a53", "arm,armv8"; 69 device_type = "cpu"; 70 reg = <0x0 0x1>; 71 enable-method = "psci"; 72 next-level-cache = <&A53_L2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 74 capacity-dmips-mhz = <592>; 75 }; 76 77 cpu2: cpu@2 { 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 device_type = "cpu"; 80 reg = <0x0 0x2>; 81 enable-method = "psci"; 82 next-level-cache = <&A53_L2>; 83 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 84 capacity-dmips-mhz = <592>; 85 }; 86 87 cpu3: cpu@3 { 88 compatible = "arm,cortex-a53", "arm,armv8"; 89 device_type = "cpu"; 90 reg = <0x0 0x3>; 91 enable-method = "psci"; 92 next-level-cache = <&A53_L2>; 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 94 capacity-dmips-mhz = <592>; 95 }; 96 97 cpu4: cpu@100 { 98 compatible = "arm,cortex-a73", "arm,armv8"; 99 device_type = "cpu"; 100 reg = <0x0 0x100>; 101 enable-method = "psci"; 102 next-level-cache = <&A73_L2>; 103 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 104 capacity-dmips-mhz = <1024>; 105 }; 106 107 cpu5: cpu@101 { 108 compatible = "arm,cortex-a73", "arm,armv8"; 109 device_type = "cpu"; 110 reg = <0x0 0x101>; 111 enable-method = "psci"; 112 next-level-cache = <&A73_L2>; 113 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 114 capacity-dmips-mhz = <1024>; 115 }; 116 117 cpu6: cpu@102 { 118 compatible = "arm,cortex-a73", "arm,armv8"; 119 device_type = "cpu"; 120 reg = <0x0 0x102>; 121 enable-method = "psci"; 122 next-level-cache = <&A73_L2>; 123 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 124 capacity-dmips-mhz = <1024>; 125 }; 126 127 cpu7: cpu@103 { 128 compatible = "arm,cortex-a73", "arm,armv8"; 129 device_type = "cpu"; 130 reg = <0x0 0x103>; 131 enable-method = "psci"; 132 next-level-cache = <&A73_L2>; 133 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; 134 capacity-dmips-mhz = <1024>; 135 }; 136 137 idle-states { 138 entry-method = "psci"; 139 140 CPU_SLEEP: cpu-sleep { 141 compatible = "arm,idle-state"; 142 local-timer-stop; 143 arm,psci-suspend-param = <0x0010000>; 144 entry-latency-us = <40>; 145 exit-latency-us = <70>; 146 min-residency-us = <3000>; 147 }; 148 149 CLUSTER_SLEEP_0: cluster-sleep-0 { 150 compatible = "arm,idle-state"; 151 local-timer-stop; 152 arm,psci-suspend-param = <0x1010000>; 153 entry-latency-us = <500>; 154 exit-latency-us = <5000>; 155 min-residency-us = <20000>; 156 }; 157 158 CLUSTER_SLEEP_1: cluster-sleep-1 { 159 compatible = "arm,idle-state"; 160 local-timer-stop; 161 arm,psci-suspend-param = <0x1010000>; 162 entry-latency-us = <1000>; 163 exit-latency-us = <5000>; 164 min-residency-us = <20000>; 165 }; 166 }; 167 168 A53_L2: l2-cache0 { 169 compatible = "cache"; 170 }; 171 172 A73_L2: l2-cache1 { 173 compatible = "cache"; 174 }; 175 }; 176 177 gic: interrupt-controller@e82b0000 { 178 compatible = "arm,gic-400"; 179 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 180 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 181 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 182 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 183 #address-cells = <0>; 184 #interrupt-cells = <3>; 185 interrupt-controller; 186 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 187 IRQ_TYPE_LEVEL_HIGH)>; 188 }; 189 190 a53-pmu { 191 compatible = "arm,cortex-a53-pmu"; 192 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 196 interrupt-affinity = <&cpu0>, 197 <&cpu1>, 198 <&cpu2>, 199 <&cpu3>; 200 }; 201 202 a73-pmu { 203 compatible = "arm,cortex-a73-pmu"; 204 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-affinity = <&cpu4>, 209 <&cpu5>, 210 <&cpu6>, 211 <&cpu7>; 212 }; 213 214 timer { 215 compatible = "arm,armv8-timer"; 216 interrupt-parent = <&gic>; 217 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 218 IRQ_TYPE_LEVEL_LOW)>, 219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 220 IRQ_TYPE_LEVEL_LOW)>, 221 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 222 IRQ_TYPE_LEVEL_LOW)>, 223 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 224 IRQ_TYPE_LEVEL_LOW)>; 225 }; 226 227 soc { 228 compatible = "simple-bus"; 229 #address-cells = <2>; 230 #size-cells = <2>; 231 ranges; 232 233 crg_ctrl: crg_ctrl@fff35000 { 234 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 235 reg = <0x0 0xfff35000 0x0 0x1000>; 236 #clock-cells = <1>; 237 }; 238 239 crg_rst: crg_rst_controller { 240 compatible = "hisilicon,hi3660-reset"; 241 #reset-cells = <2>; 242 hisi,rst-syscon = <&crg_ctrl>; 243 }; 244 245 246 pctrl: pctrl@e8a09000 { 247 compatible = "hisilicon,hi3660-pctrl", "syscon"; 248 reg = <0x0 0xe8a09000 0x0 0x2000>; 249 #clock-cells = <1>; 250 }; 251 252 pmuctrl: crg_ctrl@fff34000 { 253 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 254 reg = <0x0 0xfff34000 0x0 0x1000>; 255 #clock-cells = <1>; 256 }; 257 258 sctrl: sctrl@fff0a000 { 259 compatible = "hisilicon,hi3660-sctrl", "syscon"; 260 reg = <0x0 0xfff0a000 0x0 0x1000>; 261 #clock-cells = <1>; 262 }; 263 264 iomcu: iomcu@ffd7e000 { 265 compatible = "hisilicon,hi3660-iomcu", "syscon"; 266 reg = <0x0 0xffd7e000 0x0 0x1000>; 267 #clock-cells = <1>; 268 269 }; 270 271 iomcu_rst: reset { 272 compatible = "hisilicon,hi3660-reset"; 273 hisi,rst-syscon = <&iomcu>; 274 #reset-cells = <2>; 275 }; 276 277 dual_timer0: timer@fff14000 { 278 compatible = "arm,sp804", "arm,primecell"; 279 reg = <0x0 0xfff14000 0x0 0x1000>; 280 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&crg_ctrl HI3660_OSC32K>, 283 <&crg_ctrl HI3660_OSC32K>, 284 <&crg_ctrl HI3660_OSC32K>; 285 clock-names = "timer1", "timer2", "apb_pclk"; 286 }; 287 288 i2c0: i2c@ffd71000 { 289 compatible = "snps,designware-i2c"; 290 reg = <0x0 0xffd71000 0x0 0x1000>; 291 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 clock-frequency = <400000>; 295 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 296 resets = <&iomcu_rst 0x20 3>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 299 status = "disabled"; 300 }; 301 302 i2c1: i2c@ffd72000 { 303 compatible = "snps,designware-i2c"; 304 reg = <0x0 0xffd72000 0x0 0x1000>; 305 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 clock-frequency = <400000>; 309 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 310 resets = <&iomcu_rst 0x20 4>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 313 status = "disabled"; 314 }; 315 316 i2c3: i2c@fdf0c000 { 317 compatible = "snps,designware-i2c"; 318 reg = <0x0 0xfdf0c000 0x0 0x1000>; 319 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 clock-frequency = <400000>; 323 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 324 resets = <&crg_rst 0x78 7>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 327 status = "disabled"; 328 }; 329 330 i2c7: i2c@fdf0b000 { 331 compatible = "snps,designware-i2c"; 332 reg = <0x0 0xfdf0b000 0x0 0x1000>; 333 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 clock-frequency = <400000>; 337 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 338 resets = <&crg_rst 0x60 14>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 341 status = "disabled"; 342 }; 343 344 uart0: serial@fdf02000 { 345 compatible = "arm,pl011", "arm,primecell"; 346 reg = <0x0 0xfdf02000 0x0 0x1000>; 347 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 349 <&crg_ctrl HI3660_PCLK>; 350 clock-names = "uartclk", "apb_pclk"; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 353 status = "disabled"; 354 }; 355 356 uart1: serial@fdf00000 { 357 compatible = "arm,pl011", "arm,primecell"; 358 reg = <0x0 0xfdf00000 0x0 0x1000>; 359 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 361 <&crg_ctrl HI3660_CLK_GATE_UART1>; 362 clock-names = "uartclk", "apb_pclk"; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 365 status = "disabled"; 366 }; 367 368 uart2: serial@fdf03000 { 369 compatible = "arm,pl011", "arm,primecell"; 370 reg = <0x0 0xfdf03000 0x0 0x1000>; 371 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 373 <&crg_ctrl HI3660_PCLK>; 374 clock-names = "uartclk", "apb_pclk"; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 377 status = "disabled"; 378 }; 379 380 uart3: serial@ffd74000 { 381 compatible = "arm,pl011", "arm,primecell"; 382 reg = <0x0 0xffd74000 0x0 0x1000>; 383 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 385 <&crg_ctrl HI3660_PCLK>; 386 clock-names = "uartclk", "apb_pclk"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 389 status = "disabled"; 390 }; 391 392 uart4: serial@fdf01000 { 393 compatible = "arm,pl011", "arm,primecell"; 394 reg = <0x0 0xfdf01000 0x0 0x1000>; 395 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 397 <&crg_ctrl HI3660_CLK_GATE_UART4>; 398 clock-names = "uartclk", "apb_pclk"; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 401 status = "disabled"; 402 }; 403 404 uart5: serial@fdf05000 { 405 compatible = "arm,pl011", "arm,primecell"; 406 reg = <0x0 0xfdf05000 0x0 0x1000>; 407 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 409 <&crg_ctrl HI3660_CLK_GATE_UART5>; 410 clock-names = "uartclk", "apb_pclk"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 413 status = "disabled"; 414 }; 415 416 uart6: serial@fff32000 { 417 compatible = "arm,pl011", "arm,primecell"; 418 reg = <0x0 0xfff32000 0x0 0x1000>; 419 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&crg_ctrl HI3660_CLK_UART6>, 421 <&crg_ctrl HI3660_PCLK>; 422 clock-names = "uartclk", "apb_pclk"; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 425 status = "disabled"; 426 }; 427 428 dma0: dma@fdf30000 { 429 compatible = "hisilicon,k3-dma-1.0"; 430 reg = <0x0 0xfdf30000 0x0 0x1000>; 431 #dma-cells = <1>; 432 dma-channels = <16>; 433 dma-requests = <32>; 434 dma-min-chan = <1>; 435 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 437 dma-no-cci; 438 dma-type = "hi3660_dma"; 439 }; 440 441 rtc0: rtc@fff04000 { 442 compatible = "arm,pl031", "arm,primecell"; 443 reg = <0x0 0Xfff04000 0x0 0x1000>; 444 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&crg_ctrl HI3660_PCLK>; 446 clock-names = "apb_pclk"; 447 }; 448 449 gpio0: gpio@e8a0b000 { 450 compatible = "arm,pl061", "arm,primecell"; 451 reg = <0 0xe8a0b000 0 0x1000>; 452 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 453 gpio-controller; 454 #gpio-cells = <2>; 455 gpio-ranges = <&pmx0 1 0 7>; 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 459 clock-names = "apb_pclk"; 460 }; 461 462 gpio1: gpio@e8a0c000 { 463 compatible = "arm,pl061", "arm,primecell"; 464 reg = <0 0xe8a0c000 0 0x1000>; 465 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 gpio-ranges = <&pmx0 1 7 7>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 472 clock-names = "apb_pclk"; 473 }; 474 475 gpio2: gpio@e8a0d000 { 476 compatible = "arm,pl061", "arm,primecell"; 477 reg = <0 0xe8a0d000 0 0x1000>; 478 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 479 gpio-controller; 480 #gpio-cells = <2>; 481 gpio-ranges = <&pmx0 0 14 8>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 485 clock-names = "apb_pclk"; 486 }; 487 488 gpio3: gpio@e8a0e000 { 489 compatible = "arm,pl061", "arm,primecell"; 490 reg = <0 0xe8a0e000 0 0x1000>; 491 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 492 gpio-controller; 493 #gpio-cells = <2>; 494 gpio-ranges = <&pmx0 0 22 8>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 498 clock-names = "apb_pclk"; 499 }; 500 501 gpio4: gpio@e8a0f000 { 502 compatible = "arm,pl061", "arm,primecell"; 503 reg = <0 0xe8a0f000 0 0x1000>; 504 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 505 gpio-controller; 506 #gpio-cells = <2>; 507 gpio-ranges = <&pmx0 0 30 8>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 511 clock-names = "apb_pclk"; 512 }; 513 514 gpio5: gpio@e8a10000 { 515 compatible = "arm,pl061", "arm,primecell"; 516 reg = <0 0xe8a10000 0 0x1000>; 517 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 518 gpio-controller; 519 #gpio-cells = <2>; 520 gpio-ranges = <&pmx0 0 38 8>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 524 clock-names = "apb_pclk"; 525 }; 526 527 gpio6: gpio@e8a11000 { 528 compatible = "arm,pl061", "arm,primecell"; 529 reg = <0 0xe8a11000 0 0x1000>; 530 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 gpio-ranges = <&pmx0 0 46 8>; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 537 clock-names = "apb_pclk"; 538 }; 539 540 gpio7: gpio@e8a12000 { 541 compatible = "arm,pl061", "arm,primecell"; 542 reg = <0 0xe8a12000 0 0x1000>; 543 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 544 gpio-controller; 545 #gpio-cells = <2>; 546 gpio-ranges = <&pmx0 0 54 8>; 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 550 clock-names = "apb_pclk"; 551 }; 552 553 gpio8: gpio@e8a13000 { 554 compatible = "arm,pl061", "arm,primecell"; 555 reg = <0 0xe8a13000 0 0x1000>; 556 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 557 gpio-controller; 558 #gpio-cells = <2>; 559 gpio-ranges = <&pmx0 0 62 8>; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 563 clock-names = "apb_pclk"; 564 }; 565 566 gpio9: gpio@e8a14000 { 567 compatible = "arm,pl061", "arm,primecell"; 568 reg = <0 0xe8a14000 0 0x1000>; 569 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 570 gpio-controller; 571 #gpio-cells = <2>; 572 gpio-ranges = <&pmx0 0 70 8>; 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 576 clock-names = "apb_pclk"; 577 }; 578 579 gpio10: gpio@e8a15000 { 580 compatible = "arm,pl061", "arm,primecell"; 581 reg = <0 0xe8a15000 0 0x1000>; 582 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 583 gpio-controller; 584 #gpio-cells = <2>; 585 gpio-ranges = <&pmx0 0 78 8>; 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 589 clock-names = "apb_pclk"; 590 }; 591 592 gpio11: gpio@e8a16000 { 593 compatible = "arm,pl061", "arm,primecell"; 594 reg = <0 0xe8a16000 0 0x1000>; 595 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 596 gpio-controller; 597 #gpio-cells = <2>; 598 gpio-ranges = <&pmx0 0 86 8>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 602 clock-names = "apb_pclk"; 603 }; 604 605 gpio12: gpio@e8a17000 { 606 compatible = "arm,pl061", "arm,primecell"; 607 reg = <0 0xe8a17000 0 0x1000>; 608 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 609 gpio-controller; 610 #gpio-cells = <2>; 611 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 615 clock-names = "apb_pclk"; 616 }; 617 618 gpio13: gpio@e8a18000 { 619 compatible = "arm,pl061", "arm,primecell"; 620 reg = <0 0xe8a18000 0 0x1000>; 621 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 622 gpio-controller; 623 #gpio-cells = <2>; 624 gpio-ranges = <&pmx0 0 102 8>; 625 interrupt-controller; 626 #interrupt-cells = <2>; 627 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 628 clock-names = "apb_pclk"; 629 }; 630 631 gpio14: gpio@e8a19000 { 632 compatible = "arm,pl061", "arm,primecell"; 633 reg = <0 0xe8a19000 0 0x1000>; 634 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 635 gpio-controller; 636 #gpio-cells = <2>; 637 gpio-ranges = <&pmx0 0 110 8>; 638 interrupt-controller; 639 #interrupt-cells = <2>; 640 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 641 clock-names = "apb_pclk"; 642 }; 643 644 gpio15: gpio@e8a1a000 { 645 compatible = "arm,pl061", "arm,primecell"; 646 reg = <0 0xe8a1a000 0 0x1000>; 647 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 648 gpio-controller; 649 #gpio-cells = <2>; 650 gpio-ranges = <&pmx0 0 118 6>; 651 interrupt-controller; 652 #interrupt-cells = <2>; 653 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 654 clock-names = "apb_pclk"; 655 }; 656 657 gpio16: gpio@e8a1b000 { 658 compatible = "arm,pl061", "arm,primecell"; 659 reg = <0 0xe8a1b000 0 0x1000>; 660 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 661 gpio-controller; 662 #gpio-cells = <2>; 663 interrupt-controller; 664 #interrupt-cells = <2>; 665 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 666 clock-names = "apb_pclk"; 667 }; 668 669 gpio17: gpio@e8a1c000 { 670 compatible = "arm,pl061", "arm,primecell"; 671 reg = <0 0xe8a1c000 0 0x1000>; 672 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 673 gpio-controller; 674 #gpio-cells = <2>; 675 interrupt-controller; 676 #interrupt-cells = <2>; 677 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 678 clock-names = "apb_pclk"; 679 }; 680 681 gpio18: gpio@ff3b4000 { 682 compatible = "arm,pl061", "arm,primecell"; 683 reg = <0 0xff3b4000 0 0x1000>; 684 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 685 gpio-controller; 686 #gpio-cells = <2>; 687 gpio-ranges = <&pmx2 0 0 8>; 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 691 clock-names = "apb_pclk"; 692 }; 693 694 gpio19: gpio@ff3b5000 { 695 compatible = "arm,pl061", "arm,primecell"; 696 reg = <0 0xff3b5000 0 0x1000>; 697 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 698 gpio-controller; 699 #gpio-cells = <2>; 700 gpio-ranges = <&pmx2 0 8 4>; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 704 clock-names = "apb_pclk"; 705 }; 706 707 gpio20: gpio@e8a1f000 { 708 compatible = "arm,pl061", "arm,primecell"; 709 reg = <0 0xe8a1f000 0 0x1000>; 710 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 711 gpio-controller; 712 #gpio-cells = <2>; 713 gpio-ranges = <&pmx1 0 0 6>; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 717 clock-names = "apb_pclk"; 718 }; 719 720 gpio21: gpio@e8a20000 { 721 compatible = "arm,pl061", "arm,primecell"; 722 reg = <0 0xe8a20000 0 0x1000>; 723 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 724 gpio-controller; 725 #gpio-cells = <2>; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 gpio-ranges = <&pmx3 0 0 6>; 729 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 730 clock-names = "apb_pclk"; 731 }; 732 733 gpio22: gpio@fff0b000 { 734 compatible = "arm,pl061", "arm,primecell"; 735 reg = <0 0xfff0b000 0 0x1000>; 736 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 737 gpio-controller; 738 #gpio-cells = <2>; 739 /* GPIO176 */ 740 gpio-ranges = <&pmx4 2 0 6>; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 744 clock-names = "apb_pclk"; 745 }; 746 747 gpio23: gpio@fff0c000 { 748 compatible = "arm,pl061", "arm,primecell"; 749 reg = <0 0xfff0c000 0 0x1000>; 750 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 751 gpio-controller; 752 #gpio-cells = <2>; 753 /* GPIO184 */ 754 gpio-ranges = <&pmx4 0 6 7>; 755 interrupt-controller; 756 #interrupt-cells = <2>; 757 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 758 clock-names = "apb_pclk"; 759 }; 760 761 gpio24: gpio@fff0d000 { 762 compatible = "arm,pl061", "arm,primecell"; 763 reg = <0 0xfff0d000 0 0x1000>; 764 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 765 gpio-controller; 766 #gpio-cells = <2>; 767 /* GPIO192 */ 768 gpio-ranges = <&pmx4 0 13 8>; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 772 clock-names = "apb_pclk"; 773 }; 774 775 gpio25: gpio@fff0e000 { 776 compatible = "arm,pl061", "arm,primecell"; 777 reg = <0 0xfff0e000 0 0x1000>; 778 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 779 gpio-controller; 780 #gpio-cells = <2>; 781 /* GPIO200 */ 782 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 783 interrupt-controller; 784 #interrupt-cells = <2>; 785 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 786 clock-names = "apb_pclk"; 787 }; 788 789 gpio26: gpio@fff0f000 { 790 compatible = "arm,pl061", "arm,primecell"; 791 reg = <0 0xfff0f000 0 0x1000>; 792 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 793 gpio-controller; 794 #gpio-cells = <2>; 795 /* GPIO208 */ 796 gpio-ranges = <&pmx4 0 28 8>; 797 interrupt-controller; 798 #interrupt-cells = <2>; 799 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 800 clock-names = "apb_pclk"; 801 }; 802 803 gpio27: gpio@fff10000 { 804 compatible = "arm,pl061", "arm,primecell"; 805 reg = <0 0xfff10000 0 0x1000>; 806 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 807 gpio-controller; 808 #gpio-cells = <2>; 809 /* GPIO216 */ 810 gpio-ranges = <&pmx4 0 36 6>; 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 814 clock-names = "apb_pclk"; 815 }; 816 817 gpio28: gpio@fff1d000 { 818 compatible = "arm,pl061", "arm,primecell"; 819 reg = <0 0xfff1d000 0 0x1000>; 820 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 821 gpio-controller; 822 #gpio-cells = <2>; 823 interrupt-controller; 824 #interrupt-cells = <2>; 825 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 826 clock-names = "apb_pclk"; 827 }; 828 829 spi2: spi@ffd68000 { 830 compatible = "arm,pl022", "arm,primecell"; 831 reg = <0x0 0xffd68000 0x0 0x1000>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 836 clock-names = "apb_pclk"; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&spi2_pmx_func>; 839 num-cs = <1>; 840 cs-gpios = <&gpio27 2 0>; 841 status = "disabled"; 842 }; 843 844 spi3: spi@ff3b3000 { 845 compatible = "arm,pl022", "arm,primecell"; 846 reg = <0x0 0xff3b3000 0x0 0x1000>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 851 clock-names = "apb_pclk"; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&spi3_pmx_func>; 854 num-cs = <1>; 855 cs-gpios = <&gpio18 5 0>; 856 status = "disabled"; 857 }; 858 859 pcie@f4000000 { 860 compatible = "hisilicon,kirin960-pcie"; 861 reg = <0x0 0xf4000000 0x0 0x1000>, 862 <0x0 0xff3fe000 0x0 0x1000>, 863 <0x0 0xf3f20000 0x0 0x40000>, 864 <0x0 0xf5000000 0x0 0x2000>; 865 reg-names = "dbi", "apb", "phy", "config"; 866 bus-range = <0x0 0x1>; 867 #address-cells = <3>; 868 #size-cells = <2>; 869 device_type = "pci"; 870 ranges = <0x02000000 0x0 0x00000000 871 0x0 0xf6000000 872 0x0 0x02000000>; 873 num-lanes = <1>; 874 #interrupt-cells = <1>; 875 interrupt-map-mask = <0xf800 0 0 7>; 876 interrupt-map = <0x0 0 0 1 877 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 878 <0x0 0 0 2 879 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 880 <0x0 0 0 3 881 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 882 <0x0 0 0 4 883 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 885 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 886 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 887 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 888 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 889 clock-names = "pcie_phy_ref", "pcie_aux", 890 "pcie_apb_phy", "pcie_apb_sys", 891 "pcie_aclk"; 892 reset-gpios = <&gpio11 1 0 >; 893 }; 894 895 /* SD */ 896 dwmmc1: dwmmc1@ff37f000 { 897 #address-cells = <1>; 898 #size-cells = <0>; 899 cd-inverted; 900 compatible = "hisilicon,hi3660-dw-mshc"; 901 num-slots = <1>; 902 bus-width = <0x4>; 903 disable-wp; 904 cap-sd-highspeed; 905 supports-highspeed; 906 card-detect-delay = <200>; 907 reg = <0x0 0xff37f000 0x0 0x1000>; 908 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 910 <&crg_ctrl HI3660_HCLK_GATE_SD>; 911 clock-names = "ciu", "biu"; 912 clock-frequency = <3200000>; 913 resets = <&crg_rst 0x94 18>; 914 reset-names = "reset"; 915 cd-gpios = <&gpio25 3 0>; 916 hisilicon,peripheral-syscon = <&sctrl>; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&sd_pmx_func 919 &sd_clk_cfg_func 920 &sd_cfg_func>; 921 sd-uhs-sdr12; 922 sd-uhs-sdr25; 923 sd-uhs-sdr50; 924 sd-uhs-sdr104; 925 status = "disabled"; 926 927 slot@0 { 928 reg = <0x0>; 929 bus-width = <4>; 930 disable-wp; 931 }; 932 }; 933 934 /* SDIO */ 935 dwmmc2: dwmmc2@ff3ff000 { 936 compatible = "hisilicon,hi3660-dw-mshc"; 937 reg = <0x0 0xff3ff000 0x0 0x1000>; 938 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 939 num-slots = <1>; 940 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 941 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 942 clock-names = "ciu", "biu"; 943 resets = <&crg_rst 0x94 20>; 944 reset-names = "reset"; 945 card-detect-delay = <200>; 946 supports-highspeed; 947 keep-power-in-suspend; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&sdio_pmx_func 950 &sdio_clk_cfg_func 951 &sdio_cfg_func>; 952 status = "disabled"; 953 }; 954 955 watchdog0: watchdog@e8a06000 { 956 compatible = "arm,sp805-wdt", "arm,primecell"; 957 reg = <0x0 0xe8a06000 0x0 0x1000>; 958 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&crg_ctrl HI3660_OSC32K>; 960 clock-names = "apb_pclk"; 961 }; 962 963 watchdog1: watchdog@e8a07000 { 964 compatible = "arm,sp805-wdt", "arm,primecell"; 965 reg = <0x0 0xe8a07000 0x0 0x1000>; 966 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&crg_ctrl HI3660_OSC32K>; 968 clock-names = "apb_pclk"; 969 }; 970 971 tsensor: tsensor@fff30000 { 972 compatible = "hisilicon,hi3660-tsensor"; 973 reg = <0x0 0xfff30000 0x0 0x1000>; 974 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 975 #thermal-sensor-cells = <1>; 976 }; 977 }; 978}; 979