1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3660 SoC 4 * 5 * Copyright (C) 2016, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/hi3660-clock.h> 10 11/ { 12 compatible = "hisilicon,hi3660"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 psci { 18 compatible = "arm,psci-0.2"; 19 method = "smc"; 20 }; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 core1 { 32 cpu = <&cpu1>; 33 }; 34 core2 { 35 cpu = <&cpu2>; 36 }; 37 core3 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53", "arm,armv8"; 59 device_type = "cpu"; 60 reg = <0x0 0x0>; 61 enable-method = "psci"; 62 next-level-cache = <&A53_L2>; 63 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 64 capacity-dmips-mhz = <592>; 65 }; 66 67 cpu1: cpu@1 { 68 compatible = "arm,cortex-a53", "arm,armv8"; 69 device_type = "cpu"; 70 reg = <0x0 0x1>; 71 enable-method = "psci"; 72 next-level-cache = <&A53_L2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 74 capacity-dmips-mhz = <592>; 75 }; 76 77 cpu2: cpu@2 { 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 device_type = "cpu"; 80 reg = <0x0 0x2>; 81 enable-method = "psci"; 82 next-level-cache = <&A53_L2>; 83 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 84 capacity-dmips-mhz = <592>; 85 }; 86 87 cpu3: cpu@3 { 88 compatible = "arm,cortex-a53", "arm,armv8"; 89 device_type = "cpu"; 90 reg = <0x0 0x3>; 91 enable-method = "psci"; 92 next-level-cache = <&A53_L2>; 93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 94 capacity-dmips-mhz = <592>; 95 }; 96 97 cpu4: cpu@100 { 98 compatible = "arm,cortex-a73", "arm,armv8"; 99 device_type = "cpu"; 100 reg = <0x0 0x100>; 101 enable-method = "psci"; 102 next-level-cache = <&A73_L2>; 103 cpu-idle-states = < 104 &CPU_NAP 105 &CPU_SLEEP 106 &CLUSTER_SLEEP_1 107 >; 108 capacity-dmips-mhz = <1024>; 109 }; 110 111 cpu5: cpu@101 { 112 compatible = "arm,cortex-a73", "arm,armv8"; 113 device_type = "cpu"; 114 reg = <0x0 0x101>; 115 enable-method = "psci"; 116 next-level-cache = <&A73_L2>; 117 cpu-idle-states = < 118 &CPU_NAP 119 &CPU_SLEEP 120 &CLUSTER_SLEEP_1 121 >; 122 capacity-dmips-mhz = <1024>; 123 }; 124 125 cpu6: cpu@102 { 126 compatible = "arm,cortex-a73", "arm,armv8"; 127 device_type = "cpu"; 128 reg = <0x0 0x102>; 129 enable-method = "psci"; 130 next-level-cache = <&A73_L2>; 131 cpu-idle-states = < 132 &CPU_NAP 133 &CPU_SLEEP 134 &CLUSTER_SLEEP_1 135 >; 136 capacity-dmips-mhz = <1024>; 137 }; 138 139 cpu7: cpu@103 { 140 compatible = "arm,cortex-a73", "arm,armv8"; 141 device_type = "cpu"; 142 reg = <0x0 0x103>; 143 enable-method = "psci"; 144 next-level-cache = <&A73_L2>; 145 cpu-idle-states = < 146 &CPU_NAP 147 &CPU_SLEEP 148 &CLUSTER_SLEEP_1 149 >; 150 capacity-dmips-mhz = <1024>; 151 }; 152 153 idle-states { 154 entry-method = "psci"; 155 156 CPU_NAP: cpu-nap { 157 compatible = "arm,idle-state"; 158 arm,psci-suspend-param = <0x0000001>; 159 entry-latency-us = <7>; 160 exit-latency-us = <2>; 161 min-residency-us = <15>; 162 }; 163 164 CPU_SLEEP: cpu-sleep { 165 compatible = "arm,idle-state"; 166 local-timer-stop; 167 arm,psci-suspend-param = <0x0010000>; 168 entry-latency-us = <40>; 169 exit-latency-us = <70>; 170 min-residency-us = <3000>; 171 }; 172 173 CLUSTER_SLEEP_0: cluster-sleep-0 { 174 compatible = "arm,idle-state"; 175 local-timer-stop; 176 arm,psci-suspend-param = <0x1010000>; 177 entry-latency-us = <500>; 178 exit-latency-us = <5000>; 179 min-residency-us = <20000>; 180 }; 181 182 CLUSTER_SLEEP_1: cluster-sleep-1 { 183 compatible = "arm,idle-state"; 184 local-timer-stop; 185 arm,psci-suspend-param = <0x1010000>; 186 entry-latency-us = <1000>; 187 exit-latency-us = <5000>; 188 min-residency-us = <20000>; 189 }; 190 }; 191 192 A53_L2: l2-cache0 { 193 compatible = "cache"; 194 }; 195 196 A73_L2: l2-cache1 { 197 compatible = "cache"; 198 }; 199 }; 200 201 gic: interrupt-controller@e82b0000 { 202 compatible = "arm,gic-400"; 203 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 204 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 205 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 206 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 207 #address-cells = <0>; 208 #interrupt-cells = <3>; 209 interrupt-controller; 210 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 211 IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 a53-pmu { 215 compatible = "arm,cortex-a53-pmu"; 216 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 220 interrupt-affinity = <&cpu0>, 221 <&cpu1>, 222 <&cpu2>, 223 <&cpu3>; 224 }; 225 226 a73-pmu { 227 compatible = "arm,cortex-a73-pmu"; 228 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 232 interrupt-affinity = <&cpu4>, 233 <&cpu5>, 234 <&cpu6>, 235 <&cpu7>; 236 }; 237 238 timer { 239 compatible = "arm,armv8-timer"; 240 interrupt-parent = <&gic>; 241 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 242 IRQ_TYPE_LEVEL_LOW)>, 243 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 244 IRQ_TYPE_LEVEL_LOW)>, 245 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 246 IRQ_TYPE_LEVEL_LOW)>, 247 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 248 IRQ_TYPE_LEVEL_LOW)>; 249 }; 250 251 soc { 252 compatible = "simple-bus"; 253 #address-cells = <2>; 254 #size-cells = <2>; 255 ranges; 256 257 crg_ctrl: crg_ctrl@fff35000 { 258 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 259 reg = <0x0 0xfff35000 0x0 0x1000>; 260 #clock-cells = <1>; 261 }; 262 263 crg_rst: crg_rst_controller { 264 compatible = "hisilicon,hi3660-reset"; 265 #reset-cells = <2>; 266 hisi,rst-syscon = <&crg_ctrl>; 267 }; 268 269 270 pctrl: pctrl@e8a09000 { 271 compatible = "hisilicon,hi3660-pctrl", "syscon"; 272 reg = <0x0 0xe8a09000 0x0 0x2000>; 273 #clock-cells = <1>; 274 }; 275 276 pmuctrl: crg_ctrl@fff34000 { 277 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 278 reg = <0x0 0xfff34000 0x0 0x1000>; 279 #clock-cells = <1>; 280 }; 281 282 sctrl: sctrl@fff0a000 { 283 compatible = "hisilicon,hi3660-sctrl", "syscon"; 284 reg = <0x0 0xfff0a000 0x0 0x1000>; 285 #clock-cells = <1>; 286 }; 287 288 iomcu: iomcu@ffd7e000 { 289 compatible = "hisilicon,hi3660-iomcu", "syscon"; 290 reg = <0x0 0xffd7e000 0x0 0x1000>; 291 #clock-cells = <1>; 292 293 }; 294 295 iomcu_rst: reset { 296 compatible = "hisilicon,hi3660-reset"; 297 hisi,rst-syscon = <&iomcu>; 298 #reset-cells = <2>; 299 }; 300 301 dual_timer0: timer@fff14000 { 302 compatible = "arm,sp804", "arm,primecell"; 303 reg = <0x0 0xfff14000 0x0 0x1000>; 304 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&crg_ctrl HI3660_OSC32K>, 307 <&crg_ctrl HI3660_OSC32K>, 308 <&crg_ctrl HI3660_OSC32K>; 309 clock-names = "timer1", "timer2", "apb_pclk"; 310 }; 311 312 i2c0: i2c@ffd71000 { 313 compatible = "snps,designware-i2c"; 314 reg = <0x0 0xffd71000 0x0 0x1000>; 315 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 clock-frequency = <400000>; 319 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 320 resets = <&iomcu_rst 0x20 3>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 323 status = "disabled"; 324 }; 325 326 i2c1: i2c@ffd72000 { 327 compatible = "snps,designware-i2c"; 328 reg = <0x0 0xffd72000 0x0 0x1000>; 329 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 clock-frequency = <400000>; 333 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 334 resets = <&iomcu_rst 0x20 4>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 337 status = "disabled"; 338 }; 339 340 i2c3: i2c@fdf0c000 { 341 compatible = "snps,designware-i2c"; 342 reg = <0x0 0xfdf0c000 0x0 0x1000>; 343 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 clock-frequency = <400000>; 347 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 348 resets = <&crg_rst 0x78 7>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 351 status = "disabled"; 352 }; 353 354 i2c7: i2c@fdf0b000 { 355 compatible = "snps,designware-i2c"; 356 reg = <0x0 0xfdf0b000 0x0 0x1000>; 357 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 clock-frequency = <400000>; 361 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 362 resets = <&crg_rst 0x60 14>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 365 status = "disabled"; 366 }; 367 368 uart0: serial@fdf02000 { 369 compatible = "arm,pl011", "arm,primecell"; 370 reg = <0x0 0xfdf02000 0x0 0x1000>; 371 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 373 <&crg_ctrl HI3660_PCLK>; 374 clock-names = "uartclk", "apb_pclk"; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 377 status = "disabled"; 378 }; 379 380 uart1: serial@fdf00000 { 381 compatible = "arm,pl011", "arm,primecell"; 382 reg = <0x0 0xfdf00000 0x0 0x1000>; 383 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 385 <&crg_ctrl HI3660_CLK_GATE_UART1>; 386 clock-names = "uartclk", "apb_pclk"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 389 status = "disabled"; 390 }; 391 392 uart2: serial@fdf03000 { 393 compatible = "arm,pl011", "arm,primecell"; 394 reg = <0x0 0xfdf03000 0x0 0x1000>; 395 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 397 <&crg_ctrl HI3660_PCLK>; 398 clock-names = "uartclk", "apb_pclk"; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 401 status = "disabled"; 402 }; 403 404 uart3: serial@ffd74000 { 405 compatible = "arm,pl011", "arm,primecell"; 406 reg = <0x0 0xffd74000 0x0 0x1000>; 407 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 409 <&crg_ctrl HI3660_PCLK>; 410 clock-names = "uartclk", "apb_pclk"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 413 status = "disabled"; 414 }; 415 416 uart4: serial@fdf01000 { 417 compatible = "arm,pl011", "arm,primecell"; 418 reg = <0x0 0xfdf01000 0x0 0x1000>; 419 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 421 <&crg_ctrl HI3660_CLK_GATE_UART4>; 422 clock-names = "uartclk", "apb_pclk"; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 425 status = "disabled"; 426 }; 427 428 uart5: serial@fdf05000 { 429 compatible = "arm,pl011", "arm,primecell"; 430 reg = <0x0 0xfdf05000 0x0 0x1000>; 431 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 433 <&crg_ctrl HI3660_CLK_GATE_UART5>; 434 clock-names = "uartclk", "apb_pclk"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 437 status = "disabled"; 438 }; 439 440 uart6: serial@fff32000 { 441 compatible = "arm,pl011", "arm,primecell"; 442 reg = <0x0 0xfff32000 0x0 0x1000>; 443 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&crg_ctrl HI3660_CLK_UART6>, 445 <&crg_ctrl HI3660_PCLK>; 446 clock-names = "uartclk", "apb_pclk"; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 449 status = "disabled"; 450 }; 451 452 dma0: dma@fdf30000 { 453 compatible = "hisilicon,k3-dma-1.0"; 454 reg = <0x0 0xfdf30000 0x0 0x1000>; 455 #dma-cells = <1>; 456 dma-channels = <16>; 457 dma-requests = <32>; 458 dma-min-chan = <1>; 459 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 461 dma-no-cci; 462 dma-type = "hi3660_dma"; 463 }; 464 465 rtc0: rtc@fff04000 { 466 compatible = "arm,pl031", "arm,primecell"; 467 reg = <0x0 0Xfff04000 0x0 0x1000>; 468 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&crg_ctrl HI3660_PCLK>; 470 clock-names = "apb_pclk"; 471 }; 472 473 gpio0: gpio@e8a0b000 { 474 compatible = "arm,pl061", "arm,primecell"; 475 reg = <0 0xe8a0b000 0 0x1000>; 476 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 gpio-ranges = <&pmx0 1 0 7>; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 483 clock-names = "apb_pclk"; 484 }; 485 486 gpio1: gpio@e8a0c000 { 487 compatible = "arm,pl061", "arm,primecell"; 488 reg = <0 0xe8a0c000 0 0x1000>; 489 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 490 gpio-controller; 491 #gpio-cells = <2>; 492 gpio-ranges = <&pmx0 1 7 7>; 493 interrupt-controller; 494 #interrupt-cells = <2>; 495 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 496 clock-names = "apb_pclk"; 497 }; 498 499 gpio2: gpio@e8a0d000 { 500 compatible = "arm,pl061", "arm,primecell"; 501 reg = <0 0xe8a0d000 0 0x1000>; 502 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 503 gpio-controller; 504 #gpio-cells = <2>; 505 gpio-ranges = <&pmx0 0 14 8>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 509 clock-names = "apb_pclk"; 510 }; 511 512 gpio3: gpio@e8a0e000 { 513 compatible = "arm,pl061", "arm,primecell"; 514 reg = <0 0xe8a0e000 0 0x1000>; 515 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 516 gpio-controller; 517 #gpio-cells = <2>; 518 gpio-ranges = <&pmx0 0 22 8>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 522 clock-names = "apb_pclk"; 523 }; 524 525 gpio4: gpio@e8a0f000 { 526 compatible = "arm,pl061", "arm,primecell"; 527 reg = <0 0xe8a0f000 0 0x1000>; 528 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 529 gpio-controller; 530 #gpio-cells = <2>; 531 gpio-ranges = <&pmx0 0 30 8>; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 535 clock-names = "apb_pclk"; 536 }; 537 538 gpio5: gpio@e8a10000 { 539 compatible = "arm,pl061", "arm,primecell"; 540 reg = <0 0xe8a10000 0 0x1000>; 541 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 542 gpio-controller; 543 #gpio-cells = <2>; 544 gpio-ranges = <&pmx0 0 38 8>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 548 clock-names = "apb_pclk"; 549 }; 550 551 gpio6: gpio@e8a11000 { 552 compatible = "arm,pl061", "arm,primecell"; 553 reg = <0 0xe8a11000 0 0x1000>; 554 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 555 gpio-controller; 556 #gpio-cells = <2>; 557 gpio-ranges = <&pmx0 0 46 8>; 558 interrupt-controller; 559 #interrupt-cells = <2>; 560 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 561 clock-names = "apb_pclk"; 562 }; 563 564 gpio7: gpio@e8a12000 { 565 compatible = "arm,pl061", "arm,primecell"; 566 reg = <0 0xe8a12000 0 0x1000>; 567 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 568 gpio-controller; 569 #gpio-cells = <2>; 570 gpio-ranges = <&pmx0 0 54 8>; 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 574 clock-names = "apb_pclk"; 575 }; 576 577 gpio8: gpio@e8a13000 { 578 compatible = "arm,pl061", "arm,primecell"; 579 reg = <0 0xe8a13000 0 0x1000>; 580 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 581 gpio-controller; 582 #gpio-cells = <2>; 583 gpio-ranges = <&pmx0 0 62 8>; 584 interrupt-controller; 585 #interrupt-cells = <2>; 586 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 587 clock-names = "apb_pclk"; 588 }; 589 590 gpio9: gpio@e8a14000 { 591 compatible = "arm,pl061", "arm,primecell"; 592 reg = <0 0xe8a14000 0 0x1000>; 593 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 594 gpio-controller; 595 #gpio-cells = <2>; 596 gpio-ranges = <&pmx0 0 70 8>; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 600 clock-names = "apb_pclk"; 601 }; 602 603 gpio10: gpio@e8a15000 { 604 compatible = "arm,pl061", "arm,primecell"; 605 reg = <0 0xe8a15000 0 0x1000>; 606 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 607 gpio-controller; 608 #gpio-cells = <2>; 609 gpio-ranges = <&pmx0 0 78 8>; 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 613 clock-names = "apb_pclk"; 614 }; 615 616 gpio11: gpio@e8a16000 { 617 compatible = "arm,pl061", "arm,primecell"; 618 reg = <0 0xe8a16000 0 0x1000>; 619 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 620 gpio-controller; 621 #gpio-cells = <2>; 622 gpio-ranges = <&pmx0 0 86 8>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 626 clock-names = "apb_pclk"; 627 }; 628 629 gpio12: gpio@e8a17000 { 630 compatible = "arm,pl061", "arm,primecell"; 631 reg = <0 0xe8a17000 0 0x1000>; 632 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 633 gpio-controller; 634 #gpio-cells = <2>; 635 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 636 interrupt-controller; 637 #interrupt-cells = <2>; 638 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 639 clock-names = "apb_pclk"; 640 }; 641 642 gpio13: gpio@e8a18000 { 643 compatible = "arm,pl061", "arm,primecell"; 644 reg = <0 0xe8a18000 0 0x1000>; 645 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 646 gpio-controller; 647 #gpio-cells = <2>; 648 gpio-ranges = <&pmx0 0 102 8>; 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 652 clock-names = "apb_pclk"; 653 }; 654 655 gpio14: gpio@e8a19000 { 656 compatible = "arm,pl061", "arm,primecell"; 657 reg = <0 0xe8a19000 0 0x1000>; 658 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 659 gpio-controller; 660 #gpio-cells = <2>; 661 gpio-ranges = <&pmx0 0 110 8>; 662 interrupt-controller; 663 #interrupt-cells = <2>; 664 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 665 clock-names = "apb_pclk"; 666 }; 667 668 gpio15: gpio@e8a1a000 { 669 compatible = "arm,pl061", "arm,primecell"; 670 reg = <0 0xe8a1a000 0 0x1000>; 671 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 672 gpio-controller; 673 #gpio-cells = <2>; 674 gpio-ranges = <&pmx0 0 118 6>; 675 interrupt-controller; 676 #interrupt-cells = <2>; 677 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 678 clock-names = "apb_pclk"; 679 }; 680 681 gpio16: gpio@e8a1b000 { 682 compatible = "arm,pl061", "arm,primecell"; 683 reg = <0 0xe8a1b000 0 0x1000>; 684 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 685 gpio-controller; 686 #gpio-cells = <2>; 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 690 clock-names = "apb_pclk"; 691 }; 692 693 gpio17: gpio@e8a1c000 { 694 compatible = "arm,pl061", "arm,primecell"; 695 reg = <0 0xe8a1c000 0 0x1000>; 696 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 697 gpio-controller; 698 #gpio-cells = <2>; 699 interrupt-controller; 700 #interrupt-cells = <2>; 701 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 702 clock-names = "apb_pclk"; 703 }; 704 705 gpio18: gpio@ff3b4000 { 706 compatible = "arm,pl061", "arm,primecell"; 707 reg = <0 0xff3b4000 0 0x1000>; 708 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 709 gpio-controller; 710 #gpio-cells = <2>; 711 gpio-ranges = <&pmx2 0 0 8>; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 715 clock-names = "apb_pclk"; 716 }; 717 718 gpio19: gpio@ff3b5000 { 719 compatible = "arm,pl061", "arm,primecell"; 720 reg = <0 0xff3b5000 0 0x1000>; 721 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 722 gpio-controller; 723 #gpio-cells = <2>; 724 gpio-ranges = <&pmx2 0 8 4>; 725 interrupt-controller; 726 #interrupt-cells = <2>; 727 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 728 clock-names = "apb_pclk"; 729 }; 730 731 gpio20: gpio@e8a1f000 { 732 compatible = "arm,pl061", "arm,primecell"; 733 reg = <0 0xe8a1f000 0 0x1000>; 734 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 735 gpio-controller; 736 #gpio-cells = <2>; 737 gpio-ranges = <&pmx1 0 0 6>; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 741 clock-names = "apb_pclk"; 742 }; 743 744 gpio21: gpio@e8a20000 { 745 compatible = "arm,pl061", "arm,primecell"; 746 reg = <0 0xe8a20000 0 0x1000>; 747 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 748 gpio-controller; 749 #gpio-cells = <2>; 750 interrupt-controller; 751 #interrupt-cells = <2>; 752 gpio-ranges = <&pmx3 0 0 6>; 753 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 754 clock-names = "apb_pclk"; 755 }; 756 757 gpio22: gpio@fff0b000 { 758 compatible = "arm,pl061", "arm,primecell"; 759 reg = <0 0xfff0b000 0 0x1000>; 760 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 761 gpio-controller; 762 #gpio-cells = <2>; 763 /* GPIO176 */ 764 gpio-ranges = <&pmx4 2 0 6>; 765 interrupt-controller; 766 #interrupt-cells = <2>; 767 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 768 clock-names = "apb_pclk"; 769 }; 770 771 gpio23: gpio@fff0c000 { 772 compatible = "arm,pl061", "arm,primecell"; 773 reg = <0 0xfff0c000 0 0x1000>; 774 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 775 gpio-controller; 776 #gpio-cells = <2>; 777 /* GPIO184 */ 778 gpio-ranges = <&pmx4 0 6 7>; 779 interrupt-controller; 780 #interrupt-cells = <2>; 781 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 782 clock-names = "apb_pclk"; 783 }; 784 785 gpio24: gpio@fff0d000 { 786 compatible = "arm,pl061", "arm,primecell"; 787 reg = <0 0xfff0d000 0 0x1000>; 788 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 789 gpio-controller; 790 #gpio-cells = <2>; 791 /* GPIO192 */ 792 gpio-ranges = <&pmx4 0 13 8>; 793 interrupt-controller; 794 #interrupt-cells = <2>; 795 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 796 clock-names = "apb_pclk"; 797 }; 798 799 gpio25: gpio@fff0e000 { 800 compatible = "arm,pl061", "arm,primecell"; 801 reg = <0 0xfff0e000 0 0x1000>; 802 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 803 gpio-controller; 804 #gpio-cells = <2>; 805 /* GPIO200 */ 806 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 807 interrupt-controller; 808 #interrupt-cells = <2>; 809 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 810 clock-names = "apb_pclk"; 811 }; 812 813 gpio26: gpio@fff0f000 { 814 compatible = "arm,pl061", "arm,primecell"; 815 reg = <0 0xfff0f000 0 0x1000>; 816 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 817 gpio-controller; 818 #gpio-cells = <2>; 819 /* GPIO208 */ 820 gpio-ranges = <&pmx4 0 28 8>; 821 interrupt-controller; 822 #interrupt-cells = <2>; 823 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 824 clock-names = "apb_pclk"; 825 }; 826 827 gpio27: gpio@fff10000 { 828 compatible = "arm,pl061", "arm,primecell"; 829 reg = <0 0xfff10000 0 0x1000>; 830 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 831 gpio-controller; 832 #gpio-cells = <2>; 833 /* GPIO216 */ 834 gpio-ranges = <&pmx4 0 36 6>; 835 interrupt-controller; 836 #interrupt-cells = <2>; 837 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 838 clock-names = "apb_pclk"; 839 }; 840 841 gpio28: gpio@fff1d000 { 842 compatible = "arm,pl061", "arm,primecell"; 843 reg = <0 0xfff1d000 0 0x1000>; 844 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 845 gpio-controller; 846 #gpio-cells = <2>; 847 interrupt-controller; 848 #interrupt-cells = <2>; 849 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 850 clock-names = "apb_pclk"; 851 }; 852 853 spi2: spi@ffd68000 { 854 compatible = "arm,pl022", "arm,primecell"; 855 reg = <0x0 0xffd68000 0x0 0x1000>; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 860 clock-names = "apb_pclk"; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&spi2_pmx_func>; 863 num-cs = <1>; 864 cs-gpios = <&gpio27 2 0>; 865 status = "disabled"; 866 }; 867 868 spi3: spi@ff3b3000 { 869 compatible = "arm,pl022", "arm,primecell"; 870 reg = <0x0 0xff3b3000 0x0 0x1000>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 875 clock-names = "apb_pclk"; 876 pinctrl-names = "default"; 877 pinctrl-0 = <&spi3_pmx_func>; 878 num-cs = <1>; 879 cs-gpios = <&gpio18 5 0>; 880 status = "disabled"; 881 }; 882 883 pcie@f4000000 { 884 compatible = "hisilicon,kirin960-pcie"; 885 reg = <0x0 0xf4000000 0x0 0x1000>, 886 <0x0 0xff3fe000 0x0 0x1000>, 887 <0x0 0xf3f20000 0x0 0x40000>, 888 <0x0 0xf5000000 0x0 0x2000>; 889 reg-names = "dbi", "apb", "phy", "config"; 890 bus-range = <0x0 0x1>; 891 #address-cells = <3>; 892 #size-cells = <2>; 893 device_type = "pci"; 894 ranges = <0x02000000 0x0 0x00000000 895 0x0 0xf6000000 896 0x0 0x02000000>; 897 num-lanes = <1>; 898 #interrupt-cells = <1>; 899 interrupt-map-mask = <0xf800 0 0 7>; 900 interrupt-map = <0x0 0 0 1 901 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 902 <0x0 0 0 2 903 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 904 <0x0 0 0 3 905 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 906 <0x0 0 0 4 907 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 909 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 910 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 911 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 912 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 913 clock-names = "pcie_phy_ref", "pcie_aux", 914 "pcie_apb_phy", "pcie_apb_sys", 915 "pcie_aclk"; 916 reset-gpios = <&gpio11 1 0 >; 917 }; 918 919 /* SD */ 920 dwmmc1: dwmmc1@ff37f000 { 921 #address-cells = <1>; 922 #size-cells = <0>; 923 cd-inverted; 924 compatible = "hisilicon,hi3660-dw-mshc"; 925 bus-width = <0x4>; 926 disable-wp; 927 cap-sd-highspeed; 928 supports-highspeed; 929 card-detect-delay = <200>; 930 reg = <0x0 0xff37f000 0x0 0x1000>; 931 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 933 <&crg_ctrl HI3660_HCLK_GATE_SD>; 934 clock-names = "ciu", "biu"; 935 clock-frequency = <3200000>; 936 resets = <&crg_rst 0x94 18>; 937 reset-names = "reset"; 938 cd-gpios = <&gpio25 3 0>; 939 hisilicon,peripheral-syscon = <&sctrl>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&sd_pmx_func 942 &sd_clk_cfg_func 943 &sd_cfg_func>; 944 sd-uhs-sdr12; 945 sd-uhs-sdr25; 946 sd-uhs-sdr50; 947 sd-uhs-sdr104; 948 status = "disabled"; 949 950 slot@0 { 951 reg = <0x0>; 952 bus-width = <4>; 953 disable-wp; 954 }; 955 }; 956 957 /* SDIO */ 958 dwmmc2: dwmmc2@ff3ff000 { 959 compatible = "hisilicon,hi3660-dw-mshc"; 960 reg = <0x0 0xff3ff000 0x0 0x1000>; 961 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 963 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 964 clock-names = "ciu", "biu"; 965 resets = <&crg_rst 0x94 20>; 966 reset-names = "reset"; 967 card-detect-delay = <200>; 968 supports-highspeed; 969 keep-power-in-suspend; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&sdio_pmx_func 972 &sdio_clk_cfg_func 973 &sdio_cfg_func>; 974 status = "disabled"; 975 }; 976 977 watchdog0: watchdog@e8a06000 { 978 compatible = "arm,sp805-wdt", "arm,primecell"; 979 reg = <0x0 0xe8a06000 0x0 0x1000>; 980 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&crg_ctrl HI3660_OSC32K>; 982 clock-names = "apb_pclk"; 983 }; 984 985 watchdog1: watchdog@e8a07000 { 986 compatible = "arm,sp805-wdt", "arm,primecell"; 987 reg = <0x0 0xe8a07000 0x0 0x1000>; 988 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&crg_ctrl HI3660_OSC32K>; 990 clock-names = "apb_pclk"; 991 }; 992 993 tsensor: tsensor@fff30000 { 994 compatible = "hisilicon,hi3660-tsensor"; 995 reg = <0x0 0xfff30000 0x0 0x1000>; 996 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 997 #thermal-sensor-cells = <1>; 998 }; 999 }; 1000}; 1001