1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3660 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/hi3660-clock.h>
10
11/ {
12	compatible = "hisilicon,hi3660";
13	interrupt-parent = <&gic>;
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	psci {
18		compatible = "arm,psci-0.2";
19		method = "smc";
20	};
21
22	cpus {
23		#address-cells = <2>;
24		#size-cells = <0>;
25
26		cpu-map {
27			cluster0 {
28				core0 {
29					cpu = <&cpu0>;
30				};
31				core1 {
32					cpu = <&cpu1>;
33				};
34				core2 {
35					cpu = <&cpu2>;
36				};
37				core3 {
38					cpu = <&cpu3>;
39				};
40			};
41			cluster1 {
42				core0 {
43					cpu = <&cpu4>;
44				};
45				core1 {
46					cpu = <&cpu5>;
47				};
48				core2 {
49					cpu = <&cpu6>;
50				};
51				core3 {
52					cpu = <&cpu7>;
53				};
54			};
55		};
56
57		cpu0: cpu@0 {
58			compatible = "arm,cortex-a53", "arm,armv8";
59			device_type = "cpu";
60			reg = <0x0 0x0>;
61			enable-method = "psci";
62			next-level-cache = <&A53_L2>;
63			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
64		};
65
66		cpu1: cpu@1 {
67			compatible = "arm,cortex-a53", "arm,armv8";
68			device_type = "cpu";
69			reg = <0x0 0x1>;
70			enable-method = "psci";
71			next-level-cache = <&A53_L2>;
72			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
73		};
74
75		cpu2: cpu@2 {
76			compatible = "arm,cortex-a53", "arm,armv8";
77			device_type = "cpu";
78			reg = <0x0 0x2>;
79			enable-method = "psci";
80			next-level-cache = <&A53_L2>;
81			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
82		};
83
84		cpu3: cpu@3 {
85			compatible = "arm,cortex-a53", "arm,armv8";
86			device_type = "cpu";
87			reg = <0x0 0x3>;
88			enable-method = "psci";
89			next-level-cache = <&A53_L2>;
90			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
91		};
92
93		cpu4: cpu@100 {
94			compatible = "arm,cortex-a73", "arm,armv8";
95			device_type = "cpu";
96			reg = <0x0 0x100>;
97			enable-method = "psci";
98			next-level-cache = <&A73_L2>;
99			cpu-idle-states = <
100					&CPU_NAP
101					&CPU_SLEEP
102					&CLUSTER_SLEEP_1
103			>;
104		};
105
106		cpu5: cpu@101 {
107			compatible = "arm,cortex-a73", "arm,armv8";
108			device_type = "cpu";
109			reg = <0x0 0x101>;
110			enable-method = "psci";
111			next-level-cache = <&A73_L2>;
112			cpu-idle-states = <
113					&CPU_NAP
114					&CPU_SLEEP
115					&CLUSTER_SLEEP_1
116			>;
117		};
118
119		cpu6: cpu@102 {
120			compatible = "arm,cortex-a73", "arm,armv8";
121			device_type = "cpu";
122			reg = <0x0 0x102>;
123			enable-method = "psci";
124			next-level-cache = <&A73_L2>;
125			cpu-idle-states = <
126					&CPU_NAP
127					&CPU_SLEEP
128					&CLUSTER_SLEEP_1
129			>;
130		};
131
132		cpu7: cpu@103 {
133			compatible = "arm,cortex-a73", "arm,armv8";
134			device_type = "cpu";
135			reg = <0x0 0x103>;
136			enable-method = "psci";
137			next-level-cache = <&A73_L2>;
138			cpu-idle-states = <
139					&CPU_NAP
140					&CPU_SLEEP
141					&CLUSTER_SLEEP_1
142			>;
143		};
144
145		idle-states {
146			entry-method = "psci";
147
148			CPU_NAP: cpu-nap {
149				compatible = "arm,idle-state";
150				arm,psci-suspend-param = <0x0000001>;
151				entry-latency-us = <7>;
152				exit-latency-us = <2>;
153				min-residency-us = <15>;
154			};
155
156			CPU_SLEEP: cpu-sleep {
157				compatible = "arm,idle-state";
158				local-timer-stop;
159				arm,psci-suspend-param = <0x0010000>;
160				entry-latency-us = <40>;
161				exit-latency-us = <70>;
162				min-residency-us = <3000>;
163			};
164
165			CLUSTER_SLEEP_0: cluster-sleep-0 {
166				compatible = "arm,idle-state";
167				local-timer-stop;
168				arm,psci-suspend-param = <0x1010000>;
169				entry-latency-us = <500>;
170				exit-latency-us = <5000>;
171				min-residency-us = <20000>;
172			};
173
174			CLUSTER_SLEEP_1: cluster-sleep-1 {
175				compatible = "arm,idle-state";
176				local-timer-stop;
177				arm,psci-suspend-param = <0x1010000>;
178				entry-latency-us = <1000>;
179				exit-latency-us = <5000>;
180				min-residency-us = <20000>;
181			};
182		};
183
184		A53_L2: l2-cache0 {
185			compatible = "cache";
186		};
187
188		A73_L2: l2-cache1 {
189			compatible = "cache";
190		};
191	};
192
193	gic: interrupt-controller@e82b0000 {
194		compatible = "arm,gic-400";
195		reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
196		      <0x0 0xe82b2000 0 0x2000>, /* GICC */
197		      <0x0 0xe82b4000 0 0x2000>, /* GICH */
198		      <0x0 0xe82b6000 0 0x2000>; /* GICV */
199		#address-cells = <0>;
200		#interrupt-cells = <3>;
201		interrupt-controller;
202		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
203					 IRQ_TYPE_LEVEL_HIGH)>;
204	};
205
206	pmu {
207		compatible = "arm,armv8-pmuv3";
208		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
209			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
210			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
211			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
212			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
213			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
214			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
215			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
216		interrupt-affinity = <&cpu0>,
217				     <&cpu1>,
218				     <&cpu2>,
219				     <&cpu3>,
220				     <&cpu4>,
221				     <&cpu5>,
222				     <&cpu6>,
223				     <&cpu7>;
224	};
225
226	timer {
227		compatible = "arm,armv8-timer";
228		interrupt-parent = <&gic>;
229		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
230					  IRQ_TYPE_LEVEL_LOW)>,
231			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
232					  IRQ_TYPE_LEVEL_LOW)>,
233			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
234					  IRQ_TYPE_LEVEL_LOW)>,
235			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
236					  IRQ_TYPE_LEVEL_LOW)>;
237	};
238
239	soc {
240		compatible = "simple-bus";
241		#address-cells = <2>;
242		#size-cells = <2>;
243		ranges;
244
245		crg_ctrl: crg_ctrl@fff35000 {
246			compatible = "hisilicon,hi3660-crgctrl", "syscon";
247			reg = <0x0 0xfff35000 0x0 0x1000>;
248			#clock-cells = <1>;
249		};
250
251		crg_rst: crg_rst_controller {
252			compatible = "hisilicon,hi3660-reset";
253			#reset-cells = <2>;
254			hisi,rst-syscon = <&crg_ctrl>;
255		};
256
257
258		pctrl: pctrl@e8a09000 {
259			compatible = "hisilicon,hi3660-pctrl", "syscon";
260			reg = <0x0 0xe8a09000 0x0 0x2000>;
261			#clock-cells = <1>;
262		};
263
264		pmuctrl: crg_ctrl@fff34000 {
265			compatible = "hisilicon,hi3660-pmuctrl", "syscon";
266			reg = <0x0 0xfff34000 0x0 0x1000>;
267			#clock-cells = <1>;
268		};
269
270		sctrl: sctrl@fff0a000 {
271			compatible = "hisilicon,hi3660-sctrl", "syscon";
272			reg = <0x0 0xfff0a000 0x0 0x1000>;
273			#clock-cells = <1>;
274		};
275
276		iomcu: iomcu@ffd7e000 {
277			compatible = "hisilicon,hi3660-iomcu", "syscon";
278			reg = <0x0 0xffd7e000 0x0 0x1000>;
279			#clock-cells = <1>;
280
281		};
282
283		iomcu_rst: reset {
284			compatible = "hisilicon,hi3660-reset";
285			hisi,rst-syscon = <&iomcu>;
286			#reset-cells = <2>;
287		};
288
289		dual_timer0: timer@fff14000 {
290			compatible = "arm,sp804", "arm,primecell";
291			reg = <0x0 0xfff14000 0x0 0x1000>;
292			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
293				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
294			clocks = <&crg_ctrl HI3660_OSC32K>,
295				 <&crg_ctrl HI3660_OSC32K>,
296				 <&crg_ctrl HI3660_OSC32K>;
297			clock-names = "timer1", "timer2", "apb_pclk";
298		};
299
300		i2c0: i2c@ffd71000 {
301			compatible = "snps,designware-i2c";
302			reg = <0x0 0xffd71000 0x0 0x1000>;
303			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
304			#address-cells = <1>;
305			#size-cells = <0>;
306			clock-frequency = <400000>;
307			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
308			resets = <&iomcu_rst 0x20 3>;
309			pinctrl-names = "default";
310			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
311			status = "disabled";
312		};
313
314		i2c1: i2c@ffd72000 {
315			compatible = "snps,designware-i2c";
316			reg = <0x0 0xffd72000 0x0 0x1000>;
317			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
318			#address-cells = <1>;
319			#size-cells = <0>;
320			clock-frequency = <400000>;
321			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
322			resets = <&iomcu_rst 0x20 4>;
323			pinctrl-names = "default";
324			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
325			status = "disabled";
326		};
327
328		i2c3: i2c@fdf0c000 {
329			compatible = "snps,designware-i2c";
330			reg = <0x0 0xfdf0c000 0x0 0x1000>;
331			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
332			#address-cells = <1>;
333			#size-cells = <0>;
334			clock-frequency = <400000>;
335			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
336			resets = <&crg_rst 0x78 7>;
337			pinctrl-names = "default";
338			pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
339			status = "disabled";
340		};
341
342		i2c7: i2c@fdf0b000 {
343			compatible = "snps,designware-i2c";
344			reg = <0x0 0xfdf0b000 0x0 0x1000>;
345			interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
346			#address-cells = <1>;
347			#size-cells = <0>;
348			clock-frequency = <400000>;
349			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
350			resets = <&crg_rst 0x60 14>;
351			pinctrl-names = "default";
352			pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
353			status = "disabled";
354		};
355
356		uart0: serial@fdf02000 {
357			compatible = "arm,pl011", "arm,primecell";
358			reg = <0x0 0xfdf02000 0x0 0x1000>;
359			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
360			clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
361				 <&crg_ctrl HI3660_PCLK>;
362			clock-names = "uartclk", "apb_pclk";
363			pinctrl-names = "default";
364			pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
365			status = "disabled";
366		};
367
368		uart1: serial@fdf00000 {
369			compatible = "arm,pl011", "arm,primecell";
370			reg = <0x0 0xfdf00000 0x0 0x1000>;
371			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
372			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
373				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
374			clock-names = "uartclk", "apb_pclk";
375			pinctrl-names = "default";
376			pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
377			status = "disabled";
378		};
379
380		uart2: serial@fdf03000 {
381			compatible = "arm,pl011", "arm,primecell";
382			reg = <0x0 0xfdf03000 0x0 0x1000>;
383			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
384			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
385				 <&crg_ctrl HI3660_PCLK>;
386			clock-names = "uartclk", "apb_pclk";
387			pinctrl-names = "default";
388			pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
389			status = "disabled";
390		};
391
392		uart3: serial@ffd74000 {
393			compatible = "arm,pl011", "arm,primecell";
394			reg = <0x0 0xffd74000 0x0 0x1000>;
395			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
396			clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
397				 <&crg_ctrl HI3660_PCLK>;
398			clock-names = "uartclk", "apb_pclk";
399			pinctrl-names = "default";
400			pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
401			status = "disabled";
402		};
403
404		uart4: serial@fdf01000 {
405			compatible = "arm,pl011", "arm,primecell";
406			reg = <0x0 0xfdf01000 0x0 0x1000>;
407			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
408			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
409				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
410			clock-names = "uartclk", "apb_pclk";
411			pinctrl-names = "default";
412			pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
413			status = "disabled";
414		};
415
416		uart5: serial@fdf05000 {
417			compatible = "arm,pl011", "arm,primecell";
418			reg = <0x0 0xfdf05000 0x0 0x1000>;
419			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
420			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
421				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
422			clock-names = "uartclk", "apb_pclk";
423			pinctrl-names = "default";
424			pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
425			status = "disabled";
426		};
427
428		uart6: serial@fff32000 {
429			compatible = "arm,pl011", "arm,primecell";
430			reg = <0x0 0xfff32000 0x0 0x1000>;
431			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
432			clocks = <&crg_ctrl HI3660_CLK_UART6>,
433				 <&crg_ctrl HI3660_PCLK>;
434			clock-names = "uartclk", "apb_pclk";
435			pinctrl-names = "default";
436			pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
437			status = "disabled";
438		};
439
440		dma0: dma@fdf30000 {
441			compatible = "hisilicon,k3-dma-1.0";
442			reg = <0x0 0xfdf30000 0x0 0x1000>;
443			#dma-cells = <1>;
444			dma-channels = <16>;
445			dma-requests = <32>;
446			dma-min-chan = <1>;
447			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
448			clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
449			dma-no-cci;
450			dma-type = "hi3660_dma";
451		};
452
453		rtc0: rtc@fff04000 {
454			compatible = "arm,pl031", "arm,primecell";
455			reg = <0x0 0Xfff04000 0x0 0x1000>;
456			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
457			clocks = <&crg_ctrl HI3660_PCLK>;
458			clock-names = "apb_pclk";
459		};
460
461		gpio0: gpio@e8a0b000 {
462			compatible = "arm,pl061", "arm,primecell";
463			reg = <0 0xe8a0b000 0 0x1000>;
464			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
465			gpio-controller;
466			#gpio-cells = <2>;
467			gpio-ranges = <&pmx0 1 0 7>;
468			interrupt-controller;
469			#interrupt-cells = <2>;
470			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
471			clock-names = "apb_pclk";
472		};
473
474		gpio1: gpio@e8a0c000 {
475			compatible = "arm,pl061", "arm,primecell";
476			reg = <0 0xe8a0c000 0 0x1000>;
477			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
478			gpio-controller;
479			#gpio-cells = <2>;
480			gpio-ranges = <&pmx0 1 7 7>;
481			interrupt-controller;
482			#interrupt-cells = <2>;
483			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
484			clock-names = "apb_pclk";
485		};
486
487		gpio2: gpio@e8a0d000 {
488			compatible = "arm,pl061", "arm,primecell";
489			reg = <0 0xe8a0d000 0 0x1000>;
490			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
491			gpio-controller;
492			#gpio-cells = <2>;
493			gpio-ranges = <&pmx0 0 14 8>;
494			interrupt-controller;
495			#interrupt-cells = <2>;
496			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
497			clock-names = "apb_pclk";
498		};
499
500		gpio3: gpio@e8a0e000 {
501			compatible = "arm,pl061", "arm,primecell";
502			reg = <0 0xe8a0e000 0 0x1000>;
503			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
504			gpio-controller;
505			#gpio-cells = <2>;
506			gpio-ranges = <&pmx0 0 22 8>;
507			interrupt-controller;
508			#interrupt-cells = <2>;
509			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
510			clock-names = "apb_pclk";
511		};
512
513		gpio4: gpio@e8a0f000 {
514			compatible = "arm,pl061", "arm,primecell";
515			reg = <0 0xe8a0f000 0 0x1000>;
516			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
517			gpio-controller;
518			#gpio-cells = <2>;
519			gpio-ranges = <&pmx0 0 30 8>;
520			interrupt-controller;
521			#interrupt-cells = <2>;
522			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
523			clock-names = "apb_pclk";
524		};
525
526		gpio5: gpio@e8a10000 {
527			compatible = "arm,pl061", "arm,primecell";
528			reg = <0 0xe8a10000 0 0x1000>;
529			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
530			gpio-controller;
531			#gpio-cells = <2>;
532			gpio-ranges = <&pmx0 0 38 8>;
533			interrupt-controller;
534			#interrupt-cells = <2>;
535			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
536			clock-names = "apb_pclk";
537		};
538
539		gpio6: gpio@e8a11000 {
540			compatible = "arm,pl061", "arm,primecell";
541			reg = <0 0xe8a11000 0 0x1000>;
542			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
543			gpio-controller;
544			#gpio-cells = <2>;
545			gpio-ranges = <&pmx0 0 46 8>;
546			interrupt-controller;
547			#interrupt-cells = <2>;
548			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
549			clock-names = "apb_pclk";
550		};
551
552		gpio7: gpio@e8a12000 {
553			compatible = "arm,pl061", "arm,primecell";
554			reg = <0 0xe8a12000 0 0x1000>;
555			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
556			gpio-controller;
557			#gpio-cells = <2>;
558			gpio-ranges = <&pmx0 0 54 8>;
559			interrupt-controller;
560			#interrupt-cells = <2>;
561			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
562			clock-names = "apb_pclk";
563		};
564
565		gpio8: gpio@e8a13000 {
566			compatible = "arm,pl061", "arm,primecell";
567			reg = <0 0xe8a13000 0 0x1000>;
568			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
569			gpio-controller;
570			#gpio-cells = <2>;
571			gpio-ranges = <&pmx0 0 62 8>;
572			interrupt-controller;
573			#interrupt-cells = <2>;
574			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
575			clock-names = "apb_pclk";
576		};
577
578		gpio9: gpio@e8a14000 {
579			compatible = "arm,pl061", "arm,primecell";
580			reg = <0 0xe8a14000 0 0x1000>;
581			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
582			gpio-controller;
583			#gpio-cells = <2>;
584			gpio-ranges = <&pmx0 0 70 8>;
585			interrupt-controller;
586			#interrupt-cells = <2>;
587			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
588			clock-names = "apb_pclk";
589		};
590
591		gpio10: gpio@e8a15000 {
592			compatible = "arm,pl061", "arm,primecell";
593			reg = <0 0xe8a15000 0 0x1000>;
594			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
595			gpio-controller;
596			#gpio-cells = <2>;
597			gpio-ranges = <&pmx0 0 78 8>;
598			interrupt-controller;
599			#interrupt-cells = <2>;
600			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
601			clock-names = "apb_pclk";
602		};
603
604		gpio11: gpio@e8a16000 {
605			compatible = "arm,pl061", "arm,primecell";
606			reg = <0 0xe8a16000 0 0x1000>;
607			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
608			gpio-controller;
609			#gpio-cells = <2>;
610			gpio-ranges = <&pmx0 0 86 8>;
611			interrupt-controller;
612			#interrupt-cells = <2>;
613			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
614			clock-names = "apb_pclk";
615		};
616
617		gpio12: gpio@e8a17000 {
618			compatible = "arm,pl061", "arm,primecell";
619			reg = <0 0xe8a17000 0 0x1000>;
620			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
621			gpio-controller;
622			#gpio-cells = <2>;
623			gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
624			interrupt-controller;
625			#interrupt-cells = <2>;
626			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
627			clock-names = "apb_pclk";
628		};
629
630		gpio13: gpio@e8a18000 {
631			compatible = "arm,pl061", "arm,primecell";
632			reg = <0 0xe8a18000 0 0x1000>;
633			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
634			gpio-controller;
635			#gpio-cells = <2>;
636			gpio-ranges = <&pmx0 0 102 8>;
637			interrupt-controller;
638			#interrupt-cells = <2>;
639			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
640			clock-names = "apb_pclk";
641		};
642
643		gpio14: gpio@e8a19000 {
644			compatible = "arm,pl061", "arm,primecell";
645			reg = <0 0xe8a19000 0 0x1000>;
646			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
647			gpio-controller;
648			#gpio-cells = <2>;
649			gpio-ranges = <&pmx0 0 110 8>;
650			interrupt-controller;
651			#interrupt-cells = <2>;
652			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
653			clock-names = "apb_pclk";
654		};
655
656		gpio15: gpio@e8a1a000 {
657			compatible = "arm,pl061", "arm,primecell";
658			reg = <0 0xe8a1a000 0 0x1000>;
659			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
660			gpio-controller;
661			#gpio-cells = <2>;
662			gpio-ranges = <&pmx0 0 118 6>;
663			interrupt-controller;
664			#interrupt-cells = <2>;
665			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
666			clock-names = "apb_pclk";
667		};
668
669		gpio16: gpio@e8a1b000 {
670			compatible = "arm,pl061", "arm,primecell";
671			reg = <0 0xe8a1b000 0 0x1000>;
672			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
673			gpio-controller;
674			#gpio-cells = <2>;
675			interrupt-controller;
676			#interrupt-cells = <2>;
677			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
678			clock-names = "apb_pclk";
679		};
680
681		gpio17: gpio@e8a1c000 {
682			compatible = "arm,pl061", "arm,primecell";
683			reg = <0 0xe8a1c000 0 0x1000>;
684			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
685			gpio-controller;
686			#gpio-cells = <2>;
687			interrupt-controller;
688			#interrupt-cells = <2>;
689			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
690			clock-names = "apb_pclk";
691		};
692
693		gpio18: gpio@ff3b4000 {
694			compatible = "arm,pl061", "arm,primecell";
695			reg = <0 0xff3b4000 0 0x1000>;
696			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
697			gpio-controller;
698			#gpio-cells = <2>;
699			gpio-ranges = <&pmx2 0 0 8>;
700			interrupt-controller;
701			#interrupt-cells = <2>;
702			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
703			clock-names = "apb_pclk";
704		};
705
706		gpio19: gpio@ff3b5000 {
707			compatible = "arm,pl061", "arm,primecell";
708			reg = <0 0xff3b5000 0 0x1000>;
709			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
710			gpio-controller;
711			#gpio-cells = <2>;
712			gpio-ranges = <&pmx2 0 8 4>;
713			interrupt-controller;
714			#interrupt-cells = <2>;
715			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
716			clock-names = "apb_pclk";
717		};
718
719		gpio20: gpio@e8a1f000 {
720			compatible = "arm,pl061", "arm,primecell";
721			reg = <0 0xe8a1f000 0 0x1000>;
722			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
723			gpio-controller;
724			#gpio-cells = <2>;
725			gpio-ranges = <&pmx1 0 0 6>;
726			interrupt-controller;
727			#interrupt-cells = <2>;
728			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
729			clock-names = "apb_pclk";
730		};
731
732		gpio21: gpio@e8a20000 {
733			compatible = "arm,pl061", "arm,primecell";
734			reg = <0 0xe8a20000 0 0x1000>;
735			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
736			gpio-controller;
737			#gpio-cells = <2>;
738			interrupt-controller;
739			#interrupt-cells = <2>;
740			gpio-ranges = <&pmx3 0 0 6>;
741			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
742			clock-names = "apb_pclk";
743		};
744
745		gpio22: gpio@fff0b000 {
746			compatible = "arm,pl061", "arm,primecell";
747			reg = <0 0xfff0b000 0 0x1000>;
748			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
749			gpio-controller;
750			#gpio-cells = <2>;
751			/* GPIO176 */
752			gpio-ranges = <&pmx4 2 0 6>;
753			interrupt-controller;
754			#interrupt-cells = <2>;
755			clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
756			clock-names = "apb_pclk";
757		};
758
759		gpio23: gpio@fff0c000 {
760			compatible = "arm,pl061", "arm,primecell";
761			reg = <0 0xfff0c000 0 0x1000>;
762			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
763			gpio-controller;
764			#gpio-cells = <2>;
765			/* GPIO184 */
766			gpio-ranges = <&pmx4 0 6 7>;
767			interrupt-controller;
768			#interrupt-cells = <2>;
769			clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
770			clock-names = "apb_pclk";
771		};
772
773		gpio24: gpio@fff0d000 {
774			compatible = "arm,pl061", "arm,primecell";
775			reg = <0 0xfff0d000 0 0x1000>;
776			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
777			gpio-controller;
778			#gpio-cells = <2>;
779			/* GPIO192 */
780			gpio-ranges = <&pmx4 0 13 8>;
781			interrupt-controller;
782			#interrupt-cells = <2>;
783			clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
784			clock-names = "apb_pclk";
785		};
786
787		gpio25: gpio@fff0e000 {
788			compatible = "arm,pl061", "arm,primecell";
789			reg = <0 0xfff0e000 0 0x1000>;
790			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
791			gpio-controller;
792			#gpio-cells = <2>;
793			/* GPIO200 */
794			gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
795			interrupt-controller;
796			#interrupt-cells = <2>;
797			clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
798			clock-names = "apb_pclk";
799		};
800
801		gpio26: gpio@fff0f000 {
802			compatible = "arm,pl061", "arm,primecell";
803			reg = <0 0xfff0f000 0 0x1000>;
804			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
805			gpio-controller;
806			#gpio-cells = <2>;
807			/* GPIO208 */
808			gpio-ranges = <&pmx4 0 28 8>;
809			interrupt-controller;
810			#interrupt-cells = <2>;
811			clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
812			clock-names = "apb_pclk";
813		};
814
815		gpio27: gpio@fff10000 {
816			compatible = "arm,pl061", "arm,primecell";
817			reg = <0 0xfff10000 0 0x1000>;
818			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
819			gpio-controller;
820			#gpio-cells = <2>;
821			/* GPIO216 */
822			gpio-ranges = <&pmx4 0 36 6>;
823			interrupt-controller;
824			#interrupt-cells = <2>;
825			clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
826			clock-names = "apb_pclk";
827		};
828
829		gpio28: gpio@fff1d000 {
830			compatible = "arm,pl061", "arm,primecell";
831			reg = <0 0xfff1d000 0 0x1000>;
832			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
833			gpio-controller;
834			#gpio-cells = <2>;
835			interrupt-controller;
836			#interrupt-cells = <2>;
837			clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
838			clock-names = "apb_pclk";
839		};
840
841		spi2: spi@ffd68000 {
842			compatible = "arm,pl022", "arm,primecell";
843			reg = <0x0 0xffd68000 0x0 0x1000>;
844			#address-cells = <1>;
845			#size-cells = <0>;
846			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
847			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
848			clock-names = "apb_pclk";
849			pinctrl-names = "default";
850			pinctrl-0 = <&spi2_pmx_func>;
851			num-cs = <1>;
852			cs-gpios = <&gpio27 2 0>;
853			status = "disabled";
854		};
855
856		spi3: spi@ff3b3000 {
857			compatible = "arm,pl022", "arm,primecell";
858			reg = <0x0 0xff3b3000 0x0 0x1000>;
859			#address-cells = <1>;
860			#size-cells = <0>;
861			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
862			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
863			clock-names = "apb_pclk";
864			pinctrl-names = "default";
865			pinctrl-0 = <&spi3_pmx_func>;
866			num-cs = <1>;
867			cs-gpios = <&gpio18 5 0>;
868			status = "disabled";
869		};
870
871		pcie@f4000000 {
872			compatible = "hisilicon,kirin960-pcie";
873			reg = <0x0 0xf4000000 0x0 0x1000>,
874			      <0x0 0xff3fe000 0x0 0x1000>,
875			      <0x0 0xf3f20000 0x0 0x40000>,
876			      <0x0 0xf5000000 0x0 0x2000>;
877			reg-names = "dbi", "apb", "phy", "config";
878			bus-range = <0x0  0x1>;
879			#address-cells = <3>;
880			#size-cells = <2>;
881			device_type = "pci";
882			ranges = <0x02000000 0x0 0x00000000
883				  0x0 0xf6000000
884				  0x0 0x02000000>;
885			num-lanes = <1>;
886			#interrupt-cells = <1>;
887			interrupt-map-mask = <0xf800 0 0 7>;
888			interrupt-map = <0x0 0 0 1
889					 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
890					<0x0 0 0 2
891					 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
892					<0x0 0 0 3
893					 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
894					<0x0 0 0 4
895					 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
896			clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
897				 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
898				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
899				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
900				 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
901			clock-names = "pcie_phy_ref", "pcie_aux",
902				      "pcie_apb_phy", "pcie_apb_sys",
903				      "pcie_aclk";
904			reset-gpios = <&gpio11 1 0 >;
905		};
906
907		/* SD */
908		dwmmc1: dwmmc1@ff37f000 {
909			#address-cells = <1>;
910			#size-cells = <0>;
911			cd-inverted;
912			compatible = "hisilicon,hi3660-dw-mshc";
913			num-slots = <1>;
914			bus-width = <0x4>;
915			disable-wp;
916			cap-sd-highspeed;
917			supports-highspeed;
918			card-detect-delay = <200>;
919			reg = <0x0 0xff37f000 0x0 0x1000>;
920			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
921			clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
922				<&crg_ctrl HI3660_HCLK_GATE_SD>;
923			clock-names = "ciu", "biu";
924			clock-frequency = <3200000>;
925			resets = <&crg_rst 0x94 18>;
926			reset-names = "reset";
927			cd-gpios = <&gpio25 3 0>;
928			hisilicon,peripheral-syscon = <&sctrl>;
929			pinctrl-names = "default";
930			pinctrl-0 = <&sd_pmx_func
931				     &sd_clk_cfg_func
932				     &sd_cfg_func>;
933			sd-uhs-sdr12;
934			sd-uhs-sdr25;
935			sd-uhs-sdr50;
936			sd-uhs-sdr104;
937			status = "disabled";
938
939			slot@0 {
940				reg = <0x0>;
941				bus-width = <4>;
942				disable-wp;
943			};
944		};
945
946		/* SDIO */
947		dwmmc2: dwmmc2@ff3ff000 {
948			compatible = "hisilicon,hi3660-dw-mshc";
949			reg = <0x0 0xff3ff000 0x0 0x1000>;
950			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
951			num-slots = <1>;
952			clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
953				 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
954			clock-names = "ciu", "biu";
955			resets = <&crg_rst 0x94 20>;
956			reset-names = "reset";
957			card-detect-delay = <200>;
958			supports-highspeed;
959			keep-power-in-suspend;
960			pinctrl-names = "default";
961			pinctrl-0 = <&sdio_pmx_func
962				     &sdio_clk_cfg_func
963				     &sdio_cfg_func>;
964			status = "disabled";
965		};
966
967		watchdog0: watchdog@e8a06000 {
968			compatible = "arm,sp805-wdt", "arm,primecell";
969			reg = <0x0 0xe8a06000 0x0 0x1000>;
970			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
971			clocks = <&crg_ctrl HI3660_OSC32K>;
972			clock-names = "apb_pclk";
973		};
974
975		watchdog1: watchdog@e8a07000 {
976			compatible = "arm,sp805-wdt", "arm,primecell";
977			reg = <0x0 0xe8a07000 0x0 0x1000>;
978			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
979			clocks = <&crg_ctrl HI3660_OSC32K>;
980			clock-names = "apb_pclk";
981		};
982
983		tsensor: tsensor@fff30000 {
984			compatible = "hisilicon,hi3660-tsensor";
985			reg = <0x0 0xfff30000 0x0 0x1000>;
986			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
987			#thermal-sensor-cells = <1>;
988		};
989	};
990};
991