1/* 2 * dts file for Hisilicon Hi3660 SoC 3 * 4 * Copyright (C) 2016, Hisilicon Ltd. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/hi3660-clock.h> 9 10/ { 11 compatible = "hisilicon,hi3660"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 psci { 17 compatible = "arm,psci-0.2"; 18 method = "smc"; 19 }; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53", "arm,armv8"; 58 device_type = "cpu"; 59 reg = <0x0 0x0>; 60 enable-method = "psci"; 61 }; 62 63 cpu1: cpu@1 { 64 compatible = "arm,cortex-a53", "arm,armv8"; 65 device_type = "cpu"; 66 reg = <0x0 0x1>; 67 enable-method = "psci"; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 device_type = "cpu"; 73 reg = <0x0 0x2>; 74 enable-method = "psci"; 75 }; 76 77 cpu3: cpu@3 { 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 device_type = "cpu"; 80 reg = <0x0 0x3>; 81 enable-method = "psci"; 82 }; 83 84 cpu4: cpu@100 { 85 compatible = "arm,cortex-a73", "arm,armv8"; 86 device_type = "cpu"; 87 reg = <0x0 0x100>; 88 enable-method = "psci"; 89 }; 90 91 cpu5: cpu@101 { 92 compatible = "arm,cortex-a73", "arm,armv8"; 93 device_type = "cpu"; 94 reg = <0x0 0x101>; 95 enable-method = "psci"; 96 }; 97 98 cpu6: cpu@102 { 99 compatible = "arm,cortex-a73", "arm,armv8"; 100 device_type = "cpu"; 101 reg = <0x0 0x102>; 102 enable-method = "psci"; 103 }; 104 105 cpu7: cpu@103 { 106 compatible = "arm,cortex-a73", "arm,armv8"; 107 device_type = "cpu"; 108 reg = <0x0 0x103>; 109 enable-method = "psci"; 110 }; 111 }; 112 113 gic: interrupt-controller@e82b0000 { 114 compatible = "arm,gic-400"; 115 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 116 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 117 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 118 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 119 #address-cells = <0>; 120 #interrupt-cells = <3>; 121 interrupt-controller; 122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 123 IRQ_TYPE_LEVEL_HIGH)>; 124 }; 125 126 timer { 127 compatible = "arm,armv8-timer"; 128 interrupt-parent = <&gic>; 129 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 130 IRQ_TYPE_LEVEL_LOW)>, 131 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 132 IRQ_TYPE_LEVEL_LOW)>, 133 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 134 IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 136 IRQ_TYPE_LEVEL_LOW)>; 137 }; 138 139 soc { 140 compatible = "simple-bus"; 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 145 crg_ctrl: crg_ctrl@fff35000 { 146 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 147 reg = <0x0 0xfff35000 0x0 0x1000>; 148 #clock-cells = <1>; 149 }; 150 151 crg_rst: crg_rst_controller { 152 compatible = "hisilicon,hi3660-reset"; 153 #reset-cells = <2>; 154 hisi,rst-syscon = <&crg_ctrl>; 155 }; 156 157 158 pctrl: pctrl@e8a09000 { 159 compatible = "hisilicon,hi3660-pctrl", "syscon"; 160 reg = <0x0 0xe8a09000 0x0 0x2000>; 161 #clock-cells = <1>; 162 }; 163 164 pmuctrl: crg_ctrl@fff34000 { 165 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 166 reg = <0x0 0xfff34000 0x0 0x1000>; 167 #clock-cells = <1>; 168 }; 169 170 sctrl: sctrl@fff0a000 { 171 compatible = "hisilicon,hi3660-sctrl", "syscon"; 172 reg = <0x0 0xfff0a000 0x0 0x1000>; 173 #clock-cells = <1>; 174 }; 175 176 iomcu: iomcu@ffd7e000 { 177 compatible = "hisilicon,hi3660-iomcu", "syscon"; 178 reg = <0x0 0xffd7e000 0x0 0x1000>; 179 #clock-cells = <1>; 180 181 }; 182 183 iomcu_rst: reset { 184 compatible = "hisilicon,hi3660-reset"; 185 hisi,rst-syscon = <&iomcu>; 186 #reset-cells = <2>; 187 }; 188 189 i2c0: i2c@ffd71000 { 190 compatible = "snps,designware-i2c"; 191 reg = <0x0 0xffd71000 0x0 0x1000>; 192 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 clock-frequency = <400000>; 196 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 197 resets = <&iomcu_rst 0x20 3>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 200 status = "disabled"; 201 }; 202 203 i2c1: i2c@ffd72000 { 204 compatible = "snps,designware-i2c"; 205 reg = <0x0 0xffd72000 0x0 0x1000>; 206 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 clock-frequency = <400000>; 210 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 211 resets = <&iomcu_rst 0x20 4>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 214 status = "disabled"; 215 }; 216 217 i2c3: i2c@fdf0c000 { 218 compatible = "snps,designware-i2c"; 219 reg = <0x0 0xfdf0c000 0x0 0x1000>; 220 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 clock-frequency = <400000>; 224 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 225 resets = <&crg_rst 0x78 7>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 228 status = "disabled"; 229 }; 230 231 i2c7: i2c@fdf0b000 { 232 compatible = "snps,designware-i2c"; 233 reg = <0x0 0xfdf0b000 0x0 0x1000>; 234 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 clock-frequency = <400000>; 238 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 239 resets = <&crg_rst 0x60 14>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 242 status = "disabled"; 243 }; 244 245 uart5: serial@fdf05000 { 246 compatible = "arm,pl011", "arm,primecell"; 247 reg = <0x0 0xfdf05000 0x0 0x1000>; 248 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 250 <&crg_ctrl HI3660_CLK_GATE_UART5>; 251 clock-names = "uartclk", "apb_pclk"; 252 status = "disabled"; 253 }; 254 }; 255}; 256