1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3660 SoC 4 * 5 * Copyright (C) 2016, HiSilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/hi3660-clock.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 compatible = "hisilicon,hi3660"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 psci { 19 compatible = "arm,psci-0.2"; 20 method = "smc"; 21 }; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 cpu-map { 28 cluster0 { 29 core0 { 30 cpu = <&cpu0>; 31 }; 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 core2 { 36 cpu = <&cpu2>; 37 }; 38 core3 { 39 cpu = <&cpu3>; 40 }; 41 }; 42 cluster1 { 43 core0 { 44 cpu = <&cpu4>; 45 }; 46 core1 { 47 cpu = <&cpu5>; 48 }; 49 core2 { 50 cpu = <&cpu6>; 51 }; 52 core3 { 53 cpu = <&cpu7>; 54 }; 55 }; 56 }; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53"; 60 device_type = "cpu"; 61 reg = <0x0 0x0>; 62 enable-method = "psci"; 63 next-level-cache = <&A53_L2>; 64 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 65 capacity-dmips-mhz = <592>; 66 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 67 operating-points-v2 = <&cluster0_opp>; 68 #cooling-cells = <2>; 69 dynamic-power-coefficient = <110>; 70 }; 71 72 cpu1: cpu@1 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 reg = <0x0 0x1>; 76 enable-method = "psci"; 77 next-level-cache = <&A53_L2>; 78 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 79 capacity-dmips-mhz = <592>; 80 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 81 operating-points-v2 = <&cluster0_opp>; 82 #cooling-cells = <2>; 83 }; 84 85 cpu2: cpu@2 { 86 compatible = "arm,cortex-a53"; 87 device_type = "cpu"; 88 reg = <0x0 0x2>; 89 enable-method = "psci"; 90 next-level-cache = <&A53_L2>; 91 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 92 capacity-dmips-mhz = <592>; 93 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 94 operating-points-v2 = <&cluster0_opp>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu3: cpu@3 { 99 compatible = "arm,cortex-a53"; 100 device_type = "cpu"; 101 reg = <0x0 0x3>; 102 enable-method = "psci"; 103 next-level-cache = <&A53_L2>; 104 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 105 capacity-dmips-mhz = <592>; 106 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 107 operating-points-v2 = <&cluster0_opp>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu4: cpu@100 { 112 compatible = "arm,cortex-a73"; 113 device_type = "cpu"; 114 reg = <0x0 0x100>; 115 enable-method = "psci"; 116 next-level-cache = <&A73_L2>; 117 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 118 capacity-dmips-mhz = <1024>; 119 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 120 operating-points-v2 = <&cluster1_opp>; 121 #cooling-cells = <2>; 122 dynamic-power-coefficient = <550>; 123 }; 124 125 cpu5: cpu@101 { 126 compatible = "arm,cortex-a73"; 127 device_type = "cpu"; 128 reg = <0x0 0x101>; 129 enable-method = "psci"; 130 next-level-cache = <&A73_L2>; 131 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 132 capacity-dmips-mhz = <1024>; 133 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 134 operating-points-v2 = <&cluster1_opp>; 135 #cooling-cells = <2>; 136 }; 137 138 cpu6: cpu@102 { 139 compatible = "arm,cortex-a73"; 140 device_type = "cpu"; 141 reg = <0x0 0x102>; 142 enable-method = "psci"; 143 next-level-cache = <&A73_L2>; 144 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 145 capacity-dmips-mhz = <1024>; 146 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 147 operating-points-v2 = <&cluster1_opp>; 148 #cooling-cells = <2>; 149 }; 150 151 cpu7: cpu@103 { 152 compatible = "arm,cortex-a73"; 153 device_type = "cpu"; 154 reg = <0x0 0x103>; 155 enable-method = "psci"; 156 next-level-cache = <&A73_L2>; 157 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 158 capacity-dmips-mhz = <1024>; 159 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 160 operating-points-v2 = <&cluster1_opp>; 161 #cooling-cells = <2>; 162 }; 163 164 idle-states { 165 entry-method = "psci"; 166 167 CPU_SLEEP_0: cpu-sleep-0 { 168 compatible = "arm,idle-state"; 169 local-timer-stop; 170 arm,psci-suspend-param = <0x0010000>; 171 entry-latency-us = <400>; 172 exit-latency-us = <650>; 173 min-residency-us = <1500>; 174 }; 175 CLUSTER_SLEEP_0: cluster-sleep-0 { 176 compatible = "arm,idle-state"; 177 local-timer-stop; 178 arm,psci-suspend-param = <0x1010000>; 179 entry-latency-us = <500>; 180 exit-latency-us = <1600>; 181 min-residency-us = <3500>; 182 }; 183 184 185 CPU_SLEEP_1: cpu-sleep-1 { 186 compatible = "arm,idle-state"; 187 local-timer-stop; 188 arm,psci-suspend-param = <0x0010000>; 189 entry-latency-us = <400>; 190 exit-latency-us = <550>; 191 min-residency-us = <1500>; 192 }; 193 194 CLUSTER_SLEEP_1: cluster-sleep-1 { 195 compatible = "arm,idle-state"; 196 local-timer-stop; 197 arm,psci-suspend-param = <0x1010000>; 198 entry-latency-us = <800>; 199 exit-latency-us = <2900>; 200 min-residency-us = <3500>; 201 }; 202 }; 203 204 A53_L2: l2-cache0 { 205 compatible = "cache"; 206 cache-level = <2>; 207 }; 208 209 A73_L2: l2-cache1 { 210 compatible = "cache"; 211 cache-level = <2>; 212 }; 213 }; 214 215 cluster0_opp: opp-table-0 { 216 compatible = "operating-points-v2"; 217 opp-shared; 218 219 opp00 { 220 opp-hz = /bits/ 64 <533000000>; 221 opp-microvolt = <700000>; 222 clock-latency-ns = <300000>; 223 }; 224 225 opp01 { 226 opp-hz = /bits/ 64 <999000000>; 227 opp-microvolt = <800000>; 228 clock-latency-ns = <300000>; 229 }; 230 231 opp02 { 232 opp-hz = /bits/ 64 <1402000000>; 233 opp-microvolt = <900000>; 234 clock-latency-ns = <300000>; 235 }; 236 237 opp03 { 238 opp-hz = /bits/ 64 <1709000000>; 239 opp-microvolt = <1000000>; 240 clock-latency-ns = <300000>; 241 }; 242 243 opp04 { 244 opp-hz = /bits/ 64 <1844000000>; 245 opp-microvolt = <1100000>; 246 clock-latency-ns = <300000>; 247 }; 248 }; 249 250 cluster1_opp: opp-table-1 { 251 compatible = "operating-points-v2"; 252 opp-shared; 253 254 opp10 { 255 opp-hz = /bits/ 64 <903000000>; 256 opp-microvolt = <700000>; 257 clock-latency-ns = <300000>; 258 }; 259 260 opp11 { 261 opp-hz = /bits/ 64 <1421000000>; 262 opp-microvolt = <800000>; 263 clock-latency-ns = <300000>; 264 }; 265 266 opp12 { 267 opp-hz = /bits/ 64 <1805000000>; 268 opp-microvolt = <900000>; 269 clock-latency-ns = <300000>; 270 }; 271 272 opp13 { 273 opp-hz = /bits/ 64 <2112000000>; 274 opp-microvolt = <1000000>; 275 clock-latency-ns = <300000>; 276 }; 277 278 opp14 { 279 opp-hz = /bits/ 64 <2362000000>; 280 opp-microvolt = <1100000>; 281 clock-latency-ns = <300000>; 282 }; 283 }; 284 285 gic: interrupt-controller@e82b0000 { 286 compatible = "arm,gic-400"; 287 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 288 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 289 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 290 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 291 #address-cells = <0>; 292 #interrupt-cells = <3>; 293 interrupt-controller; 294 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 295 IRQ_TYPE_LEVEL_HIGH)>; 296 }; 297 298 a53-pmu { 299 compatible = "arm,cortex-a53-pmu"; 300 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 304 interrupt-affinity = <&cpu0>, 305 <&cpu1>, 306 <&cpu2>, 307 <&cpu3>; 308 }; 309 310 a73-pmu { 311 compatible = "arm,cortex-a73-pmu"; 312 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 316 interrupt-affinity = <&cpu4>, 317 <&cpu5>, 318 <&cpu6>, 319 <&cpu7>; 320 }; 321 322 timer { 323 compatible = "arm,armv8-timer"; 324 interrupt-parent = <&gic>; 325 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 326 IRQ_TYPE_LEVEL_LOW)>, 327 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 328 IRQ_TYPE_LEVEL_LOW)>, 329 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 330 IRQ_TYPE_LEVEL_LOW)>, 331 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 332 IRQ_TYPE_LEVEL_LOW)>; 333 }; 334 335 soc { 336 compatible = "simple-bus"; 337 #address-cells = <2>; 338 #size-cells = <2>; 339 ranges; 340 341 crg_ctrl: crg_ctrl@fff35000 { 342 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 343 reg = <0x0 0xfff35000 0x0 0x1000>; 344 #clock-cells = <1>; 345 }; 346 347 crg_rst: crg_rst_controller { 348 compatible = "hisilicon,hi3660-reset"; 349 #reset-cells = <2>; 350 hisi,rst-syscon = <&crg_ctrl>; 351 }; 352 353 354 pctrl: pctrl@e8a09000 { 355 compatible = "hisilicon,hi3660-pctrl", "syscon"; 356 reg = <0x0 0xe8a09000 0x0 0x2000>; 357 #clock-cells = <1>; 358 }; 359 360 pmuctrl: crg_ctrl@fff34000 { 361 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 362 reg = <0x0 0xfff34000 0x0 0x1000>; 363 #clock-cells = <1>; 364 }; 365 366 sctrl: sctrl@fff0a000 { 367 compatible = "hisilicon,hi3660-sctrl", "syscon"; 368 reg = <0x0 0xfff0a000 0x0 0x1000>; 369 #clock-cells = <1>; 370 }; 371 372 iomcu: iomcu@ffd7e000 { 373 compatible = "hisilicon,hi3660-iomcu", "syscon"; 374 reg = <0x0 0xffd7e000 0x0 0x1000>; 375 #clock-cells = <1>; 376 377 }; 378 379 iomcu_rst: reset { 380 compatible = "hisilicon,hi3660-reset"; 381 hisi,rst-syscon = <&iomcu>; 382 #reset-cells = <2>; 383 }; 384 385 mailbox: mailbox@e896b000 { 386 compatible = "hisilicon,hi3660-mbox"; 387 reg = <0x0 0xe896b000 0x0 0x1000>; 388 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 390 #mbox-cells = <3>; 391 }; 392 393 stub_clock: stub_clock@e896b500 { 394 compatible = "hisilicon,hi3660-stub-clk"; 395 reg = <0x0 0xe896b500 0x0 0x0100>; 396 #clock-cells = <1>; 397 mboxes = <&mailbox 13 3 0>; 398 }; 399 400 dual_timer0: timer@fff14000 { 401 compatible = "arm,sp804", "arm,primecell"; 402 reg = <0x0 0xfff14000 0x0 0x1000>; 403 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&crg_ctrl HI3660_OSC32K>, 406 <&crg_ctrl HI3660_OSC32K>, 407 <&crg_ctrl HI3660_OSC32K>; 408 clock-names = "timer1", "timer2", "apb_pclk"; 409 }; 410 411 i2c0: i2c@ffd71000 { 412 compatible = "snps,designware-i2c"; 413 reg = <0x0 0xffd71000 0x0 0x1000>; 414 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 clock-frequency = <400000>; 418 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 419 resets = <&iomcu_rst 0x20 3>; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 422 status = "disabled"; 423 }; 424 425 i2c1: i2c@ffd72000 { 426 compatible = "snps,designware-i2c"; 427 reg = <0x0 0xffd72000 0x0 0x1000>; 428 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 clock-frequency = <400000>; 432 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 433 resets = <&iomcu_rst 0x20 4>; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 436 status = "disabled"; 437 }; 438 439 i2c3: i2c@fdf0c000 { 440 compatible = "snps,designware-i2c"; 441 reg = <0x0 0xfdf0c000 0x0 0x1000>; 442 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 clock-frequency = <400000>; 446 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 447 resets = <&crg_rst 0x78 7>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 450 status = "disabled"; 451 }; 452 453 i2c7: i2c@fdf0b000 { 454 compatible = "snps,designware-i2c"; 455 reg = <0x0 0xfdf0b000 0x0 0x1000>; 456 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clock-frequency = <400000>; 460 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 461 resets = <&crg_rst 0x60 14>; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 464 status = "disabled"; 465 }; 466 467 uart0: serial@fdf02000 { 468 compatible = "arm,pl011", "arm,primecell"; 469 reg = <0x0 0xfdf02000 0x0 0x1000>; 470 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 472 <&crg_ctrl HI3660_PCLK>; 473 clock-names = "uartclk", "apb_pclk"; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 476 status = "disabled"; 477 }; 478 479 uart1: serial@fdf00000 { 480 compatible = "arm,pl011", "arm,primecell"; 481 reg = <0x0 0xfdf00000 0x0 0x1000>; 482 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 483 dma-names = "rx", "tx"; 484 dmas = <&dma0 2 &dma0 3>; 485 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 486 <&crg_ctrl HI3660_CLK_GATE_UART1>; 487 clock-names = "uartclk", "apb_pclk"; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 490 status = "disabled"; 491 }; 492 493 uart2: serial@fdf03000 { 494 compatible = "arm,pl011", "arm,primecell"; 495 reg = <0x0 0xfdf03000 0x0 0x1000>; 496 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 497 dma-names = "rx", "tx"; 498 dmas = <&dma0 4 &dma0 5>; 499 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 500 <&crg_ctrl HI3660_PCLK>; 501 clock-names = "uartclk", "apb_pclk"; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 504 status = "disabled"; 505 }; 506 507 uart3: serial@ffd74000 { 508 compatible = "arm,pl011", "arm,primecell"; 509 reg = <0x0 0xffd74000 0x0 0x1000>; 510 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 512 <&crg_ctrl HI3660_PCLK>; 513 clock-names = "uartclk", "apb_pclk"; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 516 status = "disabled"; 517 }; 518 519 uart4: serial@fdf01000 { 520 compatible = "arm,pl011", "arm,primecell"; 521 reg = <0x0 0xfdf01000 0x0 0x1000>; 522 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 523 dma-names = "rx", "tx"; 524 dmas = <&dma0 6 &dma0 7>; 525 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 526 <&crg_ctrl HI3660_CLK_GATE_UART4>; 527 clock-names = "uartclk", "apb_pclk"; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 530 status = "disabled"; 531 }; 532 533 uart5: serial@fdf05000 { 534 compatible = "arm,pl011", "arm,primecell"; 535 reg = <0x0 0xfdf05000 0x0 0x1000>; 536 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 537 dma-names = "rx", "tx"; 538 dmas = <&dma0 8 &dma0 9>; 539 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 540 <&crg_ctrl HI3660_CLK_GATE_UART5>; 541 clock-names = "uartclk", "apb_pclk"; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 544 status = "disabled"; 545 }; 546 547 uart6: serial@fff32000 { 548 compatible = "arm,pl011", "arm,primecell"; 549 reg = <0x0 0xfff32000 0x0 0x1000>; 550 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&crg_ctrl HI3660_CLK_UART6>, 552 <&crg_ctrl HI3660_PCLK>; 553 clock-names = "uartclk", "apb_pclk"; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 556 status = "disabled"; 557 }; 558 559 dma0: dma@fdf30000 { 560 compatible = "hisilicon,k3-dma-1.0"; 561 reg = <0x0 0xfdf30000 0x0 0x1000>; 562 #dma-cells = <1>; 563 dma-channels = <16>; 564 dma-requests = <32>; 565 dma-channel-mask = <0xfffe>; 566 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 568 dma-no-cci; 569 dma-type = "hi3660_dma"; 570 }; 571 572 asp_dmac: dma-controller@e804b000 { 573 compatible = "hisilicon,hisi-pcm-asp-dma-1.0"; 574 reg = <0x0 0xe804b000 0x0 0x1000>; 575 #dma-cells = <1>; 576 dma-channels = <16>; 577 dma-requests = <32>; 578 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 579 interrupt-names = "asp_dma_irq"; 580 }; 581 582 rtc0: rtc@fff04000 { 583 compatible = "arm,pl031", "arm,primecell"; 584 reg = <0x0 0Xfff04000 0x0 0x1000>; 585 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&crg_ctrl HI3660_PCLK>; 587 clock-names = "apb_pclk"; 588 }; 589 590 gpio0: gpio@e8a0b000 { 591 compatible = "arm,pl061", "arm,primecell"; 592 reg = <0 0xe8a0b000 0 0x1000>; 593 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 594 gpio-controller; 595 #gpio-cells = <2>; 596 gpio-ranges = <&pmx0 1 0 7>; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 600 clock-names = "apb_pclk"; 601 }; 602 603 gpio1: gpio@e8a0c000 { 604 compatible = "arm,pl061", "arm,primecell"; 605 reg = <0 0xe8a0c000 0 0x1000>; 606 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 607 gpio-controller; 608 #gpio-cells = <2>; 609 gpio-ranges = <&pmx0 1 7 7>; 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 613 clock-names = "apb_pclk"; 614 }; 615 616 gpio2: gpio@e8a0d000 { 617 compatible = "arm,pl061", "arm,primecell"; 618 reg = <0 0xe8a0d000 0 0x1000>; 619 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 620 gpio-controller; 621 #gpio-cells = <2>; 622 gpio-ranges = <&pmx0 0 14 8>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 626 clock-names = "apb_pclk"; 627 }; 628 629 gpio3: gpio@e8a0e000 { 630 compatible = "arm,pl061", "arm,primecell"; 631 reg = <0 0xe8a0e000 0 0x1000>; 632 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 633 gpio-controller; 634 #gpio-cells = <2>; 635 gpio-ranges = <&pmx0 0 22 8>; 636 interrupt-controller; 637 #interrupt-cells = <2>; 638 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 639 clock-names = "apb_pclk"; 640 }; 641 642 gpio4: gpio@e8a0f000 { 643 compatible = "arm,pl061", "arm,primecell"; 644 reg = <0 0xe8a0f000 0 0x1000>; 645 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 646 gpio-controller; 647 #gpio-cells = <2>; 648 gpio-ranges = <&pmx0 0 30 8>; 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 652 clock-names = "apb_pclk"; 653 }; 654 655 gpio5: gpio@e8a10000 { 656 compatible = "arm,pl061", "arm,primecell"; 657 reg = <0 0xe8a10000 0 0x1000>; 658 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 659 gpio-controller; 660 #gpio-cells = <2>; 661 gpio-ranges = <&pmx0 0 38 8>; 662 interrupt-controller; 663 #interrupt-cells = <2>; 664 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 665 clock-names = "apb_pclk"; 666 }; 667 668 gpio6: gpio@e8a11000 { 669 compatible = "arm,pl061", "arm,primecell"; 670 reg = <0 0xe8a11000 0 0x1000>; 671 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 672 gpio-controller; 673 #gpio-cells = <2>; 674 gpio-ranges = <&pmx0 0 46 8>; 675 interrupt-controller; 676 #interrupt-cells = <2>; 677 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 678 clock-names = "apb_pclk"; 679 }; 680 681 gpio7: gpio@e8a12000 { 682 compatible = "arm,pl061", "arm,primecell"; 683 reg = <0 0xe8a12000 0 0x1000>; 684 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 685 gpio-controller; 686 #gpio-cells = <2>; 687 gpio-ranges = <&pmx0 0 54 8>; 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 691 clock-names = "apb_pclk"; 692 }; 693 694 gpio8: gpio@e8a13000 { 695 compatible = "arm,pl061", "arm,primecell"; 696 reg = <0 0xe8a13000 0 0x1000>; 697 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 698 gpio-controller; 699 #gpio-cells = <2>; 700 gpio-ranges = <&pmx0 0 62 8>; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 704 clock-names = "apb_pclk"; 705 }; 706 707 gpio9: gpio@e8a14000 { 708 compatible = "arm,pl061", "arm,primecell"; 709 reg = <0 0xe8a14000 0 0x1000>; 710 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 711 gpio-controller; 712 #gpio-cells = <2>; 713 gpio-ranges = <&pmx0 0 70 8>; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 717 clock-names = "apb_pclk"; 718 }; 719 720 gpio10: gpio@e8a15000 { 721 compatible = "arm,pl061", "arm,primecell"; 722 reg = <0 0xe8a15000 0 0x1000>; 723 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 724 gpio-controller; 725 #gpio-cells = <2>; 726 gpio-ranges = <&pmx0 0 78 8>; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 730 clock-names = "apb_pclk"; 731 }; 732 733 gpio11: gpio@e8a16000 { 734 compatible = "arm,pl061", "arm,primecell"; 735 reg = <0 0xe8a16000 0 0x1000>; 736 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 737 gpio-controller; 738 #gpio-cells = <2>; 739 gpio-ranges = <&pmx0 0 86 8>; 740 interrupt-controller; 741 #interrupt-cells = <2>; 742 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 743 clock-names = "apb_pclk"; 744 }; 745 746 gpio12: gpio@e8a17000 { 747 compatible = "arm,pl061", "arm,primecell"; 748 reg = <0 0xe8a17000 0 0x1000>; 749 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 750 gpio-controller; 751 #gpio-cells = <2>; 752 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 753 interrupt-controller; 754 #interrupt-cells = <2>; 755 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 756 clock-names = "apb_pclk"; 757 }; 758 759 gpio13: gpio@e8a18000 { 760 compatible = "arm,pl061", "arm,primecell"; 761 reg = <0 0xe8a18000 0 0x1000>; 762 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 763 gpio-controller; 764 #gpio-cells = <2>; 765 gpio-ranges = <&pmx0 0 102 8>; 766 interrupt-controller; 767 #interrupt-cells = <2>; 768 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 769 clock-names = "apb_pclk"; 770 }; 771 772 gpio14: gpio@e8a19000 { 773 compatible = "arm,pl061", "arm,primecell"; 774 reg = <0 0xe8a19000 0 0x1000>; 775 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 776 gpio-controller; 777 #gpio-cells = <2>; 778 gpio-ranges = <&pmx0 0 110 8>; 779 interrupt-controller; 780 #interrupt-cells = <2>; 781 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 782 clock-names = "apb_pclk"; 783 }; 784 785 gpio15: gpio@e8a1a000 { 786 compatible = "arm,pl061", "arm,primecell"; 787 reg = <0 0xe8a1a000 0 0x1000>; 788 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 789 gpio-controller; 790 #gpio-cells = <2>; 791 gpio-ranges = <&pmx0 0 118 6>; 792 interrupt-controller; 793 #interrupt-cells = <2>; 794 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 795 clock-names = "apb_pclk"; 796 }; 797 798 gpio16: gpio@e8a1b000 { 799 compatible = "arm,pl061", "arm,primecell"; 800 reg = <0 0xe8a1b000 0 0x1000>; 801 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 802 gpio-controller; 803 #gpio-cells = <2>; 804 interrupt-controller; 805 #interrupt-cells = <2>; 806 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 807 clock-names = "apb_pclk"; 808 }; 809 810 gpio17: gpio@e8a1c000 { 811 compatible = "arm,pl061", "arm,primecell"; 812 reg = <0 0xe8a1c000 0 0x1000>; 813 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 814 gpio-controller; 815 #gpio-cells = <2>; 816 interrupt-controller; 817 #interrupt-cells = <2>; 818 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 819 clock-names = "apb_pclk"; 820 }; 821 822 gpio18: gpio@ff3b4000 { 823 compatible = "arm,pl061", "arm,primecell"; 824 reg = <0 0xff3b4000 0 0x1000>; 825 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 826 gpio-controller; 827 #gpio-cells = <2>; 828 gpio-ranges = <&pmx2 0 0 8>; 829 interrupt-controller; 830 #interrupt-cells = <2>; 831 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 832 clock-names = "apb_pclk"; 833 }; 834 835 gpio19: gpio@ff3b5000 { 836 compatible = "arm,pl061", "arm,primecell"; 837 reg = <0 0xff3b5000 0 0x1000>; 838 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 839 gpio-controller; 840 #gpio-cells = <2>; 841 gpio-ranges = <&pmx2 0 8 4>; 842 interrupt-controller; 843 #interrupt-cells = <2>; 844 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 845 clock-names = "apb_pclk"; 846 }; 847 848 gpio20: gpio@e8a1f000 { 849 compatible = "arm,pl061", "arm,primecell"; 850 reg = <0 0xe8a1f000 0 0x1000>; 851 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 852 gpio-controller; 853 #gpio-cells = <2>; 854 gpio-ranges = <&pmx1 0 0 6>; 855 interrupt-controller; 856 #interrupt-cells = <2>; 857 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 858 clock-names = "apb_pclk"; 859 }; 860 861 gpio21: gpio@e8a20000 { 862 compatible = "arm,pl061", "arm,primecell"; 863 reg = <0 0xe8a20000 0 0x1000>; 864 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 865 gpio-controller; 866 #gpio-cells = <2>; 867 interrupt-controller; 868 #interrupt-cells = <2>; 869 gpio-ranges = <&pmx3 0 0 6>; 870 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 871 clock-names = "apb_pclk"; 872 }; 873 874 gpio22: gpio@fff0b000 { 875 compatible = "arm,pl061", "arm,primecell"; 876 reg = <0 0xfff0b000 0 0x1000>; 877 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 878 gpio-controller; 879 #gpio-cells = <2>; 880 /* GPIO176 */ 881 gpio-ranges = <&pmx4 2 0 6>; 882 interrupt-controller; 883 #interrupt-cells = <2>; 884 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 885 clock-names = "apb_pclk"; 886 }; 887 888 gpio23: gpio@fff0c000 { 889 compatible = "arm,pl061", "arm,primecell"; 890 reg = <0 0xfff0c000 0 0x1000>; 891 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 892 gpio-controller; 893 #gpio-cells = <2>; 894 /* GPIO184 */ 895 gpio-ranges = <&pmx4 0 6 7>; 896 interrupt-controller; 897 #interrupt-cells = <2>; 898 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 899 clock-names = "apb_pclk"; 900 }; 901 902 gpio24: gpio@fff0d000 { 903 compatible = "arm,pl061", "arm,primecell"; 904 reg = <0 0xfff0d000 0 0x1000>; 905 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 906 gpio-controller; 907 #gpio-cells = <2>; 908 /* GPIO192 */ 909 gpio-ranges = <&pmx4 0 13 8>; 910 interrupt-controller; 911 #interrupt-cells = <2>; 912 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 913 clock-names = "apb_pclk"; 914 }; 915 916 gpio25: gpio@fff0e000 { 917 compatible = "arm,pl061", "arm,primecell"; 918 reg = <0 0xfff0e000 0 0x1000>; 919 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 920 gpio-controller; 921 #gpio-cells = <2>; 922 /* GPIO200 */ 923 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 924 interrupt-controller; 925 #interrupt-cells = <2>; 926 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 927 clock-names = "apb_pclk"; 928 }; 929 930 gpio26: gpio@fff0f000 { 931 compatible = "arm,pl061", "arm,primecell"; 932 reg = <0 0xfff0f000 0 0x1000>; 933 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 934 gpio-controller; 935 #gpio-cells = <2>; 936 /* GPIO208 */ 937 gpio-ranges = <&pmx4 0 28 8>; 938 interrupt-controller; 939 #interrupt-cells = <2>; 940 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 941 clock-names = "apb_pclk"; 942 }; 943 944 gpio27: gpio@fff10000 { 945 compatible = "arm,pl061", "arm,primecell"; 946 reg = <0 0xfff10000 0 0x1000>; 947 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 948 gpio-controller; 949 #gpio-cells = <2>; 950 /* GPIO216 */ 951 gpio-ranges = <&pmx4 0 36 6>; 952 interrupt-controller; 953 #interrupt-cells = <2>; 954 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 955 clock-names = "apb_pclk"; 956 }; 957 958 gpio28: gpio@fff1d000 { 959 compatible = "arm,pl061", "arm,primecell"; 960 reg = <0 0xfff1d000 0 0x1000>; 961 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 962 gpio-controller; 963 #gpio-cells = <2>; 964 interrupt-controller; 965 #interrupt-cells = <2>; 966 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 967 clock-names = "apb_pclk"; 968 }; 969 970 spi2: spi@ffd68000 { 971 compatible = "arm,pl022", "arm,primecell"; 972 reg = <0x0 0xffd68000 0x0 0x1000>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>; 977 clock-names = "sspclk", "apb_pclk"; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; 980 num-cs = <1>; 981 cs-gpios = <&gpio27 2 0>; 982 status = "disabled"; 983 }; 984 985 spi3: spi@ff3b3000 { 986 compatible = "arm,pl022", "arm,primecell"; 987 reg = <0x0 0xff3b3000 0x0 0x1000>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>; 992 clock-names = "sspclk", "apb_pclk"; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; 995 num-cs = <1>; 996 cs-gpios = <&gpio18 5 0>; 997 status = "disabled"; 998 }; 999 1000 pcie@f4000000 { 1001 compatible = "hisilicon,kirin960-pcie"; 1002 reg = <0x0 0xf4000000 0x0 0x1000>, 1003 <0x0 0xff3fe000 0x0 0x1000>, 1004 <0x0 0xf3f20000 0x0 0x40000>, 1005 <0x0 0xf5000000 0x0 0x2000>; 1006 reg-names = "dbi", "apb", "phy", "config"; 1007 bus-range = <0x0 0xff>; 1008 #address-cells = <3>; 1009 #size-cells = <2>; 1010 device_type = "pci"; 1011 ranges = <0x02000000 0x0 0x00000000 1012 0x0 0xf6000000 1013 0x0 0x02000000>; 1014 num-lanes = <1>; 1015 #interrupt-cells = <1>; 1016 interrupts = <0 283 4>; 1017 interrupt-names = "msi"; 1018 interrupt-map-mask = <0xf800 0 0 7>; 1019 interrupt-map = <0x0 0 0 1 1020 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1021 <0x0 0 0 2 1022 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1023 <0x0 0 0 3 1024 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1025 <0x0 0 0 4 1026 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 1028 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 1029 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 1030 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 1031 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 1032 clock-names = "pcie_phy_ref", "pcie_aux", 1033 "pcie_apb_phy", "pcie_apb_sys", 1034 "pcie_aclk"; 1035 reset-gpios = <&gpio11 1 0 >; 1036 }; 1037 1038 /* UFS */ 1039 ufs: ufs@ff3b0000 { 1040 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; 1041 /* 0: HCI standard */ 1042 /* 1: UFS SYS CTRL */ 1043 reg = <0x0 0xff3b0000 0x0 0x1000>, 1044 <0x0 0xff3b1000 0x0 0x1000>; 1045 interrupt-parent = <&gic>; 1046 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, 1048 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; 1049 clock-names = "ref_clk", "phy_clk"; 1050 freq-table-hz = <0 0>, 1051 <0 0>; 1052 /* offset: 0x84; bit: 12 */ 1053 resets = <&crg_rst 0x84 12>; 1054 reset-names = "rst"; 1055 }; 1056 1057 /* SD */ 1058 dwmmc1: dwmmc1@ff37f000 { 1059 compatible = "hisilicon,hi3660-dw-mshc"; 1060 reg = <0x0 0xff37f000 0x0 0x1000>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 1065 <&crg_ctrl HI3660_HCLK_GATE_SD>; 1066 clock-names = "ciu", "biu"; 1067 clock-frequency = <3200000>; 1068 resets = <&crg_rst 0x94 18>; 1069 reset-names = "reset"; 1070 hisilicon,peripheral-syscon = <&sctrl>; 1071 card-detect-delay = <200>; 1072 status = "disabled"; 1073 }; 1074 1075 /* SDIO */ 1076 dwmmc2: dwmmc2@ff3ff000 { 1077 compatible = "hisilicon,hi3660-dw-mshc"; 1078 reg = <0x0 0xff3ff000 0x0 0x1000>; 1079 #address-cells = <0x1>; 1080 #size-cells = <0x0>; 1081 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 1083 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 1084 clock-names = "ciu", "biu"; 1085 resets = <&crg_rst 0x94 20>; 1086 reset-names = "reset"; 1087 card-detect-delay = <200>; 1088 status = "disabled"; 1089 }; 1090 1091 watchdog0: watchdog@e8a06000 { 1092 compatible = "arm,sp805", "arm,primecell"; 1093 reg = <0x0 0xe8a06000 0x0 0x1000>; 1094 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&crg_ctrl HI3660_OSC32K>, 1096 <&crg_ctrl HI3660_OSC32K>; 1097 clock-names = "wdog_clk", "apb_pclk"; 1098 }; 1099 1100 watchdog1: watchdog@e8a07000 { 1101 compatible = "arm,sp805", "arm,primecell"; 1102 reg = <0x0 0xe8a07000 0x0 0x1000>; 1103 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&crg_ctrl HI3660_OSC32K>, 1105 <&crg_ctrl HI3660_OSC32K>; 1106 clock-names = "wdog_clk", "apb_pclk"; 1107 }; 1108 1109 tsensor: tsensor@fff30000 { 1110 compatible = "hisilicon,hi3660-tsensor"; 1111 reg = <0x0 0xfff30000 0x0 0x1000>; 1112 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1113 #thermal-sensor-cells = <1>; 1114 }; 1115 1116 thermal-zones { 1117 1118 cls0: cls0-thermal { 1119 polling-delay = <1000>; 1120 polling-delay-passive = <100>; 1121 sustainable-power = <4500>; 1122 1123 /* sensor ID */ 1124 thermal-sensors = <&tsensor 1>; 1125 1126 trips { 1127 threshold: trip-point0 { 1128 temperature = <65000>; 1129 hysteresis = <1000>; 1130 type = "passive"; 1131 }; 1132 1133 target: trip-point1 { 1134 temperature = <75000>; 1135 hysteresis = <1000>; 1136 type = "passive"; 1137 }; 1138 }; 1139 1140 cooling-maps { 1141 map0 { 1142 trip = <&target>; 1143 contribution = <1024>; 1144 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1145 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1146 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1147 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1148 }; 1149 map1 { 1150 trip = <&target>; 1151 contribution = <512>; 1152 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1153 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1154 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1155 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1156 }; 1157 }; 1158 }; 1159 }; 1160 1161 usb3_otg_bc: usb3_otg_bc@ff200000 { 1162 compatible = "syscon", "simple-mfd"; 1163 reg = <0x0 0xff200000 0x0 0x1000>; 1164 1165 usb_phy: usb-phy { 1166 compatible = "hisilicon,hi3660-usb-phy"; 1167 #phy-cells = <0>; 1168 hisilicon,pericrg-syscon = <&crg_ctrl>; 1169 hisilicon,pctrl-syscon = <&pctrl>; 1170 hisilicon,eye-diagram-param = <0x22466e4>; 1171 }; 1172 }; 1173 1174 dwc3: usb@ff100000 { 1175 compatible = "snps,dwc3"; 1176 reg = <0x0 0xff100000 0x0 0x100000>; 1177 1178 clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, 1179 <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; 1180 clock-names = "ref", "bus_early"; 1181 1182 assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; 1183 assigned-clock-rates = <229000000>; 1184 1185 resets = <&crg_rst 0x90 8>, 1186 <&crg_rst 0x90 7>, 1187 <&crg_rst 0x90 6>, 1188 <&crg_rst 0x90 5>; 1189 1190 interrupts = <0 159 4>, <0 161 4>; 1191 phys = <&usb_phy>; 1192 phy-names = "usb3-phy"; 1193 }; 1194 }; 1195}; 1196 1197#include "hi3660-coresight.dtsi" 1198