1/* 2 * dts file for Hisilicon Hi3660 SoC 3 * 4 * Copyright (C) 2016, Hisilicon Ltd. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/hi3660-clock.h> 9 10/ { 11 compatible = "hisilicon,hi3660"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 psci { 17 compatible = "arm,psci-0.2"; 18 method = "smc"; 19 }; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53", "arm,armv8"; 58 device_type = "cpu"; 59 reg = <0x0 0x0>; 60 enable-method = "psci"; 61 }; 62 63 cpu1: cpu@1 { 64 compatible = "arm,cortex-a53", "arm,armv8"; 65 device_type = "cpu"; 66 reg = <0x0 0x1>; 67 enable-method = "psci"; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 device_type = "cpu"; 73 reg = <0x0 0x2>; 74 enable-method = "psci"; 75 }; 76 77 cpu3: cpu@3 { 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 device_type = "cpu"; 80 reg = <0x0 0x3>; 81 enable-method = "psci"; 82 }; 83 84 cpu4: cpu@100 { 85 compatible = "arm,cortex-a73", "arm,armv8"; 86 device_type = "cpu"; 87 reg = <0x0 0x100>; 88 enable-method = "psci"; 89 }; 90 91 cpu5: cpu@101 { 92 compatible = "arm,cortex-a73", "arm,armv8"; 93 device_type = "cpu"; 94 reg = <0x0 0x101>; 95 enable-method = "psci"; 96 }; 97 98 cpu6: cpu@102 { 99 compatible = "arm,cortex-a73", "arm,armv8"; 100 device_type = "cpu"; 101 reg = <0x0 0x102>; 102 enable-method = "psci"; 103 }; 104 105 cpu7: cpu@103 { 106 compatible = "arm,cortex-a73", "arm,armv8"; 107 device_type = "cpu"; 108 reg = <0x0 0x103>; 109 enable-method = "psci"; 110 }; 111 }; 112 113 gic: interrupt-controller@e82b0000 { 114 compatible = "arm,gic-400"; 115 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 116 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 117 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 118 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 119 #address-cells = <0>; 120 #interrupt-cells = <3>; 121 interrupt-controller; 122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 123 IRQ_TYPE_LEVEL_HIGH)>; 124 }; 125 126 timer { 127 compatible = "arm,armv8-timer"; 128 interrupt-parent = <&gic>; 129 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 130 IRQ_TYPE_LEVEL_LOW)>, 131 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 132 IRQ_TYPE_LEVEL_LOW)>, 133 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 134 IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 136 IRQ_TYPE_LEVEL_LOW)>; 137 }; 138 139 soc { 140 compatible = "simple-bus"; 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 145 crg_ctrl: crg_ctrl@fff35000 { 146 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 147 reg = <0x0 0xfff35000 0x0 0x1000>; 148 #clock-cells = <1>; 149 }; 150 151 crg_rst: crg_rst_controller { 152 compatible = "hisilicon,hi3660-reset"; 153 #reset-cells = <2>; 154 hisi,rst-syscon = <&crg_ctrl>; 155 }; 156 157 158 pctrl: pctrl@e8a09000 { 159 compatible = "hisilicon,hi3660-pctrl", "syscon"; 160 reg = <0x0 0xe8a09000 0x0 0x2000>; 161 #clock-cells = <1>; 162 }; 163 164 pmuctrl: crg_ctrl@fff34000 { 165 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 166 reg = <0x0 0xfff34000 0x0 0x1000>; 167 #clock-cells = <1>; 168 }; 169 170 sctrl: sctrl@fff0a000 { 171 compatible = "hisilicon,hi3660-sctrl", "syscon"; 172 reg = <0x0 0xfff0a000 0x0 0x1000>; 173 #clock-cells = <1>; 174 }; 175 176 iomcu: iomcu@ffd7e000 { 177 compatible = "hisilicon,hi3660-iomcu", "syscon"; 178 reg = <0x0 0xffd7e000 0x0 0x1000>; 179 #clock-cells = <1>; 180 181 }; 182 183 iomcu_rst: reset { 184 compatible = "hisilicon,hi3660-reset"; 185 hisi,rst-syscon = <&iomcu>; 186 #reset-cells = <2>; 187 }; 188 189 i2c0: i2c@ffd71000 { 190 compatible = "snps,designware-i2c"; 191 reg = <0x0 0xffd71000 0x0 0x1000>; 192 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 clock-frequency = <400000>; 196 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 197 resets = <&iomcu_rst 0x20 3>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 200 status = "disabled"; 201 }; 202 203 i2c1: i2c@ffd72000 { 204 compatible = "snps,designware-i2c"; 205 reg = <0x0 0xffd72000 0x0 0x1000>; 206 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 clock-frequency = <400000>; 210 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 211 resets = <&iomcu_rst 0x20 4>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 214 status = "disabled"; 215 }; 216 217 i2c3: i2c@fdf0c000 { 218 compatible = "snps,designware-i2c"; 219 reg = <0x0 0xfdf0c000 0x0 0x1000>; 220 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 clock-frequency = <400000>; 224 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 225 resets = <&crg_rst 0x78 7>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 228 status = "disabled"; 229 }; 230 231 i2c7: i2c@fdf0b000 { 232 compatible = "snps,designware-i2c"; 233 reg = <0x0 0xfdf0b000 0x0 0x1000>; 234 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 clock-frequency = <400000>; 238 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 239 resets = <&crg_rst 0x60 14>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 242 status = "disabled"; 243 }; 244 245 uart0: serial@fdf02000 { 246 compatible = "arm,pl011", "arm,primecell"; 247 reg = <0x0 0xfdf02000 0x0 0x1000>; 248 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 250 <&crg_ctrl HI3660_PCLK>; 251 clock-names = "uartclk", "apb_pclk"; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 254 status = "disabled"; 255 }; 256 257 uart1: serial@fdf00000 { 258 compatible = "arm,pl011", "arm,primecell"; 259 reg = <0x0 0xfdf00000 0x0 0x1000>; 260 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 262 <&crg_ctrl HI3660_CLK_GATE_UART1>; 263 clock-names = "uartclk", "apb_pclk"; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 266 status = "disabled"; 267 }; 268 269 uart2: serial@fdf03000 { 270 compatible = "arm,pl011", "arm,primecell"; 271 reg = <0x0 0xfdf03000 0x0 0x1000>; 272 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 274 <&crg_ctrl HI3660_PCLK>; 275 clock-names = "uartclk", "apb_pclk"; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 278 status = "disabled"; 279 }; 280 281 uart3: serial@ffd74000 { 282 compatible = "arm,pl011", "arm,primecell"; 283 reg = <0x0 0xffd74000 0x0 0x1000>; 284 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 286 <&crg_ctrl HI3660_PCLK>; 287 clock-names = "uartclk", "apb_pclk"; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 290 status = "disabled"; 291 }; 292 293 uart4: serial@fdf01000 { 294 compatible = "arm,pl011", "arm,primecell"; 295 reg = <0x0 0xfdf01000 0x0 0x1000>; 296 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 298 <&crg_ctrl HI3660_CLK_GATE_UART4>; 299 clock-names = "uartclk", "apb_pclk"; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 302 status = "disabled"; 303 }; 304 305 uart5: serial@fdf05000 { 306 compatible = "arm,pl011", "arm,primecell"; 307 reg = <0x0 0xfdf05000 0x0 0x1000>; 308 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 310 <&crg_ctrl HI3660_CLK_GATE_UART5>; 311 clock-names = "uartclk", "apb_pclk"; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 314 status = "disabled"; 315 }; 316 317 uart6: serial@fff32000 { 318 compatible = "arm,pl011", "arm,primecell"; 319 reg = <0x0 0xfff32000 0x0 0x1000>; 320 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&crg_ctrl HI3660_CLK_UART6>, 322 <&crg_ctrl HI3660_PCLK>; 323 clock-names = "uartclk", "apb_pclk"; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 326 status = "disabled"; 327 }; 328 329 rtc0: rtc@fff04000 { 330 compatible = "arm,pl031", "arm,primecell"; 331 reg = <0x0 0Xfff04000 0x0 0x1000>; 332 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&crg_ctrl HI3660_PCLK>; 334 clock-names = "apb_pclk"; 335 }; 336 337 gpio0: gpio@e8a0b000 { 338 compatible = "arm,pl061", "arm,primecell"; 339 reg = <0 0xe8a0b000 0 0x1000>; 340 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 341 gpio-controller; 342 #gpio-cells = <2>; 343 gpio-ranges = <&pmx0 1 0 7>; 344 interrupt-controller; 345 #interrupt-cells = <2>; 346 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 347 clock-names = "apb_pclk"; 348 }; 349 350 gpio1: gpio@e8a0c000 { 351 compatible = "arm,pl061", "arm,primecell"; 352 reg = <0 0xe8a0c000 0 0x1000>; 353 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 354 gpio-controller; 355 #gpio-cells = <2>; 356 gpio-ranges = <&pmx0 1 7 7>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 360 clock-names = "apb_pclk"; 361 }; 362 363 gpio2: gpio@e8a0d000 { 364 compatible = "arm,pl061", "arm,primecell"; 365 reg = <0 0xe8a0d000 0 0x1000>; 366 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 367 gpio-controller; 368 #gpio-cells = <2>; 369 gpio-ranges = <&pmx0 0 14 8>; 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 373 clock-names = "apb_pclk"; 374 }; 375 376 gpio3: gpio@e8a0e000 { 377 compatible = "arm,pl061", "arm,primecell"; 378 reg = <0 0xe8a0e000 0 0x1000>; 379 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 380 gpio-controller; 381 #gpio-cells = <2>; 382 gpio-ranges = <&pmx0 0 22 8>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 386 clock-names = "apb_pclk"; 387 }; 388 389 gpio4: gpio@e8a0f000 { 390 compatible = "arm,pl061", "arm,primecell"; 391 reg = <0 0xe8a0f000 0 0x1000>; 392 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 393 gpio-controller; 394 #gpio-cells = <2>; 395 gpio-ranges = <&pmx0 0 30 8>; 396 interrupt-controller; 397 #interrupt-cells = <2>; 398 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 399 clock-names = "apb_pclk"; 400 }; 401 402 gpio5: gpio@e8a10000 { 403 compatible = "arm,pl061", "arm,primecell"; 404 reg = <0 0xe8a10000 0 0x1000>; 405 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 406 gpio-controller; 407 #gpio-cells = <2>; 408 gpio-ranges = <&pmx0 0 38 8>; 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 412 clock-names = "apb_pclk"; 413 }; 414 415 gpio6: gpio@e8a11000 { 416 compatible = "arm,pl061", "arm,primecell"; 417 reg = <0 0xe8a11000 0 0x1000>; 418 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 419 gpio-controller; 420 #gpio-cells = <2>; 421 gpio-ranges = <&pmx0 0 46 8>; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 425 clock-names = "apb_pclk"; 426 }; 427 428 gpio7: gpio@e8a12000 { 429 compatible = "arm,pl061", "arm,primecell"; 430 reg = <0 0xe8a12000 0 0x1000>; 431 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 432 gpio-controller; 433 #gpio-cells = <2>; 434 gpio-ranges = <&pmx0 0 54 8>; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 438 clock-names = "apb_pclk"; 439 }; 440 441 gpio8: gpio@e8a13000 { 442 compatible = "arm,pl061", "arm,primecell"; 443 reg = <0 0xe8a13000 0 0x1000>; 444 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 445 gpio-controller; 446 #gpio-cells = <2>; 447 gpio-ranges = <&pmx0 0 62 8>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 451 clock-names = "apb_pclk"; 452 }; 453 454 gpio9: gpio@e8a14000 { 455 compatible = "arm,pl061", "arm,primecell"; 456 reg = <0 0xe8a14000 0 0x1000>; 457 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 458 gpio-controller; 459 #gpio-cells = <2>; 460 gpio-ranges = <&pmx0 0 70 8>; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 464 clock-names = "apb_pclk"; 465 }; 466 467 gpio10: gpio@e8a15000 { 468 compatible = "arm,pl061", "arm,primecell"; 469 reg = <0 0xe8a15000 0 0x1000>; 470 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 471 gpio-controller; 472 #gpio-cells = <2>; 473 gpio-ranges = <&pmx0 0 78 8>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 477 clock-names = "apb_pclk"; 478 }; 479 480 gpio11: gpio@e8a16000 { 481 compatible = "arm,pl061", "arm,primecell"; 482 reg = <0 0xe8a16000 0 0x1000>; 483 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 484 gpio-controller; 485 #gpio-cells = <2>; 486 gpio-ranges = <&pmx0 0 86 8>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 490 clock-names = "apb_pclk"; 491 }; 492 493 gpio12: gpio@e8a17000 { 494 compatible = "arm,pl061", "arm,primecell"; 495 reg = <0 0xe8a17000 0 0x1000>; 496 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 500 interrupt-controller; 501 #interrupt-cells = <2>; 502 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 503 clock-names = "apb_pclk"; 504 }; 505 506 gpio13: gpio@e8a18000 { 507 compatible = "arm,pl061", "arm,primecell"; 508 reg = <0 0xe8a18000 0 0x1000>; 509 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 510 gpio-controller; 511 #gpio-cells = <2>; 512 gpio-ranges = <&pmx0 0 102 8>; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 516 clock-names = "apb_pclk"; 517 }; 518 519 gpio14: gpio@e8a19000 { 520 compatible = "arm,pl061", "arm,primecell"; 521 reg = <0 0xe8a19000 0 0x1000>; 522 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 523 gpio-controller; 524 #gpio-cells = <2>; 525 gpio-ranges = <&pmx0 0 110 8>; 526 interrupt-controller; 527 #interrupt-cells = <2>; 528 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 529 clock-names = "apb_pclk"; 530 }; 531 532 gpio15: gpio@e8a1a000 { 533 compatible = "arm,pl061", "arm,primecell"; 534 reg = <0 0xe8a1a000 0 0x1000>; 535 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 536 gpio-controller; 537 #gpio-cells = <2>; 538 gpio-ranges = <&pmx0 0 118 6>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 542 clock-names = "apb_pclk"; 543 }; 544 545 gpio16: gpio@e8a1b000 { 546 compatible = "arm,pl061", "arm,primecell"; 547 reg = <0 0xe8a1b000 0 0x1000>; 548 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 549 gpio-controller; 550 #gpio-cells = <2>; 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 554 clock-names = "apb_pclk"; 555 }; 556 557 gpio17: gpio@e8a1c000 { 558 compatible = "arm,pl061", "arm,primecell"; 559 reg = <0 0xe8a1c000 0 0x1000>; 560 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 561 gpio-controller; 562 #gpio-cells = <2>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 566 clock-names = "apb_pclk"; 567 }; 568 569 gpio18: gpio@ff3b4000 { 570 compatible = "arm,pl061", "arm,primecell"; 571 reg = <0 0xff3b4000 0 0x1000>; 572 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 573 gpio-controller; 574 #gpio-cells = <2>; 575 gpio-ranges = <&pmx2 0 0 8>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 579 clock-names = "apb_pclk"; 580 }; 581 582 gpio19: gpio@ff3b5000 { 583 compatible = "arm,pl061", "arm,primecell"; 584 reg = <0 0xff3b5000 0 0x1000>; 585 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 586 gpio-controller; 587 #gpio-cells = <2>; 588 gpio-ranges = <&pmx2 0 8 4>; 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 592 clock-names = "apb_pclk"; 593 }; 594 595 gpio20: gpio@e8a1f000 { 596 compatible = "arm,pl061", "arm,primecell"; 597 reg = <0 0xe8a1f000 0 0x1000>; 598 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 599 gpio-controller; 600 #gpio-cells = <2>; 601 gpio-ranges = <&pmx1 0 0 6>; 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 605 clock-names = "apb_pclk"; 606 }; 607 608 gpio21: gpio@e8a20000 { 609 compatible = "arm,pl061", "arm,primecell"; 610 reg = <0 0xe8a20000 0 0x1000>; 611 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 612 gpio-controller; 613 #gpio-cells = <2>; 614 interrupt-controller; 615 #interrupt-cells = <2>; 616 gpio-ranges = <&pmx3 0 0 6>; 617 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 618 clock-names = "apb_pclk"; 619 }; 620 621 gpio22: gpio@fff0b000 { 622 compatible = "arm,pl061", "arm,primecell"; 623 reg = <0 0xfff0b000 0 0x1000>; 624 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 625 gpio-controller; 626 #gpio-cells = <2>; 627 /* GPIO176 */ 628 gpio-ranges = <&pmx4 2 0 6>; 629 interrupt-controller; 630 #interrupt-cells = <2>; 631 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 632 clock-names = "apb_pclk"; 633 }; 634 635 gpio23: gpio@fff0c000 { 636 compatible = "arm,pl061", "arm,primecell"; 637 reg = <0 0xfff0c000 0 0x1000>; 638 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 639 gpio-controller; 640 #gpio-cells = <2>; 641 /* GPIO184 */ 642 gpio-ranges = <&pmx4 0 6 7>; 643 interrupt-controller; 644 #interrupt-cells = <2>; 645 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 646 clock-names = "apb_pclk"; 647 }; 648 649 gpio24: gpio@fff0d000 { 650 compatible = "arm,pl061", "arm,primecell"; 651 reg = <0 0xfff0d000 0 0x1000>; 652 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 653 gpio-controller; 654 #gpio-cells = <2>; 655 /* GPIO192 */ 656 gpio-ranges = <&pmx4 0 13 8>; 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 660 clock-names = "apb_pclk"; 661 }; 662 663 gpio25: gpio@fff0e000 { 664 compatible = "arm,pl061", "arm,primecell"; 665 reg = <0 0xfff0e000 0 0x1000>; 666 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 667 gpio-controller; 668 #gpio-cells = <2>; 669 /* GPIO200 */ 670 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 671 interrupt-controller; 672 #interrupt-cells = <2>; 673 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 674 clock-names = "apb_pclk"; 675 }; 676 677 gpio26: gpio@fff0f000 { 678 compatible = "arm,pl061", "arm,primecell"; 679 reg = <0 0xfff0f000 0 0x1000>; 680 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 681 gpio-controller; 682 #gpio-cells = <2>; 683 /* GPIO208 */ 684 gpio-ranges = <&pmx4 0 28 8>; 685 interrupt-controller; 686 #interrupt-cells = <2>; 687 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 688 clock-names = "apb_pclk"; 689 }; 690 691 gpio27: gpio@fff10000 { 692 compatible = "arm,pl061", "arm,primecell"; 693 reg = <0 0xfff10000 0 0x1000>; 694 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 695 gpio-controller; 696 #gpio-cells = <2>; 697 /* GPIO216 */ 698 gpio-ranges = <&pmx4 0 36 6>; 699 interrupt-controller; 700 #interrupt-cells = <2>; 701 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 702 clock-names = "apb_pclk"; 703 }; 704 705 gpio28: gpio@fff1d000 { 706 compatible = "arm,pl061", "arm,primecell"; 707 reg = <0 0xfff1d000 0 0x1000>; 708 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 709 gpio-controller; 710 #gpio-cells = <2>; 711 interrupt-controller; 712 #interrupt-cells = <2>; 713 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 714 clock-names = "apb_pclk"; 715 }; 716 717 spi2: spi@ffd68000 { 718 compatible = "arm,pl022", "arm,primecell"; 719 reg = <0x0 0xffd68000 0x0 0x1000>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 724 clock-names = "apb_pclk"; 725 pinctrl-names = "default"; 726 pinctrl-0 = <&spi2_pmx_func>; 727 num-cs = <1>; 728 cs-gpios = <&gpio27 2 0>; 729 status = "disabled"; 730 }; 731 732 spi3: spi@ff3b3000 { 733 compatible = "arm,pl022", "arm,primecell"; 734 reg = <0x0 0xff3b3000 0x0 0x1000>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 739 clock-names = "apb_pclk"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&spi3_pmx_func>; 742 num-cs = <1>; 743 cs-gpios = <&gpio18 5 0>; 744 status = "disabled"; 745 }; 746 }; 747}; 748