1/* 2 * dts file for Hisilicon Hi3660 SoC 3 * 4 * Copyright (C) 2016, Hisilicon Ltd. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/hi3660-clock.h> 9 10/ { 11 compatible = "hisilicon,hi3660"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 psci { 17 compatible = "arm,psci-0.2"; 18 method = "smc"; 19 }; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53", "arm,armv8"; 58 device_type = "cpu"; 59 reg = <0x0 0x0>; 60 enable-method = "psci"; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a53", "arm,armv8"; 66 device_type = "cpu"; 67 reg = <0x0 0x1>; 68 enable-method = "psci"; 69 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 device_type = "cpu"; 75 reg = <0x0 0x2>; 76 enable-method = "psci"; 77 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53", "arm,armv8"; 82 device_type = "cpu"; 83 reg = <0x0 0x3>; 84 enable-method = "psci"; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; 86 }; 87 88 cpu4: cpu@100 { 89 compatible = "arm,cortex-a73", "arm,armv8"; 90 device_type = "cpu"; 91 reg = <0x0 0x100>; 92 enable-method = "psci"; 93 cpu-idle-states = < 94 &CPU_NAP 95 &CPU_SLEEP 96 &CLUSTER_SLEEP_1 97 >; 98 }; 99 100 cpu5: cpu@101 { 101 compatible = "arm,cortex-a73", "arm,armv8"; 102 device_type = "cpu"; 103 reg = <0x0 0x101>; 104 enable-method = "psci"; 105 cpu-idle-states = < 106 &CPU_NAP 107 &CPU_SLEEP 108 &CLUSTER_SLEEP_1 109 >; 110 }; 111 112 cpu6: cpu@102 { 113 compatible = "arm,cortex-a73", "arm,armv8"; 114 device_type = "cpu"; 115 reg = <0x0 0x102>; 116 enable-method = "psci"; 117 cpu-idle-states = < 118 &CPU_NAP 119 &CPU_SLEEP 120 &CLUSTER_SLEEP_1 121 >; 122 }; 123 124 cpu7: cpu@103 { 125 compatible = "arm,cortex-a73", "arm,armv8"; 126 device_type = "cpu"; 127 reg = <0x0 0x103>; 128 enable-method = "psci"; 129 cpu-idle-states = < 130 &CPU_NAP 131 &CPU_SLEEP 132 &CLUSTER_SLEEP_1 133 >; 134 }; 135 136 idle-states { 137 entry-method = "psci"; 138 139 CPU_NAP: cpu-nap { 140 compatible = "arm,idle-state"; 141 arm,psci-suspend-param = <0x0000001>; 142 entry-latency-us = <7>; 143 exit-latency-us = <2>; 144 min-residency-us = <15>; 145 }; 146 147 CPU_SLEEP: cpu-sleep { 148 compatible = "arm,idle-state"; 149 local-timer-stop; 150 arm,psci-suspend-param = <0x0010000>; 151 entry-latency-us = <40>; 152 exit-latency-us = <70>; 153 min-residency-us = <3000>; 154 }; 155 156 CLUSTER_SLEEP_0: cluster-sleep-0 { 157 compatible = "arm,idle-state"; 158 local-timer-stop; 159 arm,psci-suspend-param = <0x1010000>; 160 entry-latency-us = <500>; 161 exit-latency-us = <5000>; 162 min-residency-us = <20000>; 163 }; 164 165 CLUSTER_SLEEP_1: cluster-sleep-1 { 166 compatible = "arm,idle-state"; 167 local-timer-stop; 168 arm,psci-suspend-param = <0x1010000>; 169 entry-latency-us = <1000>; 170 exit-latency-us = <5000>; 171 min-residency-us = <20000>; 172 }; 173 }; 174 }; 175 176 gic: interrupt-controller@e82b0000 { 177 compatible = "arm,gic-400"; 178 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 179 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 180 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 181 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 182 #address-cells = <0>; 183 #interrupt-cells = <3>; 184 interrupt-controller; 185 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 186 IRQ_TYPE_LEVEL_HIGH)>; 187 }; 188 189 timer { 190 compatible = "arm,armv8-timer"; 191 interrupt-parent = <&gic>; 192 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 193 IRQ_TYPE_LEVEL_LOW)>, 194 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 195 IRQ_TYPE_LEVEL_LOW)>, 196 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 197 IRQ_TYPE_LEVEL_LOW)>, 198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 199 IRQ_TYPE_LEVEL_LOW)>; 200 }; 201 202 soc { 203 compatible = "simple-bus"; 204 #address-cells = <2>; 205 #size-cells = <2>; 206 ranges; 207 208 crg_ctrl: crg_ctrl@fff35000 { 209 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 210 reg = <0x0 0xfff35000 0x0 0x1000>; 211 #clock-cells = <1>; 212 }; 213 214 crg_rst: crg_rst_controller { 215 compatible = "hisilicon,hi3660-reset"; 216 #reset-cells = <2>; 217 hisi,rst-syscon = <&crg_ctrl>; 218 }; 219 220 221 pctrl: pctrl@e8a09000 { 222 compatible = "hisilicon,hi3660-pctrl", "syscon"; 223 reg = <0x0 0xe8a09000 0x0 0x2000>; 224 #clock-cells = <1>; 225 }; 226 227 pmuctrl: crg_ctrl@fff34000 { 228 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 229 reg = <0x0 0xfff34000 0x0 0x1000>; 230 #clock-cells = <1>; 231 }; 232 233 sctrl: sctrl@fff0a000 { 234 compatible = "hisilicon,hi3660-sctrl", "syscon"; 235 reg = <0x0 0xfff0a000 0x0 0x1000>; 236 #clock-cells = <1>; 237 }; 238 239 iomcu: iomcu@ffd7e000 { 240 compatible = "hisilicon,hi3660-iomcu", "syscon"; 241 reg = <0x0 0xffd7e000 0x0 0x1000>; 242 #clock-cells = <1>; 243 244 }; 245 246 iomcu_rst: reset { 247 compatible = "hisilicon,hi3660-reset"; 248 hisi,rst-syscon = <&iomcu>; 249 #reset-cells = <2>; 250 }; 251 252 dual_timer0: timer@fff14000 { 253 compatible = "arm,sp804", "arm,primecell"; 254 reg = <0x0 0xfff14000 0x0 0x1000>; 255 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&crg_ctrl HI3660_OSC32K>, 258 <&crg_ctrl HI3660_OSC32K>, 259 <&crg_ctrl HI3660_OSC32K>; 260 clock-names = "timer1", "timer2", "apb_pclk"; 261 }; 262 263 i2c0: i2c@ffd71000 { 264 compatible = "snps,designware-i2c"; 265 reg = <0x0 0xffd71000 0x0 0x1000>; 266 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 clock-frequency = <400000>; 270 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 271 resets = <&iomcu_rst 0x20 3>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 274 status = "disabled"; 275 }; 276 277 i2c1: i2c@ffd72000 { 278 compatible = "snps,designware-i2c"; 279 reg = <0x0 0xffd72000 0x0 0x1000>; 280 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 clock-frequency = <400000>; 284 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 285 resets = <&iomcu_rst 0x20 4>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 288 status = "disabled"; 289 }; 290 291 i2c3: i2c@fdf0c000 { 292 compatible = "snps,designware-i2c"; 293 reg = <0x0 0xfdf0c000 0x0 0x1000>; 294 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 clock-frequency = <400000>; 298 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 299 resets = <&crg_rst 0x78 7>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 302 status = "disabled"; 303 }; 304 305 i2c7: i2c@fdf0b000 { 306 compatible = "snps,designware-i2c"; 307 reg = <0x0 0xfdf0b000 0x0 0x1000>; 308 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 clock-frequency = <400000>; 312 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 313 resets = <&crg_rst 0x60 14>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 316 status = "disabled"; 317 }; 318 319 uart0: serial@fdf02000 { 320 compatible = "arm,pl011", "arm,primecell"; 321 reg = <0x0 0xfdf02000 0x0 0x1000>; 322 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 324 <&crg_ctrl HI3660_PCLK>; 325 clock-names = "uartclk", "apb_pclk"; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 328 status = "disabled"; 329 }; 330 331 uart1: serial@fdf00000 { 332 compatible = "arm,pl011", "arm,primecell"; 333 reg = <0x0 0xfdf00000 0x0 0x1000>; 334 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 336 <&crg_ctrl HI3660_CLK_GATE_UART1>; 337 clock-names = "uartclk", "apb_pclk"; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 340 status = "disabled"; 341 }; 342 343 uart2: serial@fdf03000 { 344 compatible = "arm,pl011", "arm,primecell"; 345 reg = <0x0 0xfdf03000 0x0 0x1000>; 346 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 348 <&crg_ctrl HI3660_PCLK>; 349 clock-names = "uartclk", "apb_pclk"; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 352 status = "disabled"; 353 }; 354 355 uart3: serial@ffd74000 { 356 compatible = "arm,pl011", "arm,primecell"; 357 reg = <0x0 0xffd74000 0x0 0x1000>; 358 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 360 <&crg_ctrl HI3660_PCLK>; 361 clock-names = "uartclk", "apb_pclk"; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 364 status = "disabled"; 365 }; 366 367 uart4: serial@fdf01000 { 368 compatible = "arm,pl011", "arm,primecell"; 369 reg = <0x0 0xfdf01000 0x0 0x1000>; 370 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 372 <&crg_ctrl HI3660_CLK_GATE_UART4>; 373 clock-names = "uartclk", "apb_pclk"; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 376 status = "disabled"; 377 }; 378 379 uart5: serial@fdf05000 { 380 compatible = "arm,pl011", "arm,primecell"; 381 reg = <0x0 0xfdf05000 0x0 0x1000>; 382 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 384 <&crg_ctrl HI3660_CLK_GATE_UART5>; 385 clock-names = "uartclk", "apb_pclk"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 388 status = "disabled"; 389 }; 390 391 uart6: serial@fff32000 { 392 compatible = "arm,pl011", "arm,primecell"; 393 reg = <0x0 0xfff32000 0x0 0x1000>; 394 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&crg_ctrl HI3660_CLK_UART6>, 396 <&crg_ctrl HI3660_PCLK>; 397 clock-names = "uartclk", "apb_pclk"; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 400 status = "disabled"; 401 }; 402 403 rtc0: rtc@fff04000 { 404 compatible = "arm,pl031", "arm,primecell"; 405 reg = <0x0 0Xfff04000 0x0 0x1000>; 406 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&crg_ctrl HI3660_PCLK>; 408 clock-names = "apb_pclk"; 409 }; 410 411 gpio0: gpio@e8a0b000 { 412 compatible = "arm,pl061", "arm,primecell"; 413 reg = <0 0xe8a0b000 0 0x1000>; 414 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 415 gpio-controller; 416 #gpio-cells = <2>; 417 gpio-ranges = <&pmx0 1 0 7>; 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 421 clock-names = "apb_pclk"; 422 }; 423 424 gpio1: gpio@e8a0c000 { 425 compatible = "arm,pl061", "arm,primecell"; 426 reg = <0 0xe8a0c000 0 0x1000>; 427 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 gpio-ranges = <&pmx0 1 7 7>; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 434 clock-names = "apb_pclk"; 435 }; 436 437 gpio2: gpio@e8a0d000 { 438 compatible = "arm,pl061", "arm,primecell"; 439 reg = <0 0xe8a0d000 0 0x1000>; 440 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 gpio-ranges = <&pmx0 0 14 8>; 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 447 clock-names = "apb_pclk"; 448 }; 449 450 gpio3: gpio@e8a0e000 { 451 compatible = "arm,pl061", "arm,primecell"; 452 reg = <0 0xe8a0e000 0 0x1000>; 453 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 454 gpio-controller; 455 #gpio-cells = <2>; 456 gpio-ranges = <&pmx0 0 22 8>; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 460 clock-names = "apb_pclk"; 461 }; 462 463 gpio4: gpio@e8a0f000 { 464 compatible = "arm,pl061", "arm,primecell"; 465 reg = <0 0xe8a0f000 0 0x1000>; 466 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 gpio-ranges = <&pmx0 0 30 8>; 470 interrupt-controller; 471 #interrupt-cells = <2>; 472 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 473 clock-names = "apb_pclk"; 474 }; 475 476 gpio5: gpio@e8a10000 { 477 compatible = "arm,pl061", "arm,primecell"; 478 reg = <0 0xe8a10000 0 0x1000>; 479 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 480 gpio-controller; 481 #gpio-cells = <2>; 482 gpio-ranges = <&pmx0 0 38 8>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 486 clock-names = "apb_pclk"; 487 }; 488 489 gpio6: gpio@e8a11000 { 490 compatible = "arm,pl061", "arm,primecell"; 491 reg = <0 0xe8a11000 0 0x1000>; 492 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 493 gpio-controller; 494 #gpio-cells = <2>; 495 gpio-ranges = <&pmx0 0 46 8>; 496 interrupt-controller; 497 #interrupt-cells = <2>; 498 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 499 clock-names = "apb_pclk"; 500 }; 501 502 gpio7: gpio@e8a12000 { 503 compatible = "arm,pl061", "arm,primecell"; 504 reg = <0 0xe8a12000 0 0x1000>; 505 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 506 gpio-controller; 507 #gpio-cells = <2>; 508 gpio-ranges = <&pmx0 0 54 8>; 509 interrupt-controller; 510 #interrupt-cells = <2>; 511 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 512 clock-names = "apb_pclk"; 513 }; 514 515 gpio8: gpio@e8a13000 { 516 compatible = "arm,pl061", "arm,primecell"; 517 reg = <0 0xe8a13000 0 0x1000>; 518 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 gpio-ranges = <&pmx0 0 62 8>; 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 525 clock-names = "apb_pclk"; 526 }; 527 528 gpio9: gpio@e8a14000 { 529 compatible = "arm,pl061", "arm,primecell"; 530 reg = <0 0xe8a14000 0 0x1000>; 531 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 532 gpio-controller; 533 #gpio-cells = <2>; 534 gpio-ranges = <&pmx0 0 70 8>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 538 clock-names = "apb_pclk"; 539 }; 540 541 gpio10: gpio@e8a15000 { 542 compatible = "arm,pl061", "arm,primecell"; 543 reg = <0 0xe8a15000 0 0x1000>; 544 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 545 gpio-controller; 546 #gpio-cells = <2>; 547 gpio-ranges = <&pmx0 0 78 8>; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 551 clock-names = "apb_pclk"; 552 }; 553 554 gpio11: gpio@e8a16000 { 555 compatible = "arm,pl061", "arm,primecell"; 556 reg = <0 0xe8a16000 0 0x1000>; 557 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 558 gpio-controller; 559 #gpio-cells = <2>; 560 gpio-ranges = <&pmx0 0 86 8>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 564 clock-names = "apb_pclk"; 565 }; 566 567 gpio12: gpio@e8a17000 { 568 compatible = "arm,pl061", "arm,primecell"; 569 reg = <0 0xe8a17000 0 0x1000>; 570 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 571 gpio-controller; 572 #gpio-cells = <2>; 573 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 577 clock-names = "apb_pclk"; 578 }; 579 580 gpio13: gpio@e8a18000 { 581 compatible = "arm,pl061", "arm,primecell"; 582 reg = <0 0xe8a18000 0 0x1000>; 583 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 584 gpio-controller; 585 #gpio-cells = <2>; 586 gpio-ranges = <&pmx0 0 102 8>; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 590 clock-names = "apb_pclk"; 591 }; 592 593 gpio14: gpio@e8a19000 { 594 compatible = "arm,pl061", "arm,primecell"; 595 reg = <0 0xe8a19000 0 0x1000>; 596 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 597 gpio-controller; 598 #gpio-cells = <2>; 599 gpio-ranges = <&pmx0 0 110 8>; 600 interrupt-controller; 601 #interrupt-cells = <2>; 602 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 603 clock-names = "apb_pclk"; 604 }; 605 606 gpio15: gpio@e8a1a000 { 607 compatible = "arm,pl061", "arm,primecell"; 608 reg = <0 0xe8a1a000 0 0x1000>; 609 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 610 gpio-controller; 611 #gpio-cells = <2>; 612 gpio-ranges = <&pmx0 0 118 6>; 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 616 clock-names = "apb_pclk"; 617 }; 618 619 gpio16: gpio@e8a1b000 { 620 compatible = "arm,pl061", "arm,primecell"; 621 reg = <0 0xe8a1b000 0 0x1000>; 622 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 623 gpio-controller; 624 #gpio-cells = <2>; 625 interrupt-controller; 626 #interrupt-cells = <2>; 627 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 628 clock-names = "apb_pclk"; 629 }; 630 631 gpio17: gpio@e8a1c000 { 632 compatible = "arm,pl061", "arm,primecell"; 633 reg = <0 0xe8a1c000 0 0x1000>; 634 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 635 gpio-controller; 636 #gpio-cells = <2>; 637 interrupt-controller; 638 #interrupt-cells = <2>; 639 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 640 clock-names = "apb_pclk"; 641 }; 642 643 gpio18: gpio@ff3b4000 { 644 compatible = "arm,pl061", "arm,primecell"; 645 reg = <0 0xff3b4000 0 0x1000>; 646 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 647 gpio-controller; 648 #gpio-cells = <2>; 649 gpio-ranges = <&pmx2 0 0 8>; 650 interrupt-controller; 651 #interrupt-cells = <2>; 652 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 653 clock-names = "apb_pclk"; 654 }; 655 656 gpio19: gpio@ff3b5000 { 657 compatible = "arm,pl061", "arm,primecell"; 658 reg = <0 0xff3b5000 0 0x1000>; 659 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 660 gpio-controller; 661 #gpio-cells = <2>; 662 gpio-ranges = <&pmx2 0 8 4>; 663 interrupt-controller; 664 #interrupt-cells = <2>; 665 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 666 clock-names = "apb_pclk"; 667 }; 668 669 gpio20: gpio@e8a1f000 { 670 compatible = "arm,pl061", "arm,primecell"; 671 reg = <0 0xe8a1f000 0 0x1000>; 672 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 673 gpio-controller; 674 #gpio-cells = <2>; 675 gpio-ranges = <&pmx1 0 0 6>; 676 interrupt-controller; 677 #interrupt-cells = <2>; 678 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 679 clock-names = "apb_pclk"; 680 }; 681 682 gpio21: gpio@e8a20000 { 683 compatible = "arm,pl061", "arm,primecell"; 684 reg = <0 0xe8a20000 0 0x1000>; 685 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 686 gpio-controller; 687 #gpio-cells = <2>; 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 gpio-ranges = <&pmx3 0 0 6>; 691 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 692 clock-names = "apb_pclk"; 693 }; 694 695 gpio22: gpio@fff0b000 { 696 compatible = "arm,pl061", "arm,primecell"; 697 reg = <0 0xfff0b000 0 0x1000>; 698 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 699 gpio-controller; 700 #gpio-cells = <2>; 701 /* GPIO176 */ 702 gpio-ranges = <&pmx4 2 0 6>; 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 706 clock-names = "apb_pclk"; 707 }; 708 709 gpio23: gpio@fff0c000 { 710 compatible = "arm,pl061", "arm,primecell"; 711 reg = <0 0xfff0c000 0 0x1000>; 712 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 713 gpio-controller; 714 #gpio-cells = <2>; 715 /* GPIO184 */ 716 gpio-ranges = <&pmx4 0 6 7>; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 720 clock-names = "apb_pclk"; 721 }; 722 723 gpio24: gpio@fff0d000 { 724 compatible = "arm,pl061", "arm,primecell"; 725 reg = <0 0xfff0d000 0 0x1000>; 726 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 727 gpio-controller; 728 #gpio-cells = <2>; 729 /* GPIO192 */ 730 gpio-ranges = <&pmx4 0 13 8>; 731 interrupt-controller; 732 #interrupt-cells = <2>; 733 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 734 clock-names = "apb_pclk"; 735 }; 736 737 gpio25: gpio@fff0e000 { 738 compatible = "arm,pl061", "arm,primecell"; 739 reg = <0 0xfff0e000 0 0x1000>; 740 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 741 gpio-controller; 742 #gpio-cells = <2>; 743 /* GPIO200 */ 744 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 748 clock-names = "apb_pclk"; 749 }; 750 751 gpio26: gpio@fff0f000 { 752 compatible = "arm,pl061", "arm,primecell"; 753 reg = <0 0xfff0f000 0 0x1000>; 754 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 755 gpio-controller; 756 #gpio-cells = <2>; 757 /* GPIO208 */ 758 gpio-ranges = <&pmx4 0 28 8>; 759 interrupt-controller; 760 #interrupt-cells = <2>; 761 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 762 clock-names = "apb_pclk"; 763 }; 764 765 gpio27: gpio@fff10000 { 766 compatible = "arm,pl061", "arm,primecell"; 767 reg = <0 0xfff10000 0 0x1000>; 768 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 769 gpio-controller; 770 #gpio-cells = <2>; 771 /* GPIO216 */ 772 gpio-ranges = <&pmx4 0 36 6>; 773 interrupt-controller; 774 #interrupt-cells = <2>; 775 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 776 clock-names = "apb_pclk"; 777 }; 778 779 gpio28: gpio@fff1d000 { 780 compatible = "arm,pl061", "arm,primecell"; 781 reg = <0 0xfff1d000 0 0x1000>; 782 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 783 gpio-controller; 784 #gpio-cells = <2>; 785 interrupt-controller; 786 #interrupt-cells = <2>; 787 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 788 clock-names = "apb_pclk"; 789 }; 790 791 spi2: spi@ffd68000 { 792 compatible = "arm,pl022", "arm,primecell"; 793 reg = <0x0 0xffd68000 0x0 0x1000>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 798 clock-names = "apb_pclk"; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&spi2_pmx_func>; 801 num-cs = <1>; 802 cs-gpios = <&gpio27 2 0>; 803 status = "disabled"; 804 }; 805 806 spi3: spi@ff3b3000 { 807 compatible = "arm,pl022", "arm,primecell"; 808 reg = <0x0 0xff3b3000 0x0 0x1000>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 813 clock-names = "apb_pclk"; 814 pinctrl-names = "default"; 815 pinctrl-0 = <&spi3_pmx_func>; 816 num-cs = <1>; 817 cs-gpios = <&gpio18 5 0>; 818 status = "disabled"; 819 }; 820 821 pcie@f4000000 { 822 compatible = "hisilicon,kirin960-pcie"; 823 reg = <0x0 0xf4000000 0x0 0x1000>, 824 <0x0 0xff3fe000 0x0 0x1000>, 825 <0x0 0xf3f20000 0x0 0x40000>, 826 <0x0 0xf5000000 0x0 0x2000>; 827 reg-names = "dbi", "apb", "phy", "config"; 828 bus-range = <0x0 0x1>; 829 #address-cells = <3>; 830 #size-cells = <2>; 831 device_type = "pci"; 832 ranges = <0x02000000 0x0 0x00000000 833 0x0 0xf6000000 834 0x0 0x02000000>; 835 num-lanes = <1>; 836 #interrupt-cells = <1>; 837 interrupt-map-mask = <0xf800 0 0 7>; 838 interrupt-map = <0x0 0 0 1 839 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 840 <0x0 0 0 2 841 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 842 <0x0 0 0 3 843 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 844 <0x0 0 0 4 845 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 847 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 848 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 849 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 850 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 851 clock-names = "pcie_phy_ref", "pcie_aux", 852 "pcie_apb_phy", "pcie_apb_sys", 853 "pcie_aclk"; 854 reset-gpios = <&gpio11 1 0 >; 855 }; 856 857 /* SD */ 858 dwmmc1: dwmmc1@ff37f000 { 859 #address-cells = <1>; 860 #size-cells = <0>; 861 cd-inverted; 862 compatible = "hisilicon,hi3660-dw-mshc"; 863 num-slots = <1>; 864 bus-width = <0x4>; 865 disable-wp; 866 cap-sd-highspeed; 867 supports-highspeed; 868 card-detect-delay = <200>; 869 reg = <0x0 0xff37f000 0x0 0x1000>; 870 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 872 <&crg_ctrl HI3660_HCLK_GATE_SD>; 873 clock-names = "ciu", "biu"; 874 clock-frequency = <3200000>; 875 resets = <&crg_rst 0x94 18>; 876 cd-gpios = <&gpio25 3 0>; 877 hisilicon,peripheral-syscon = <&sctrl>; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&sd_pmx_func 880 &sd_clk_cfg_func 881 &sd_cfg_func>; 882 sd-uhs-sdr12; 883 sd-uhs-sdr25; 884 sd-uhs-sdr50; 885 sd-uhs-sdr104; 886 status = "disabled"; 887 888 slot@0 { 889 reg = <0x0>; 890 bus-width = <4>; 891 disable-wp; 892 }; 893 }; 894 895 /* SDIO */ 896 dwmmc2: dwmmc2@ff3ff000 { 897 compatible = "hisilicon,hi3660-dw-mshc"; 898 reg = <0x0 0xff3ff000 0x0 0x1000>; 899 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 900 num-slots = <1>; 901 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 902 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 903 clock-names = "ciu", "biu"; 904 resets = <&crg_rst 0x94 20>; 905 card-detect-delay = <200>; 906 supports-highspeed; 907 keep-power-in-suspend; 908 pinctrl-names = "default"; 909 pinctrl-0 = <&sdio_pmx_func 910 &sdio_clk_cfg_func 911 &sdio_cfg_func>; 912 status = "disabled"; 913 }; 914 }; 915}; 916