1/* 2 * dts file for Hisilicon Hi3660 SoC 3 * 4 * Copyright (C) 2016, Hisilicon Ltd. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/hi3660-clock.h> 9 10/ { 11 compatible = "hisilicon,hi3660"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 psci { 17 compatible = "arm,psci-0.2"; 18 method = "smc"; 19 }; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53", "arm,armv8"; 58 device_type = "cpu"; 59 reg = <0x0 0x0>; 60 enable-method = "psci"; 61 }; 62 63 cpu1: cpu@1 { 64 compatible = "arm,cortex-a53", "arm,armv8"; 65 device_type = "cpu"; 66 reg = <0x0 0x1>; 67 enable-method = "psci"; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 device_type = "cpu"; 73 reg = <0x0 0x2>; 74 enable-method = "psci"; 75 }; 76 77 cpu3: cpu@3 { 78 compatible = "arm,cortex-a53", "arm,armv8"; 79 device_type = "cpu"; 80 reg = <0x0 0x3>; 81 enable-method = "psci"; 82 }; 83 84 cpu4: cpu@100 { 85 compatible = "arm,cortex-a73", "arm,armv8"; 86 device_type = "cpu"; 87 reg = <0x0 0x100>; 88 enable-method = "psci"; 89 }; 90 91 cpu5: cpu@101 { 92 compatible = "arm,cortex-a73", "arm,armv8"; 93 device_type = "cpu"; 94 reg = <0x0 0x101>; 95 enable-method = "psci"; 96 }; 97 98 cpu6: cpu@102 { 99 compatible = "arm,cortex-a73", "arm,armv8"; 100 device_type = "cpu"; 101 reg = <0x0 0x102>; 102 enable-method = "psci"; 103 }; 104 105 cpu7: cpu@103 { 106 compatible = "arm,cortex-a73", "arm,armv8"; 107 device_type = "cpu"; 108 reg = <0x0 0x103>; 109 enable-method = "psci"; 110 }; 111 }; 112 113 gic: interrupt-controller@e82b0000 { 114 compatible = "arm,gic-400"; 115 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 116 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 117 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 118 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 119 #address-cells = <0>; 120 #interrupt-cells = <3>; 121 interrupt-controller; 122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 123 IRQ_TYPE_LEVEL_HIGH)>; 124 }; 125 126 timer { 127 compatible = "arm,armv8-timer"; 128 interrupt-parent = <&gic>; 129 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 130 IRQ_TYPE_LEVEL_LOW)>, 131 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 132 IRQ_TYPE_LEVEL_LOW)>, 133 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 134 IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 136 IRQ_TYPE_LEVEL_LOW)>; 137 }; 138 139 soc { 140 compatible = "simple-bus"; 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 145 crg_ctrl: crg_ctrl@fff35000 { 146 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 147 reg = <0x0 0xfff35000 0x0 0x1000>; 148 #clock-cells = <1>; 149 }; 150 151 crg_rst: crg_rst_controller { 152 compatible = "hisilicon,hi3660-reset"; 153 #reset-cells = <2>; 154 hisi,rst-syscon = <&crg_ctrl>; 155 }; 156 157 158 pctrl: pctrl@e8a09000 { 159 compatible = "hisilicon,hi3660-pctrl", "syscon"; 160 reg = <0x0 0xe8a09000 0x0 0x2000>; 161 #clock-cells = <1>; 162 }; 163 164 pmuctrl: crg_ctrl@fff34000 { 165 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 166 reg = <0x0 0xfff34000 0x0 0x1000>; 167 #clock-cells = <1>; 168 }; 169 170 sctrl: sctrl@fff0a000 { 171 compatible = "hisilicon,hi3660-sctrl", "syscon"; 172 reg = <0x0 0xfff0a000 0x0 0x1000>; 173 #clock-cells = <1>; 174 }; 175 176 iomcu: iomcu@ffd7e000 { 177 compatible = "hisilicon,hi3660-iomcu", "syscon"; 178 reg = <0x0 0xffd7e000 0x0 0x1000>; 179 #clock-cells = <1>; 180 181 }; 182 183 iomcu_rst: reset { 184 compatible = "hisilicon,hi3660-reset"; 185 hisi,rst-syscon = <&iomcu>; 186 #reset-cells = <2>; 187 }; 188 189 i2c0: i2c@ffd71000 { 190 compatible = "snps,designware-i2c"; 191 reg = <0x0 0xffd71000 0x0 0x1000>; 192 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 clock-frequency = <400000>; 196 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 197 resets = <&iomcu_rst 0x20 3>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 200 status = "disabled"; 201 }; 202 203 i2c1: i2c@ffd72000 { 204 compatible = "snps,designware-i2c"; 205 reg = <0x0 0xffd72000 0x0 0x1000>; 206 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 clock-frequency = <400000>; 210 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 211 resets = <&iomcu_rst 0x20 4>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 214 status = "disabled"; 215 }; 216 217 i2c3: i2c@fdf0c000 { 218 compatible = "snps,designware-i2c"; 219 reg = <0x0 0xfdf0c000 0x0 0x1000>; 220 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 clock-frequency = <400000>; 224 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 225 resets = <&crg_rst 0x78 7>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 228 status = "disabled"; 229 }; 230 231 i2c7: i2c@fdf0b000 { 232 compatible = "snps,designware-i2c"; 233 reg = <0x0 0xfdf0b000 0x0 0x1000>; 234 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 clock-frequency = <400000>; 238 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 239 resets = <&crg_rst 0x60 14>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 242 status = "disabled"; 243 }; 244 245 uart0: serial@fdf02000 { 246 compatible = "arm,pl011", "arm,primecell"; 247 reg = <0x0 0xfdf02000 0x0 0x1000>; 248 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 250 <&crg_ctrl HI3660_PCLK>; 251 clock-names = "uartclk", "apb_pclk"; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 254 status = "disabled"; 255 }; 256 257 uart1: serial@fdf00000 { 258 compatible = "arm,pl011", "arm,primecell"; 259 reg = <0x0 0xfdf00000 0x0 0x1000>; 260 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 262 <&crg_ctrl HI3660_CLK_GATE_UART1>; 263 clock-names = "uartclk", "apb_pclk"; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 266 status = "disabled"; 267 }; 268 269 uart2: serial@fdf03000 { 270 compatible = "arm,pl011", "arm,primecell"; 271 reg = <0x0 0xfdf03000 0x0 0x1000>; 272 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 274 <&crg_ctrl HI3660_PCLK>; 275 clock-names = "uartclk", "apb_pclk"; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 278 status = "disabled"; 279 }; 280 281 uart3: serial@ffd74000 { 282 compatible = "arm,pl011", "arm,primecell"; 283 reg = <0x0 0xffd74000 0x0 0x1000>; 284 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 286 <&crg_ctrl HI3660_PCLK>; 287 clock-names = "uartclk", "apb_pclk"; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 290 status = "disabled"; 291 }; 292 293 uart4: serial@fdf01000 { 294 compatible = "arm,pl011", "arm,primecell"; 295 reg = <0x0 0xfdf01000 0x0 0x1000>; 296 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 298 <&crg_ctrl HI3660_CLK_GATE_UART4>; 299 clock-names = "uartclk", "apb_pclk"; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 302 status = "disabled"; 303 }; 304 305 uart5: serial@fdf05000 { 306 compatible = "arm,pl011", "arm,primecell"; 307 reg = <0x0 0xfdf05000 0x0 0x1000>; 308 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 310 <&crg_ctrl HI3660_CLK_GATE_UART5>; 311 clock-names = "uartclk", "apb_pclk"; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 314 status = "disabled"; 315 }; 316 317 uart6: serial@fff32000 { 318 compatible = "arm,pl011", "arm,primecell"; 319 reg = <0x0 0xfff32000 0x0 0x1000>; 320 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&crg_ctrl HI3660_CLK_UART6>, 322 <&crg_ctrl HI3660_PCLK>; 323 clock-names = "uartclk", "apb_pclk"; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 326 status = "disabled"; 327 }; 328 329 gpio0: gpio@e8a0b000 { 330 compatible = "arm,pl061", "arm,primecell"; 331 reg = <0 0xe8a0b000 0 0x1000>; 332 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 gpio-ranges = <&pmx0 1 0 7>; 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 339 clock-names = "apb_pclk"; 340 }; 341 342 gpio1: gpio@e8a0c000 { 343 compatible = "arm,pl061", "arm,primecell"; 344 reg = <0 0xe8a0c000 0 0x1000>; 345 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 gpio-ranges = <&pmx0 1 7 7>; 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 352 clock-names = "apb_pclk"; 353 }; 354 355 gpio2: gpio@e8a0d000 { 356 compatible = "arm,pl061", "arm,primecell"; 357 reg = <0 0xe8a0d000 0 0x1000>; 358 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 gpio-ranges = <&pmx0 0 14 8>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 365 clock-names = "apb_pclk"; 366 }; 367 368 gpio3: gpio@e8a0e000 { 369 compatible = "arm,pl061", "arm,primecell"; 370 reg = <0 0xe8a0e000 0 0x1000>; 371 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 gpio-ranges = <&pmx0 0 22 8>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 378 clock-names = "apb_pclk"; 379 }; 380 381 gpio4: gpio@e8a0f000 { 382 compatible = "arm,pl061", "arm,primecell"; 383 reg = <0 0xe8a0f000 0 0x1000>; 384 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 385 gpio-controller; 386 #gpio-cells = <2>; 387 gpio-ranges = <&pmx0 0 30 8>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 391 clock-names = "apb_pclk"; 392 }; 393 394 gpio5: gpio@e8a10000 { 395 compatible = "arm,pl061", "arm,primecell"; 396 reg = <0 0xe8a10000 0 0x1000>; 397 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 398 gpio-controller; 399 #gpio-cells = <2>; 400 gpio-ranges = <&pmx0 0 38 8>; 401 interrupt-controller; 402 #interrupt-cells = <2>; 403 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 404 clock-names = "apb_pclk"; 405 }; 406 407 gpio6: gpio@e8a11000 { 408 compatible = "arm,pl061", "arm,primecell"; 409 reg = <0 0xe8a11000 0 0x1000>; 410 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 411 gpio-controller; 412 #gpio-cells = <2>; 413 gpio-ranges = <&pmx0 0 46 8>; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 417 clock-names = "apb_pclk"; 418 }; 419 420 gpio7: gpio@e8a12000 { 421 compatible = "arm,pl061", "arm,primecell"; 422 reg = <0 0xe8a12000 0 0x1000>; 423 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 424 gpio-controller; 425 #gpio-cells = <2>; 426 gpio-ranges = <&pmx0 0 54 8>; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 430 clock-names = "apb_pclk"; 431 }; 432 433 gpio8: gpio@e8a13000 { 434 compatible = "arm,pl061", "arm,primecell"; 435 reg = <0 0xe8a13000 0 0x1000>; 436 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 437 gpio-controller; 438 #gpio-cells = <2>; 439 gpio-ranges = <&pmx0 0 62 8>; 440 interrupt-controller; 441 #interrupt-cells = <2>; 442 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 443 clock-names = "apb_pclk"; 444 }; 445 446 gpio9: gpio@e8a14000 { 447 compatible = "arm,pl061", "arm,primecell"; 448 reg = <0 0xe8a14000 0 0x1000>; 449 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 450 gpio-controller; 451 #gpio-cells = <2>; 452 gpio-ranges = <&pmx0 0 70 8>; 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 456 clock-names = "apb_pclk"; 457 }; 458 459 gpio10: gpio@e8a15000 { 460 compatible = "arm,pl061", "arm,primecell"; 461 reg = <0 0xe8a15000 0 0x1000>; 462 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 463 gpio-controller; 464 #gpio-cells = <2>; 465 gpio-ranges = <&pmx0 0 78 8>; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 469 clock-names = "apb_pclk"; 470 }; 471 472 gpio11: gpio@e8a16000 { 473 compatible = "arm,pl061", "arm,primecell"; 474 reg = <0 0xe8a16000 0 0x1000>; 475 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 476 gpio-controller; 477 #gpio-cells = <2>; 478 gpio-ranges = <&pmx0 0 86 8>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 482 clock-names = "apb_pclk"; 483 }; 484 485 gpio12: gpio@e8a17000 { 486 compatible = "arm,pl061", "arm,primecell"; 487 reg = <0 0xe8a17000 0 0x1000>; 488 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 489 gpio-controller; 490 #gpio-cells = <2>; 491 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 492 interrupt-controller; 493 #interrupt-cells = <2>; 494 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 495 clock-names = "apb_pclk"; 496 }; 497 498 gpio13: gpio@e8a18000 { 499 compatible = "arm,pl061", "arm,primecell"; 500 reg = <0 0xe8a18000 0 0x1000>; 501 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 502 gpio-controller; 503 #gpio-cells = <2>; 504 gpio-ranges = <&pmx0 0 102 8>; 505 interrupt-controller; 506 #interrupt-cells = <2>; 507 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 508 clock-names = "apb_pclk"; 509 }; 510 511 gpio14: gpio@e8a19000 { 512 compatible = "arm,pl061", "arm,primecell"; 513 reg = <0 0xe8a19000 0 0x1000>; 514 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 515 gpio-controller; 516 #gpio-cells = <2>; 517 gpio-ranges = <&pmx0 0 110 8>; 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 521 clock-names = "apb_pclk"; 522 }; 523 524 gpio15: gpio@e8a1a000 { 525 compatible = "arm,pl061", "arm,primecell"; 526 reg = <0 0xe8a1a000 0 0x1000>; 527 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 528 gpio-controller; 529 #gpio-cells = <2>; 530 gpio-ranges = <&pmx0 0 118 6>; 531 interrupt-controller; 532 #interrupt-cells = <2>; 533 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 534 clock-names = "apb_pclk"; 535 }; 536 537 gpio16: gpio@e8a1b000 { 538 compatible = "arm,pl061", "arm,primecell"; 539 reg = <0 0xe8a1b000 0 0x1000>; 540 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 541 gpio-controller; 542 #gpio-cells = <2>; 543 interrupt-controller; 544 #interrupt-cells = <2>; 545 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 546 clock-names = "apb_pclk"; 547 }; 548 549 gpio17: gpio@e8a1c000 { 550 compatible = "arm,pl061", "arm,primecell"; 551 reg = <0 0xe8a1c000 0 0x1000>; 552 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 553 gpio-controller; 554 #gpio-cells = <2>; 555 interrupt-controller; 556 #interrupt-cells = <2>; 557 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 558 clock-names = "apb_pclk"; 559 }; 560 561 gpio18: gpio@ff3b4000 { 562 compatible = "arm,pl061", "arm,primecell"; 563 reg = <0 0xff3b4000 0 0x1000>; 564 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 565 gpio-controller; 566 #gpio-cells = <2>; 567 gpio-ranges = <&pmx2 0 0 8>; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 571 clock-names = "apb_pclk"; 572 }; 573 574 gpio19: gpio@ff3b5000 { 575 compatible = "arm,pl061", "arm,primecell"; 576 reg = <0 0xff3b5000 0 0x1000>; 577 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 578 gpio-controller; 579 #gpio-cells = <2>; 580 gpio-ranges = <&pmx2 0 8 4>; 581 interrupt-controller; 582 #interrupt-cells = <2>; 583 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 584 clock-names = "apb_pclk"; 585 }; 586 587 gpio20: gpio@e8a1f000 { 588 compatible = "arm,pl061", "arm,primecell"; 589 reg = <0 0xe8a1f000 0 0x1000>; 590 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 591 gpio-controller; 592 #gpio-cells = <2>; 593 gpio-ranges = <&pmx1 0 0 6>; 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 597 clock-names = "apb_pclk"; 598 }; 599 600 gpio21: gpio@e8a20000 { 601 compatible = "arm,pl061", "arm,primecell"; 602 reg = <0 0xe8a20000 0 0x1000>; 603 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 604 gpio-controller; 605 #gpio-cells = <2>; 606 interrupt-controller; 607 #interrupt-cells = <2>; 608 gpio-ranges = <&pmx3 0 0 6>; 609 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 610 clock-names = "apb_pclk"; 611 }; 612 613 gpio22: gpio@fff0b000 { 614 compatible = "arm,pl061", "arm,primecell"; 615 reg = <0 0xfff0b000 0 0x1000>; 616 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 617 gpio-controller; 618 #gpio-cells = <2>; 619 /* GPIO176 */ 620 gpio-ranges = <&pmx4 2 0 6>; 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 624 clock-names = "apb_pclk"; 625 }; 626 627 gpio23: gpio@fff0c000 { 628 compatible = "arm,pl061", "arm,primecell"; 629 reg = <0 0xfff0c000 0 0x1000>; 630 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 631 gpio-controller; 632 #gpio-cells = <2>; 633 /* GPIO184 */ 634 gpio-ranges = <&pmx4 0 6 7>; 635 interrupt-controller; 636 #interrupt-cells = <2>; 637 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 638 clock-names = "apb_pclk"; 639 }; 640 641 gpio24: gpio@fff0d000 { 642 compatible = "arm,pl061", "arm,primecell"; 643 reg = <0 0xfff0d000 0 0x1000>; 644 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 645 gpio-controller; 646 #gpio-cells = <2>; 647 /* GPIO192 */ 648 gpio-ranges = <&pmx4 0 13 8>; 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 652 clock-names = "apb_pclk"; 653 }; 654 655 gpio25: gpio@fff0e000 { 656 compatible = "arm,pl061", "arm,primecell"; 657 reg = <0 0xfff0e000 0 0x1000>; 658 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 659 gpio-controller; 660 #gpio-cells = <2>; 661 /* GPIO200 */ 662 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 663 interrupt-controller; 664 #interrupt-cells = <2>; 665 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 666 clock-names = "apb_pclk"; 667 }; 668 669 gpio26: gpio@fff0f000 { 670 compatible = "arm,pl061", "arm,primecell"; 671 reg = <0 0xfff0f000 0 0x1000>; 672 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 673 gpio-controller; 674 #gpio-cells = <2>; 675 /* GPIO208 */ 676 gpio-ranges = <&pmx4 0 28 8>; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 680 clock-names = "apb_pclk"; 681 }; 682 683 gpio27: gpio@fff10000 { 684 compatible = "arm,pl061", "arm,primecell"; 685 reg = <0 0xfff10000 0 0x1000>; 686 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 687 gpio-controller; 688 #gpio-cells = <2>; 689 /* GPIO216 */ 690 gpio-ranges = <&pmx4 0 36 6>; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 694 clock-names = "apb_pclk"; 695 }; 696 697 gpio28: gpio@fff1d000 { 698 compatible = "arm,pl061", "arm,primecell"; 699 reg = <0 0xfff1d000 0 0x1000>; 700 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 701 gpio-controller; 702 #gpio-cells = <2>; 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 706 clock-names = "apb_pclk"; 707 }; 708 }; 709}; 710