13686673dSChester Lin// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
23686673dSChester Lin/*
33686673dSChester Lin * Copyright (c) 2021 SUSE LLC
4*0c8bedf2SChester Lin * Copyright (c) 2019-2021 NXP
53686673dSChester Lin */
63686673dSChester Lin
73686673dSChester Lin/dts-v1/;
83686673dSChester Lin
93686673dSChester Lin#include "s32g2.dtsi"
103686673dSChester Lin
113686673dSChester Lin/ {
123686673dSChester Lin	model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
133686673dSChester Lin	compatible = "nxp,s32g274a-rdb2", "nxp,s32g2";
143686673dSChester Lin
153686673dSChester Lin	aliases {
163686673dSChester Lin		serial0 = &uart0;
173686673dSChester Lin		serial1 = &uart1;
183686673dSChester Lin	};
193686673dSChester Lin
203686673dSChester Lin	chosen {
213686673dSChester Lin		stdout-path = "serial0:115200n8";
223686673dSChester Lin	};
23*0c8bedf2SChester Lin
24*0c8bedf2SChester Lin	/* 4GiB RAM */
25*0c8bedf2SChester Lin	memory@80000000 {
26*0c8bedf2SChester Lin		device_type = "memory";
27*0c8bedf2SChester Lin		reg = <0x0 0x80000000 0 0x80000000>,
28*0c8bedf2SChester Lin		      <0x8 0x80000000 0 0x80000000>;
29*0c8bedf2SChester Lin	};
303686673dSChester Lin};
313686673dSChester Lin
323686673dSChester Lin/* UART (J2) to Micro USB port */
333686673dSChester Lin&uart0 {
343686673dSChester Lin	status = "okay";
353686673dSChester Lin};
363686673dSChester Lin
373686673dSChester Lin/* UART (J1) to Micro USB port */
383686673dSChester Lin&uart1 {
393686673dSChester Lin	status = "okay";
403686673dSChester Lin};
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