1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/fsl,imx93-power.h> 11 12#include "imx93-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 gpio0 = &gpio1; 21 gpio1 = &gpio2; 22 gpio2 = &gpio3; 23 gpio3 = &gpio4; 24 i2c0 = &lpi2c1; 25 i2c1 = &lpi2c2; 26 i2c2 = &lpi2c3; 27 i2c3 = &lpi2c4; 28 i2c4 = &lpi2c5; 29 i2c5 = &lpi2c6; 30 i2c6 = &lpi2c7; 31 i2c7 = &lpi2c8; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &lpuart1; 36 serial1 = &lpuart2; 37 serial2 = &lpuart3; 38 serial3 = &lpuart4; 39 serial4 = &lpuart5; 40 serial5 = &lpuart6; 41 serial6 = &lpuart7; 42 serial7 = &lpuart8; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 A55_0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 reg = <0x0>; 53 enable-method = "psci"; 54 #cooling-cells = <2>; 55 }; 56 57 A55_1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a55"; 60 reg = <0x100>; 61 enable-method = "psci"; 62 #cooling-cells = <2>; 63 }; 64 65 }; 66 67 osc_32k: clock-osc-32k { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <32768>; 71 clock-output-names = "osc_32k"; 72 }; 73 74 osc_24m: clock-osc-24m { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <24000000>; 78 clock-output-names = "osc_24m"; 79 }; 80 81 clk_ext1: clock-ext1 { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <133000000>; 85 clock-output-names = "clk_ext1"; 86 }; 87 88 pmu { 89 compatible = "arm,cortex-a55-pmu"; 90 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 91 }; 92 93 psci { 94 compatible = "arm,psci-1.0"; 95 method = "smc"; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 104 clock-frequency = <24000000>; 105 arm,no-tick-in-suspend; 106 interrupt-parent = <&gic>; 107 }; 108 109 gic: interrupt-controller@48000000 { 110 compatible = "arm,gic-v3"; 111 reg = <0 0x48000000 0 0x10000>, 112 <0 0x48040000 0 0xc0000>; 113 #interrupt-cells = <3>; 114 interrupt-controller; 115 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-parent = <&gic>; 117 }; 118 119 soc@0 { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0x0 0x0 0x0 0x80000000>, 124 <0x28000000 0x0 0x28000000 0x10000000>; 125 126 aips1: bus@44000000 { 127 compatible = "fsl,aips-bus", "simple-bus"; 128 reg = <0x44000000 0x800000>; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 anomix_ns_gpr: syscon@44210000 { 134 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 135 reg = <0x44210000 0x1000>; 136 }; 137 138 mu1: mailbox@44230000 { 139 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 140 reg = <0x44230000 0x10000>; 141 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&clk IMX93_CLK_MU1_B_GATE>; 143 #mbox-cells = <2>; 144 status = "disabled"; 145 }; 146 147 system_counter: timer@44290000 { 148 compatible = "nxp,sysctr-timer"; 149 reg = <0x44290000 0x30000>; 150 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&osc_24m>; 152 clock-names = "per"; 153 nxp,no-divider; 154 }; 155 156 tpm1: pwm@44310000 { 157 compatible = "fsl,imx7ulp-pwm"; 158 reg = <0x44310000 0x1000>; 159 clocks = <&clk IMX93_CLK_TPM1_GATE>; 160 #pwm-cells = <3>; 161 status = "disabled"; 162 }; 163 164 tpm2: pwm@44320000 { 165 compatible = "fsl,imx7ulp-pwm"; 166 reg = <0x44320000 0x10000>; 167 clocks = <&clk IMX93_CLK_TPM2_GATE>; 168 #pwm-cells = <3>; 169 status = "disabled"; 170 }; 171 172 lpi2c1: i2c@44340000 { 173 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 174 reg = <0x44340000 0x10000>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 179 <&clk IMX93_CLK_BUS_AON>; 180 clock-names = "per", "ipg"; 181 status = "disabled"; 182 }; 183 184 lpi2c2: i2c@44350000 { 185 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 186 reg = <0x44350000 0x10000>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 191 <&clk IMX93_CLK_BUS_AON>; 192 clock-names = "per", "ipg"; 193 status = "disabled"; 194 }; 195 196 lpspi1: spi@44360000 { 197 #address-cells = <1>; 198 #size-cells = <0>; 199 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 200 reg = <0x44360000 0x10000>; 201 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 203 <&clk IMX93_CLK_BUS_AON>; 204 clock-names = "per", "ipg"; 205 status = "disabled"; 206 }; 207 208 lpspi2: spi@44370000 { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 212 reg = <0x44370000 0x10000>; 213 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 215 <&clk IMX93_CLK_BUS_AON>; 216 clock-names = "per", "ipg"; 217 status = "disabled"; 218 }; 219 220 lpuart1: serial@44380000 { 221 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 222 reg = <0x44380000 0x1000>; 223 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 225 clock-names = "ipg"; 226 status = "disabled"; 227 }; 228 229 lpuart2: serial@44390000 { 230 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 231 reg = <0x44390000 0x1000>; 232 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 234 clock-names = "ipg"; 235 status = "disabled"; 236 }; 237 238 flexcan1: can@443a0000 { 239 compatible = "fsl,imx93-flexcan"; 240 reg = <0x443a0000 0x10000>; 241 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&clk IMX93_CLK_BUS_AON>, 243 <&clk IMX93_CLK_CAN1_GATE>; 244 clock-names = "ipg", "per"; 245 assigned-clocks = <&clk IMX93_CLK_CAN1>; 246 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 247 assigned-clock-rates = <40000000>; 248 fsl,clk-source = /bits/ 8 <0>; 249 status = "disabled"; 250 }; 251 252 iomuxc: pinctrl@443c0000 { 253 compatible = "fsl,imx93-iomuxc"; 254 reg = <0x443c0000 0x10000>; 255 status = "okay"; 256 }; 257 258 bbnsm: bbnsm@44440000 { 259 compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; 260 reg = <0x44440000 0x10000>; 261 262 bbnsm_rtc: rtc { 263 compatible = "nxp,imx93-bbnsm-rtc"; 264 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 265 }; 266 267 bbnsm_pwrkey: pwrkey { 268 compatible = "nxp,imx93-bbnsm-pwrkey"; 269 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 270 linux,code = <KEY_POWER>; 271 }; 272 }; 273 274 clk: clock-controller@44450000 { 275 compatible = "fsl,imx93-ccm"; 276 reg = <0x44450000 0x10000>; 277 #clock-cells = <1>; 278 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 279 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 280 status = "okay"; 281 }; 282 283 src: system-controller@44460000 { 284 compatible = "fsl,imx93-src", "syscon"; 285 reg = <0x44460000 0x10000>; 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges; 289 290 mediamix: power-domain@44462400 { 291 compatible = "fsl,imx93-src-slice"; 292 reg = <0x44462400 0x400>, <0x44465800 0x400>; 293 #power-domain-cells = <0>; 294 clocks = <&clk IMX93_CLK_MEDIA_AXI>, 295 <&clk IMX93_CLK_MEDIA_APB>; 296 }; 297 298 mlmix: power-domain@44461800 { 299 compatible = "fsl,imx93-src-slice"; 300 reg = <0x44461800 0x400>, <0x44464800 0x400>; 301 #power-domain-cells = <0>; 302 clocks = <&clk IMX93_CLK_ML_APB>, 303 <&clk IMX93_CLK_ML>; 304 }; 305 }; 306 307 anatop: anatop@44480000 { 308 compatible = "fsl,imx93-anatop", "syscon"; 309 reg = <0x44480000 0x10000>; 310 }; 311 312 adc1: adc@44530000 { 313 compatible = "nxp,imx93-adc"; 314 reg = <0x44530000 0x10000>; 315 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX93_CLK_ADC1_GATE>; 320 clock-names = "ipg"; 321 #io-channel-cells = <1>; 322 status = "disabled"; 323 }; 324 }; 325 326 aips2: bus@42000000 { 327 compatible = "fsl,aips-bus", "simple-bus"; 328 reg = <0x42000000 0x800000>; 329 #address-cells = <1>; 330 #size-cells = <1>; 331 ranges; 332 333 wakeupmix_gpr: syscon@42420000 { 334 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 335 reg = <0x42420000 0x1000>; 336 }; 337 338 mu2: mailbox@42440000 { 339 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 340 reg = <0x42440000 0x10000>; 341 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&clk IMX93_CLK_MU2_B_GATE>; 343 #mbox-cells = <2>; 344 status = "disabled"; 345 }; 346 347 tpm3: pwm@424e0000 { 348 compatible = "fsl,imx7ulp-pwm"; 349 reg = <0x424e0000 0x1000>; 350 clocks = <&clk IMX93_CLK_TPM3_GATE>; 351 #pwm-cells = <3>; 352 status = "disabled"; 353 }; 354 355 tpm4: pwm@424f0000 { 356 compatible = "fsl,imx7ulp-pwm"; 357 reg = <0x424f0000 0x10000>; 358 clocks = <&clk IMX93_CLK_TPM4_GATE>; 359 #pwm-cells = <3>; 360 status = "disabled"; 361 }; 362 363 tpm5: pwm@42500000 { 364 compatible = "fsl,imx7ulp-pwm"; 365 reg = <0x42500000 0x10000>; 366 clocks = <&clk IMX93_CLK_TPM5_GATE>; 367 #pwm-cells = <3>; 368 status = "disabled"; 369 }; 370 371 tpm6: pwm@42510000 { 372 compatible = "fsl,imx7ulp-pwm"; 373 reg = <0x42510000 0x10000>; 374 clocks = <&clk IMX93_CLK_TPM6_GATE>; 375 #pwm-cells = <3>; 376 status = "disabled"; 377 }; 378 379 lpi2c3: i2c@42530000 { 380 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 381 reg = <0x42530000 0x10000>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 386 <&clk IMX93_CLK_BUS_WAKEUP>; 387 clock-names = "per", "ipg"; 388 status = "disabled"; 389 }; 390 391 lpi2c4: i2c@42540000 { 392 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 393 reg = <0x42540000 0x10000>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 398 <&clk IMX93_CLK_BUS_WAKEUP>; 399 clock-names = "per", "ipg"; 400 status = "disabled"; 401 }; 402 403 lpspi3: spi@42550000 { 404 #address-cells = <1>; 405 #size-cells = <0>; 406 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 407 reg = <0x42550000 0x10000>; 408 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&clk IMX93_CLK_LPSPI3_GATE>, 410 <&clk IMX93_CLK_BUS_WAKEUP>; 411 clock-names = "per", "ipg"; 412 status = "disabled"; 413 }; 414 415 lpspi4: spi@42560000 { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 419 reg = <0x42560000 0x10000>; 420 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clk IMX93_CLK_LPSPI4_GATE>, 422 <&clk IMX93_CLK_BUS_WAKEUP>; 423 clock-names = "per", "ipg"; 424 status = "disabled"; 425 }; 426 427 lpuart3: serial@42570000 { 428 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 429 reg = <0x42570000 0x1000>; 430 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 432 clock-names = "ipg"; 433 status = "disabled"; 434 }; 435 436 lpuart4: serial@42580000 { 437 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 438 reg = <0x42580000 0x1000>; 439 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 441 clock-names = "ipg"; 442 status = "disabled"; 443 }; 444 445 lpuart5: serial@42590000 { 446 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 447 reg = <0x42590000 0x1000>; 448 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 450 clock-names = "ipg"; 451 status = "disabled"; 452 }; 453 454 lpuart6: serial@425a0000 { 455 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 456 reg = <0x425a0000 0x1000>; 457 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 459 clock-names = "ipg"; 460 status = "disabled"; 461 }; 462 463 flexcan2: can@425b0000 { 464 compatible = "fsl,imx93-flexcan"; 465 reg = <0x425b0000 0x10000>; 466 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 468 <&clk IMX93_CLK_CAN2_GATE>; 469 clock-names = "ipg", "per"; 470 assigned-clocks = <&clk IMX93_CLK_CAN2>; 471 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 472 assigned-clock-rates = <40000000>; 473 fsl,clk-source = /bits/ 8 <0>; 474 status = "disabled"; 475 }; 476 477 flexspi1: spi@425e0000 { 478 compatible = "nxp,imx8mm-fspi"; 479 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; 480 reg-names = "fspi_base", "fspi_mmap"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, 485 <&clk IMX93_CLK_FLEXSPI1_GATE>; 486 clock-names = "fspi_en", "fspi"; 487 assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; 488 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 489 status = "disabled"; 490 }; 491 492 lpuart7: serial@42690000 { 493 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 494 reg = <0x42690000 0x1000>; 495 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 497 clock-names = "ipg"; 498 status = "disabled"; 499 }; 500 501 lpuart8: serial@426a0000 { 502 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 503 reg = <0x426a0000 0x1000>; 504 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 506 clock-names = "ipg"; 507 status = "disabled"; 508 }; 509 510 lpi2c5: i2c@426b0000 { 511 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 512 reg = <0x426b0000 0x10000>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 517 <&clk IMX93_CLK_BUS_WAKEUP>; 518 clock-names = "per", "ipg"; 519 status = "disabled"; 520 }; 521 522 lpi2c6: i2c@426c0000 { 523 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 524 reg = <0x426c0000 0x10000>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 529 <&clk IMX93_CLK_BUS_WAKEUP>; 530 clock-names = "per", "ipg"; 531 status = "disabled"; 532 }; 533 534 lpi2c7: i2c@426d0000 { 535 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 536 reg = <0x426d0000 0x10000>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 541 <&clk IMX93_CLK_BUS_WAKEUP>; 542 clock-names = "per", "ipg"; 543 status = "disabled"; 544 }; 545 546 lpi2c8: i2c@426e0000 { 547 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 548 reg = <0x426e0000 0x10000>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 553 <&clk IMX93_CLK_BUS_WAKEUP>; 554 clock-names = "per", "ipg"; 555 status = "disabled"; 556 }; 557 558 lpspi5: spi@426f0000 { 559 #address-cells = <1>; 560 #size-cells = <0>; 561 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 562 reg = <0x426f0000 0x10000>; 563 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&clk IMX93_CLK_LPSPI5_GATE>, 565 <&clk IMX93_CLK_BUS_WAKEUP>; 566 clock-names = "per", "ipg"; 567 status = "disabled"; 568 }; 569 570 lpspi6: spi@42700000 { 571 #address-cells = <1>; 572 #size-cells = <0>; 573 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 574 reg = <0x42700000 0x10000>; 575 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&clk IMX93_CLK_LPSPI6_GATE>, 577 <&clk IMX93_CLK_BUS_WAKEUP>; 578 clock-names = "per", "ipg"; 579 status = "disabled"; 580 }; 581 582 lpspi7: spi@42710000 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 586 reg = <0x42710000 0x10000>; 587 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clk IMX93_CLK_LPSPI7_GATE>, 589 <&clk IMX93_CLK_BUS_WAKEUP>; 590 clock-names = "per", "ipg"; 591 status = "disabled"; 592 }; 593 594 lpspi8: spi@42720000 { 595 #address-cells = <1>; 596 #size-cells = <0>; 597 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 598 reg = <0x42720000 0x10000>; 599 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&clk IMX93_CLK_LPSPI8_GATE>, 601 <&clk IMX93_CLK_BUS_WAKEUP>; 602 clock-names = "per", "ipg"; 603 status = "disabled"; 604 }; 605 606 }; 607 608 aips3: bus@42800000 { 609 compatible = "fsl,aips-bus", "simple-bus"; 610 reg = <0x42800000 0x800000>; 611 #address-cells = <1>; 612 #size-cells = <1>; 613 ranges; 614 615 usdhc1: mmc@42850000 { 616 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 617 reg = <0x42850000 0x10000>; 618 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 620 <&clk IMX93_CLK_WAKEUP_AXI>, 621 <&clk IMX93_CLK_USDHC1_GATE>; 622 clock-names = "ipg", "ahb", "per"; 623 bus-width = <8>; 624 fsl,tuning-start-tap = <20>; 625 fsl,tuning-step= <2>; 626 status = "disabled"; 627 }; 628 629 usdhc2: mmc@42860000 { 630 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 631 reg = <0x42860000 0x10000>; 632 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 634 <&clk IMX93_CLK_WAKEUP_AXI>, 635 <&clk IMX93_CLK_USDHC2_GATE>; 636 clock-names = "ipg", "ahb", "per"; 637 bus-width = <4>; 638 fsl,tuning-start-tap = <20>; 639 fsl,tuning-step= <2>; 640 status = "disabled"; 641 }; 642 643 eqos: ethernet@428a0000 { 644 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; 645 reg = <0x428a0000 0x10000>; 646 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 648 interrupt-names = "macirq", "eth_wake_irq"; 649 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, 650 <&clk IMX93_CLK_ENET_QOS_GATE>, 651 <&clk IMX93_CLK_ENET_TIMER2>, 652 <&clk IMX93_CLK_ENET>, 653 <&clk IMX93_CLK_ENET_QOS_GATE>; 654 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; 655 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, 656 <&clk IMX93_CLK_ENET>; 657 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 658 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 659 assigned-clock-rates = <100000000>, <250000000>; 660 intf_mode = <&wakeupmix_gpr 0x28>; 661 snps,clk-csr = <0>; 662 status = "disabled"; 663 }; 664 665 fec: ethernet@42890000 { 666 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 667 reg = <0x42890000 0x10000>; 668 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&clk IMX93_CLK_ENET1_GATE>, 673 <&clk IMX93_CLK_ENET1_GATE>, 674 <&clk IMX93_CLK_ENET_TIMER1>, 675 <&clk IMX93_CLK_ENET_REF>, 676 <&clk IMX93_CLK_ENET_REF_PHY>; 677 clock-names = "ipg", "ahb", "ptp", 678 "enet_clk_ref", "enet_out"; 679 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 680 <&clk IMX93_CLK_ENET_REF>, 681 <&clk IMX93_CLK_ENET_REF_PHY>; 682 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 683 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, 684 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 685 assigned-clock-rates = <100000000>, <250000000>, <50000000>; 686 fsl,num-tx-queues = <3>; 687 fsl,num-rx-queues = <3>; 688 status = "disabled"; 689 }; 690 691 usdhc3: mmc@428b0000 { 692 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 693 reg = <0x428b0000 0x10000>; 694 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 696 <&clk IMX93_CLK_WAKEUP_AXI>, 697 <&clk IMX93_CLK_USDHC3_GATE>; 698 clock-names = "ipg", "ahb", "per"; 699 bus-width = <4>; 700 fsl,tuning-start-tap = <20>; 701 fsl,tuning-step= <2>; 702 status = "disabled"; 703 }; 704 }; 705 706 gpio2: gpio@43810080 { 707 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 708 reg = <0x43810080 0x1000>, <0x43810040 0x40>; 709 gpio-controller; 710 #gpio-cells = <2>; 711 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 715 <&clk IMX93_CLK_GPIO2_GATE>; 716 clock-names = "gpio", "port"; 717 gpio-ranges = <&iomuxc 0 4 30>; 718 }; 719 720 gpio3: gpio@43820080 { 721 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 722 reg = <0x43820080 0x1000>, <0x43820040 0x40>; 723 gpio-controller; 724 #gpio-cells = <2>; 725 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 729 <&clk IMX93_CLK_GPIO3_GATE>; 730 clock-names = "gpio", "port"; 731 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 732 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 733 }; 734 735 gpio4: gpio@43830080 { 736 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 737 reg = <0x43830080 0x1000>, <0x43830040 0x40>; 738 gpio-controller; 739 #gpio-cells = <2>; 740 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 744 <&clk IMX93_CLK_GPIO4_GATE>; 745 clock-names = "gpio", "port"; 746 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 747 }; 748 749 gpio1: gpio@47400080 { 750 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 751 reg = <0x47400080 0x1000>, <0x47400040 0x40>; 752 gpio-controller; 753 #gpio-cells = <2>; 754 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 755 interrupt-controller; 756 #interrupt-cells = <2>; 757 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 758 <&clk IMX93_CLK_GPIO1_GATE>; 759 clock-names = "gpio", "port"; 760 gpio-ranges = <&iomuxc 0 92 16>; 761 }; 762 763 s4muap: mailbox@47520000 { 764 compatible = "fsl,imx93-mu-s4"; 765 reg = <0x47520000 0x10000>; 766 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 768 interrupt-names = "tx", "rx"; 769 #mbox-cells = <2>; 770 }; 771 772 media_blk_ctrl: system-controller@4ac10000 { 773 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 774 reg = <0x4ac10000 0x10000>; 775 power-domains = <&mediamix>; 776 clocks = <&clk IMX93_CLK_MEDIA_APB>, 777 <&clk IMX93_CLK_MEDIA_AXI>, 778 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 779 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 780 <&clk IMX93_CLK_CAM_PIX>, 781 <&clk IMX93_CLK_PXP_GATE>, 782 <&clk IMX93_CLK_LCDIF_GATE>, 783 <&clk IMX93_CLK_ISI_GATE>, 784 <&clk IMX93_CLK_MIPI_CSI_GATE>, 785 <&clk IMX93_CLK_MIPI_DSI_GATE>; 786 clock-names = "apb", "axi", "nic", "disp", "cam", 787 "pxp", "lcdif", "isi", "csi", "dsi"; 788 #power-domain-cells = <1>; 789 status = "disabled"; 790 }; 791 }; 792}; 793