1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/fsl,imx93-power.h> 11 12#include "imx93-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &lpi2c1; 21 i2c1 = &lpi2c2; 22 i2c2 = &lpi2c3; 23 i2c3 = &lpi2c4; 24 i2c4 = &lpi2c5; 25 i2c5 = &lpi2c6; 26 i2c6 = &lpi2c7; 27 i2c7 = &lpi2c8; 28 mmc0 = &usdhc1; 29 mmc1 = &usdhc2; 30 mmc2 = &usdhc3; 31 serial0 = &lpuart1; 32 serial1 = &lpuart2; 33 serial2 = &lpuart3; 34 serial3 = &lpuart4; 35 serial4 = &lpuart5; 36 serial5 = &lpuart6; 37 serial6 = &lpuart7; 38 serial7 = &lpuart8; 39 }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 A55_0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a55"; 48 reg = <0x0>; 49 enable-method = "psci"; 50 #cooling-cells = <2>; 51 }; 52 53 A55_1: cpu@100 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x100>; 57 enable-method = "psci"; 58 #cooling-cells = <2>; 59 }; 60 61 }; 62 63 osc_32k: clock-osc-32k { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <32768>; 67 clock-output-names = "osc_32k"; 68 }; 69 70 osc_24m: clock-osc-24m { 71 compatible = "fixed-clock"; 72 #clock-cells = <0>; 73 clock-frequency = <24000000>; 74 clock-output-names = "osc_24m"; 75 }; 76 77 clk_ext1: clock-ext1 { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <133000000>; 81 clock-output-names = "clk_ext1"; 82 }; 83 84 pmu { 85 compatible = "arm,cortex-a55-pmu"; 86 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 87 }; 88 89 psci { 90 compatible = "arm,psci-1.0"; 91 method = "smc"; 92 }; 93 94 timer { 95 compatible = "arm,armv8-timer"; 96 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 97 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 100 clock-frequency = <24000000>; 101 arm,no-tick-in-suspend; 102 interrupt-parent = <&gic>; 103 }; 104 105 gic: interrupt-controller@48000000 { 106 compatible = "arm,gic-v3"; 107 reg = <0 0x48000000 0 0x10000>, 108 <0 0x48040000 0 0xc0000>; 109 #interrupt-cells = <3>; 110 interrupt-controller; 111 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 112 interrupt-parent = <&gic>; 113 }; 114 115 soc@0 { 116 compatible = "simple-bus"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges = <0x0 0x0 0x0 0x80000000>, 120 <0x28000000 0x0 0x28000000 0x10000000>; 121 122 aips1: bus@44000000 { 123 compatible = "fsl,aips-bus", "simple-bus"; 124 reg = <0x44000000 0x800000>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges; 128 129 anomix_ns_gpr: syscon@44210000 { 130 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 131 reg = <0x44210000 0x1000>; 132 }; 133 134 mu1: mailbox@44230000 { 135 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 136 reg = <0x44230000 0x10000>; 137 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 138 #mbox-cells = <2>; 139 status = "disabled"; 140 }; 141 142 system_counter: timer@44290000 { 143 compatible = "nxp,sysctr-timer"; 144 reg = <0x44290000 0x30000>; 145 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&osc_24m>; 147 clock-names = "per"; 148 }; 149 150 lpi2c1: i2c@44340000 { 151 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 152 reg = <0x44340000 0x10000>; 153 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 155 <&clk IMX93_CLK_BUS_AON>; 156 clock-names = "per", "ipg"; 157 status = "disabled"; 158 }; 159 160 lpi2c2: i2c@44350000 { 161 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 162 reg = <0x44350000 0x10000>; 163 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 165 <&clk IMX93_CLK_BUS_AON>; 166 clock-names = "per", "ipg"; 167 status = "disabled"; 168 }; 169 170 lpspi1: spi@44360000 { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 174 reg = <0x44360000 0x10000>; 175 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 177 <&clk IMX93_CLK_BUS_AON>; 178 clock-names = "per", "ipg"; 179 status = "disabled"; 180 }; 181 182 lpspi2: spi@44370000 { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 186 reg = <0x44370000 0x10000>; 187 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 189 <&clk IMX93_CLK_BUS_AON>; 190 clock-names = "per", "ipg"; 191 status = "disabled"; 192 }; 193 194 lpuart1: serial@44380000 { 195 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 196 reg = <0x44380000 0x1000>; 197 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 199 clock-names = "ipg"; 200 status = "disabled"; 201 }; 202 203 lpuart2: serial@44390000 { 204 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 205 reg = <0x44390000 0x1000>; 206 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 208 clock-names = "ipg"; 209 status = "disabled"; 210 }; 211 212 iomuxc: pinctrl@443c0000 { 213 compatible = "fsl,imx93-iomuxc"; 214 reg = <0x443c0000 0x10000>; 215 status = "okay"; 216 }; 217 218 clk: clock-controller@44450000 { 219 compatible = "fsl,imx93-ccm"; 220 reg = <0x44450000 0x10000>; 221 #clock-cells = <1>; 222 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 223 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 224 status = "okay"; 225 }; 226 227 src: system-controller@44460000 { 228 compatible = "fsl,imx93-src", "syscon"; 229 reg = <0x44460000 0x10000>; 230 #address-cells = <1>; 231 #size-cells = <1>; 232 ranges; 233 234 mediamix: power-domain@44462400 { 235 compatible = "fsl,imx93-src-slice"; 236 reg = <0x44462400 0x400>, <0x44465800 0x400>; 237 #power-domain-cells = <0>; 238 clocks = <&clk IMX93_CLK_MEDIA_AXI>, 239 <&clk IMX93_CLK_MEDIA_APB>; 240 }; 241 242 mlmix: power-domain@44461800 { 243 compatible = "fsl,imx93-src-slice"; 244 reg = <0x44461800 0x400>, <0x44464800 0x400>; 245 #power-domain-cells = <0>; 246 clocks = <&clk IMX93_CLK_ML_APB>, 247 <&clk IMX93_CLK_ML>; 248 }; 249 }; 250 251 anatop: anatop@44480000 { 252 compatible = "fsl,imx93-anatop", "syscon"; 253 reg = <0x44480000 0x10000>; 254 }; 255 }; 256 257 aips2: bus@42000000 { 258 compatible = "fsl,aips-bus", "simple-bus"; 259 reg = <0x42000000 0x800000>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges; 263 264 wakeupmix_gpr: syscon@42420000 { 265 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 266 reg = <0x42420000 0x1000>; 267 }; 268 269 mu2: mailbox@42440000 { 270 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 271 reg = <0x42440000 0x10000>; 272 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 273 #mbox-cells = <2>; 274 status = "disabled"; 275 }; 276 277 lpi2c3: i2c@42530000 { 278 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 279 reg = <0x42530000 0x10000>; 280 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 282 <&clk IMX93_CLK_BUS_WAKEUP>; 283 clock-names = "per", "ipg"; 284 status = "disabled"; 285 }; 286 287 lpi2c4: i2c@42540000 { 288 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 289 reg = <0x42540000 0x10000>; 290 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 292 <&clk IMX93_CLK_BUS_WAKEUP>; 293 clock-names = "per", "ipg"; 294 status = "disabled"; 295 }; 296 297 lpuart3: serial@42570000 { 298 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 299 reg = <0x42570000 0x1000>; 300 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 302 clock-names = "ipg"; 303 status = "disabled"; 304 }; 305 306 lpuart4: serial@42580000 { 307 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 308 reg = <0x42580000 0x1000>; 309 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 311 clock-names = "ipg"; 312 status = "disabled"; 313 }; 314 315 lpuart5: serial@42590000 { 316 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 317 reg = <0x42590000 0x1000>; 318 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 320 clock-names = "ipg"; 321 status = "disabled"; 322 }; 323 324 lpuart6: serial@425a0000 { 325 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 326 reg = <0x425a0000 0x1000>; 327 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 329 clock-names = "ipg"; 330 status = "disabled"; 331 }; 332 333 lpuart7: serial@42690000 { 334 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 335 reg = <0x42690000 0x1000>; 336 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 338 clock-names = "ipg"; 339 status = "disabled"; 340 }; 341 342 lpuart8: serial@426a0000 { 343 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 344 reg = <0x426a0000 0x1000>; 345 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 347 clock-names = "ipg"; 348 status = "disabled"; 349 }; 350 351 lpi2c5: i2c@426b0000 { 352 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 353 reg = <0x426b0000 0x10000>; 354 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 356 <&clk IMX93_CLK_BUS_WAKEUP>; 357 clock-names = "per", "ipg"; 358 status = "disabled"; 359 }; 360 361 lpi2c6: i2c@426c0000 { 362 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 363 reg = <0x426c0000 0x10000>; 364 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 366 <&clk IMX93_CLK_BUS_WAKEUP>; 367 clock-names = "per", "ipg"; 368 status = "disabled"; 369 }; 370 371 lpi2c7: i2c@426d0000 { 372 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 373 reg = <0x426d0000 0x10000>; 374 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 376 <&clk IMX93_CLK_BUS_WAKEUP>; 377 clock-names = "per", "ipg"; 378 status = "disabled"; 379 }; 380 381 lpi2c8: i2c@426e0000 { 382 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 383 reg = <0x426e0000 0x10000>; 384 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 386 <&clk IMX93_CLK_BUS_WAKEUP>; 387 clock-names = "per", "ipg"; 388 status = "disabled"; 389 }; 390 391 }; 392 393 aips3: bus@42800000 { 394 compatible = "fsl,aips-bus", "simple-bus"; 395 reg = <0x42800000 0x800000>; 396 #address-cells = <1>; 397 #size-cells = <1>; 398 ranges; 399 400 usdhc1: mmc@42850000 { 401 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 402 reg = <0x42850000 0x10000>; 403 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 405 <&clk IMX93_CLK_WAKEUP_AXI>, 406 <&clk IMX93_CLK_USDHC1_GATE>; 407 clock-names = "ipg", "ahb", "per"; 408 bus-width = <8>; 409 fsl,tuning-start-tap = <20>; 410 fsl,tuning-step= <2>; 411 status = "disabled"; 412 }; 413 414 usdhc2: mmc@42860000 { 415 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 416 reg = <0x42860000 0x10000>; 417 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 419 <&clk IMX93_CLK_WAKEUP_AXI>, 420 <&clk IMX93_CLK_USDHC2_GATE>; 421 clock-names = "ipg", "ahb", "per"; 422 bus-width = <4>; 423 fsl,tuning-start-tap = <20>; 424 fsl,tuning-step= <2>; 425 status = "disabled"; 426 }; 427 428 usdhc3: mmc@428b0000 { 429 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 430 reg = <0x428b0000 0x10000>; 431 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 433 <&clk IMX93_CLK_WAKEUP_AXI>, 434 <&clk IMX93_CLK_USDHC3_GATE>; 435 clock-names = "ipg", "ahb", "per"; 436 bus-width = <4>; 437 fsl,tuning-start-tap = <20>; 438 fsl,tuning-step= <2>; 439 status = "disabled"; 440 }; 441 }; 442 443 gpio2: gpio@43810080 { 444 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 445 reg = <0x43810080 0x1000>, <0x43810040 0x40>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 449 interrupt-controller; 450 #interrupt-cells = <2>; 451 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 452 <&clk IMX93_CLK_GPIO2_GATE>; 453 clock-names = "gpio", "port"; 454 gpio-ranges = <&iomuxc 0 4 30>; 455 }; 456 457 gpio3: gpio@43820080 { 458 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 459 reg = <0x43820080 0x1000>, <0x43820040 0x40>; 460 gpio-controller; 461 #gpio-cells = <2>; 462 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 466 <&clk IMX93_CLK_GPIO3_GATE>; 467 clock-names = "gpio", "port"; 468 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 469 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 470 }; 471 472 gpio4: gpio@43830080 { 473 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 474 reg = <0x43830080 0x1000>, <0x43830040 0x40>; 475 gpio-controller; 476 #gpio-cells = <2>; 477 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 481 <&clk IMX93_CLK_GPIO4_GATE>; 482 clock-names = "gpio", "port"; 483 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 484 }; 485 486 gpio1: gpio@47400080 { 487 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 488 reg = <0x47400080 0x1000>, <0x47400040 0x40>; 489 gpio-controller; 490 #gpio-cells = <2>; 491 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-controller; 493 #interrupt-cells = <2>; 494 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 495 <&clk IMX93_CLK_GPIO1_GATE>; 496 clock-names = "gpio", "port"; 497 gpio-ranges = <&iomuxc 0 92 16>; 498 }; 499 500 s4muap: mailbox@47520000 { 501 compatible = "fsl,imx93-mu-s4"; 502 reg = <0x47520000 0x10000>; 503 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "tx", "rx"; 506 #mbox-cells = <2>; 507 }; 508 509 media_blk_ctrl: system-controller@4ac10000 { 510 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 511 reg = <0x4ac10000 0x10000>; 512 power-domains = <&mediamix>; 513 clocks = <&clk IMX93_CLK_MEDIA_APB>, 514 <&clk IMX93_CLK_MEDIA_AXI>, 515 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 516 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 517 <&clk IMX93_CLK_CAM_PIX>, 518 <&clk IMX93_CLK_PXP_GATE>, 519 <&clk IMX93_CLK_LCDIF_GATE>, 520 <&clk IMX93_CLK_ISI_GATE>, 521 <&clk IMX93_CLK_MIPI_CSI_GATE>, 522 <&clk IMX93_CLK_MIPI_DSI_GATE>; 523 clock-names = "apb", "axi", "nic", "disp", "cam", 524 "pxp", "lcdif", "isi", "csi", "dsi"; 525 #power-domain-cells = <1>; 526 status = "disabled"; 527 }; 528 }; 529}; 530