1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/fsl,imx93-power.h> 11#include <dt-bindings/thermal/thermal.h> 12 13#include "imx93-pinfunc.h" 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 i2c0 = &lpi2c1; 26 i2c1 = &lpi2c2; 27 i2c2 = &lpi2c3; 28 i2c3 = &lpi2c4; 29 i2c4 = &lpi2c5; 30 i2c5 = &lpi2c6; 31 i2c6 = &lpi2c7; 32 i2c7 = &lpi2c8; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 mmc2 = &usdhc3; 36 serial0 = &lpuart1; 37 serial1 = &lpuart2; 38 serial2 = &lpuart3; 39 serial3 = &lpuart4; 40 serial4 = &lpuart5; 41 serial5 = &lpuart6; 42 serial6 = &lpuart7; 43 serial7 = &lpuart8; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 idle-states { 51 entry-method = "psci"; 52 53 cpu_pd_wait: cpu-pd-wait { 54 compatible = "arm,idle-state"; 55 arm,psci-suspend-param = <0x0010033>; 56 local-timer-stop; 57 entry-latency-us = <10000>; 58 exit-latency-us = <7000>; 59 min-residency-us = <27000>; 60 wakeup-latency-us = <15000>; 61 }; 62 }; 63 64 A55_0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x0>; 68 enable-method = "psci"; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&cpu_pd_wait>; 71 }; 72 73 A55_1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a55"; 76 reg = <0x100>; 77 enable-method = "psci"; 78 #cooling-cells = <2>; 79 cpu-idle-states = <&cpu_pd_wait>; 80 }; 81 82 }; 83 84 osc_32k: clock-osc-32k { 85 compatible = "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <32768>; 88 clock-output-names = "osc_32k"; 89 }; 90 91 osc_24m: clock-osc-24m { 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <24000000>; 95 clock-output-names = "osc_24m"; 96 }; 97 98 clk_ext1: clock-ext1 { 99 compatible = "fixed-clock"; 100 #clock-cells = <0>; 101 clock-frequency = <133000000>; 102 clock-output-names = "clk_ext1"; 103 }; 104 105 pmu { 106 compatible = "arm,cortex-a55-pmu"; 107 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 108 }; 109 110 psci { 111 compatible = "arm,psci-1.0"; 112 method = "smc"; 113 }; 114 115 timer { 116 compatible = "arm,armv8-timer"; 117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 118 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 121 clock-frequency = <24000000>; 122 arm,no-tick-in-suspend; 123 interrupt-parent = <&gic>; 124 }; 125 126 gic: interrupt-controller@48000000 { 127 compatible = "arm,gic-v3"; 128 reg = <0 0x48000000 0 0x10000>, 129 <0 0x48040000 0 0xc0000>; 130 #interrupt-cells = <3>; 131 interrupt-controller; 132 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 133 interrupt-parent = <&gic>; 134 }; 135 136 thermal-zones { 137 cpu-thermal { 138 polling-delay-passive = <250>; 139 polling-delay = <2000>; 140 141 thermal-sensors = <&tmu 0>; 142 143 trips { 144 cpu_alert: cpu-alert { 145 temperature = <80000>; 146 hysteresis = <2000>; 147 type = "passive"; 148 }; 149 150 cpu_crit: cpu-crit { 151 temperature = <90000>; 152 hysteresis = <2000>; 153 type = "critical"; 154 }; 155 }; 156 157 cooling-maps { 158 map0 { 159 trip = <&cpu_alert>; 160 cooling-device = 161 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 162 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 163 }; 164 }; 165 }; 166 }; 167 168 cm33: remoteproc-cm33 { 169 compatible = "fsl,imx93-cm33"; 170 clocks = <&clk IMX93_CLK_CM33_GATE>; 171 status = "disabled"; 172 }; 173 174 soc@0 { 175 compatible = "simple-bus"; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 ranges = <0x0 0x0 0x0 0x80000000>, 179 <0x28000000 0x0 0x28000000 0x10000000>; 180 181 aips1: bus@44000000 { 182 compatible = "fsl,aips-bus", "simple-bus"; 183 reg = <0x44000000 0x800000>; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 ranges; 187 188 aonmix_ns_gpr: syscon@44210000 { 189 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 190 reg = <0x44210000 0x1000>; 191 }; 192 193 mu1: mailbox@44230000 { 194 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 195 reg = <0x44230000 0x10000>; 196 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clk IMX93_CLK_MU1_B_GATE>; 198 #mbox-cells = <2>; 199 status = "disabled"; 200 }; 201 202 system_counter: timer@44290000 { 203 compatible = "nxp,sysctr-timer"; 204 reg = <0x44290000 0x30000>; 205 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&osc_24m>; 207 clock-names = "per"; 208 nxp,no-divider; 209 }; 210 211 wdog1: watchdog@442d0000 { 212 compatible = "fsl,imx93-wdt"; 213 reg = <0x442d0000 0x10000>; 214 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&clk IMX93_CLK_WDOG1_GATE>; 216 timeout-sec = <40>; 217 status = "disabled"; 218 }; 219 220 wdog2: watchdog@442e0000 { 221 compatible = "fsl,imx93-wdt"; 222 reg = <0x442e0000 0x10000>; 223 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&clk IMX93_CLK_WDOG2_GATE>; 225 timeout-sec = <40>; 226 status = "disabled"; 227 }; 228 229 tpm1: pwm@44310000 { 230 compatible = "fsl,imx7ulp-pwm"; 231 reg = <0x44310000 0x1000>; 232 clocks = <&clk IMX93_CLK_TPM1_GATE>; 233 #pwm-cells = <3>; 234 status = "disabled"; 235 }; 236 237 tpm2: pwm@44320000 { 238 compatible = "fsl,imx7ulp-pwm"; 239 reg = <0x44320000 0x10000>; 240 clocks = <&clk IMX93_CLK_TPM2_GATE>; 241 #pwm-cells = <3>; 242 status = "disabled"; 243 }; 244 245 lpi2c1: i2c@44340000 { 246 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 247 reg = <0x44340000 0x10000>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 252 <&clk IMX93_CLK_BUS_AON>; 253 clock-names = "per", "ipg"; 254 status = "disabled"; 255 }; 256 257 lpi2c2: i2c@44350000 { 258 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 259 reg = <0x44350000 0x10000>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 264 <&clk IMX93_CLK_BUS_AON>; 265 clock-names = "per", "ipg"; 266 status = "disabled"; 267 }; 268 269 lpspi1: spi@44360000 { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 273 reg = <0x44360000 0x10000>; 274 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 276 <&clk IMX93_CLK_BUS_AON>; 277 clock-names = "per", "ipg"; 278 status = "disabled"; 279 }; 280 281 lpspi2: spi@44370000 { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 285 reg = <0x44370000 0x10000>; 286 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 288 <&clk IMX93_CLK_BUS_AON>; 289 clock-names = "per", "ipg"; 290 status = "disabled"; 291 }; 292 293 lpuart1: serial@44380000 { 294 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 295 reg = <0x44380000 0x1000>; 296 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 298 clock-names = "ipg"; 299 status = "disabled"; 300 }; 301 302 lpuart2: serial@44390000 { 303 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 304 reg = <0x44390000 0x1000>; 305 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 307 clock-names = "ipg"; 308 status = "disabled"; 309 }; 310 311 flexcan1: can@443a0000 { 312 compatible = "fsl,imx93-flexcan"; 313 reg = <0x443a0000 0x10000>; 314 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clk IMX93_CLK_BUS_AON>, 316 <&clk IMX93_CLK_CAN1_GATE>; 317 clock-names = "ipg", "per"; 318 assigned-clocks = <&clk IMX93_CLK_CAN1>; 319 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 320 assigned-clock-rates = <40000000>; 321 fsl,clk-source = /bits/ 8 <0>; 322 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; 323 status = "disabled"; 324 }; 325 326 iomuxc: pinctrl@443c0000 { 327 compatible = "fsl,imx93-iomuxc"; 328 reg = <0x443c0000 0x10000>; 329 status = "okay"; 330 }; 331 332 bbnsm: bbnsm@44440000 { 333 compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; 334 reg = <0x44440000 0x10000>; 335 336 bbnsm_rtc: rtc { 337 compatible = "nxp,imx93-bbnsm-rtc"; 338 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 339 }; 340 341 bbnsm_pwrkey: pwrkey { 342 compatible = "nxp,imx93-bbnsm-pwrkey"; 343 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 344 linux,code = <KEY_POWER>; 345 }; 346 }; 347 348 clk: clock-controller@44450000 { 349 compatible = "fsl,imx93-ccm"; 350 reg = <0x44450000 0x10000>; 351 #clock-cells = <1>; 352 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 353 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 354 status = "okay"; 355 }; 356 357 src: system-controller@44460000 { 358 compatible = "fsl,imx93-src", "syscon"; 359 reg = <0x44460000 0x10000>; 360 #address-cells = <1>; 361 #size-cells = <1>; 362 ranges; 363 364 mlmix: power-domain@44461800 { 365 compatible = "fsl,imx93-src-slice"; 366 reg = <0x44461800 0x400>, <0x44464800 0x400>; 367 #power-domain-cells = <0>; 368 clocks = <&clk IMX93_CLK_ML_APB>, 369 <&clk IMX93_CLK_ML>; 370 }; 371 372 mediamix: power-domain@44462400 { 373 compatible = "fsl,imx93-src-slice"; 374 reg = <0x44462400 0x400>, <0x44465800 0x400>; 375 #power-domain-cells = <0>; 376 clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, 377 <&clk IMX93_CLK_MEDIA_APB>; 378 }; 379 }; 380 381 anatop: anatop@44480000 { 382 compatible = "fsl,imx93-anatop", "syscon"; 383 reg = <0x44480000 0x2000>; 384 }; 385 386 tmu: tmu@44482000 { 387 compatible = "fsl,qoriq-tmu"; 388 reg = <0x44482000 0x1000>; 389 clocks = <&clk IMX93_CLK_TMC_GATE>; 390 little-endian; 391 fsl,tmu-range = <0x800000da 0x800000e9 392 0x80000102 0x8000012a 393 0x80000166 0x800001a7 394 0x800001b6>; 395 fsl,tmu-calibration = <0x00000000 0x0000000e 396 0x00000001 0x00000029 397 0x00000002 0x00000056 398 0x00000003 0x000000a2 399 0x00000004 0x00000116 400 0x00000005 0x00000195 401 0x00000006 0x000001b2>; 402 #thermal-sensor-cells = <1>; 403 }; 404 405 406 adc1: adc@44530000 { 407 compatible = "nxp,imx93-adc"; 408 reg = <0x44530000 0x10000>; 409 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&clk IMX93_CLK_ADC1_GATE>; 414 clock-names = "ipg"; 415 #io-channel-cells = <1>; 416 status = "disabled"; 417 }; 418 }; 419 420 aips2: bus@42000000 { 421 compatible = "fsl,aips-bus", "simple-bus"; 422 reg = <0x42000000 0x800000>; 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges; 426 427 wakeupmix_gpr: syscon@42420000 { 428 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 429 reg = <0x42420000 0x1000>; 430 }; 431 432 mu2: mailbox@42440000 { 433 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 434 reg = <0x42440000 0x10000>; 435 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&clk IMX93_CLK_MU2_B_GATE>; 437 #mbox-cells = <2>; 438 status = "disabled"; 439 }; 440 441 wdog3: watchdog@42490000 { 442 compatible = "fsl,imx93-wdt"; 443 reg = <0x42490000 0x10000>; 444 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&clk IMX93_CLK_WDOG3_GATE>; 446 timeout-sec = <40>; 447 status = "disabled"; 448 }; 449 450 wdog4: watchdog@424a0000 { 451 compatible = "fsl,imx93-wdt"; 452 reg = <0x424a0000 0x10000>; 453 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&clk IMX93_CLK_WDOG4_GATE>; 455 timeout-sec = <40>; 456 status = "disabled"; 457 }; 458 459 wdog5: watchdog@424b0000 { 460 compatible = "fsl,imx93-wdt"; 461 reg = <0x424b0000 0x10000>; 462 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&clk IMX93_CLK_WDOG5_GATE>; 464 timeout-sec = <40>; 465 status = "disabled"; 466 }; 467 468 tpm3: pwm@424e0000 { 469 compatible = "fsl,imx7ulp-pwm"; 470 reg = <0x424e0000 0x1000>; 471 clocks = <&clk IMX93_CLK_TPM3_GATE>; 472 #pwm-cells = <3>; 473 status = "disabled"; 474 }; 475 476 tpm4: pwm@424f0000 { 477 compatible = "fsl,imx7ulp-pwm"; 478 reg = <0x424f0000 0x10000>; 479 clocks = <&clk IMX93_CLK_TPM4_GATE>; 480 #pwm-cells = <3>; 481 status = "disabled"; 482 }; 483 484 tpm5: pwm@42500000 { 485 compatible = "fsl,imx7ulp-pwm"; 486 reg = <0x42500000 0x10000>; 487 clocks = <&clk IMX93_CLK_TPM5_GATE>; 488 #pwm-cells = <3>; 489 status = "disabled"; 490 }; 491 492 tpm6: pwm@42510000 { 493 compatible = "fsl,imx7ulp-pwm"; 494 reg = <0x42510000 0x10000>; 495 clocks = <&clk IMX93_CLK_TPM6_GATE>; 496 #pwm-cells = <3>; 497 status = "disabled"; 498 }; 499 500 lpi2c3: i2c@42530000 { 501 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 502 reg = <0x42530000 0x10000>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 507 <&clk IMX93_CLK_BUS_WAKEUP>; 508 clock-names = "per", "ipg"; 509 status = "disabled"; 510 }; 511 512 lpi2c4: i2c@42540000 { 513 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 514 reg = <0x42540000 0x10000>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 519 <&clk IMX93_CLK_BUS_WAKEUP>; 520 clock-names = "per", "ipg"; 521 status = "disabled"; 522 }; 523 524 lpspi3: spi@42550000 { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 528 reg = <0x42550000 0x10000>; 529 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clk IMX93_CLK_LPSPI3_GATE>, 531 <&clk IMX93_CLK_BUS_WAKEUP>; 532 clock-names = "per", "ipg"; 533 status = "disabled"; 534 }; 535 536 lpspi4: spi@42560000 { 537 #address-cells = <1>; 538 #size-cells = <0>; 539 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 540 reg = <0x42560000 0x10000>; 541 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clk IMX93_CLK_LPSPI4_GATE>, 543 <&clk IMX93_CLK_BUS_WAKEUP>; 544 clock-names = "per", "ipg"; 545 status = "disabled"; 546 }; 547 548 lpuart3: serial@42570000 { 549 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 550 reg = <0x42570000 0x1000>; 551 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 553 clock-names = "ipg"; 554 status = "disabled"; 555 }; 556 557 lpuart4: serial@42580000 { 558 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 559 reg = <0x42580000 0x1000>; 560 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 562 clock-names = "ipg"; 563 status = "disabled"; 564 }; 565 566 lpuart5: serial@42590000 { 567 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 568 reg = <0x42590000 0x1000>; 569 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 571 clock-names = "ipg"; 572 status = "disabled"; 573 }; 574 575 lpuart6: serial@425a0000 { 576 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 577 reg = <0x425a0000 0x1000>; 578 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 580 clock-names = "ipg"; 581 status = "disabled"; 582 }; 583 584 flexcan2: can@425b0000 { 585 compatible = "fsl,imx93-flexcan"; 586 reg = <0x425b0000 0x10000>; 587 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 589 <&clk IMX93_CLK_CAN2_GATE>; 590 clock-names = "ipg", "per"; 591 assigned-clocks = <&clk IMX93_CLK_CAN2>; 592 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 593 assigned-clock-rates = <40000000>; 594 fsl,clk-source = /bits/ 8 <0>; 595 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; 596 status = "disabled"; 597 }; 598 599 flexspi1: spi@425e0000 { 600 compatible = "nxp,imx8mm-fspi"; 601 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; 602 reg-names = "fspi_base", "fspi_mmap"; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, 607 <&clk IMX93_CLK_FLEXSPI1_GATE>; 608 clock-names = "fspi_en", "fspi"; 609 assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; 610 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 611 status = "disabled"; 612 }; 613 614 lpuart7: serial@42690000 { 615 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 616 reg = <0x42690000 0x1000>; 617 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 619 clock-names = "ipg"; 620 status = "disabled"; 621 }; 622 623 lpuart8: serial@426a0000 { 624 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 625 reg = <0x426a0000 0x1000>; 626 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 628 clock-names = "ipg"; 629 status = "disabled"; 630 }; 631 632 lpi2c5: i2c@426b0000 { 633 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 634 reg = <0x426b0000 0x10000>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 639 <&clk IMX93_CLK_BUS_WAKEUP>; 640 clock-names = "per", "ipg"; 641 status = "disabled"; 642 }; 643 644 lpi2c6: i2c@426c0000 { 645 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 646 reg = <0x426c0000 0x10000>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 651 <&clk IMX93_CLK_BUS_WAKEUP>; 652 clock-names = "per", "ipg"; 653 status = "disabled"; 654 }; 655 656 lpi2c7: i2c@426d0000 { 657 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 658 reg = <0x426d0000 0x10000>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 663 <&clk IMX93_CLK_BUS_WAKEUP>; 664 clock-names = "per", "ipg"; 665 status = "disabled"; 666 }; 667 668 lpi2c8: i2c@426e0000 { 669 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 670 reg = <0x426e0000 0x10000>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 675 <&clk IMX93_CLK_BUS_WAKEUP>; 676 clock-names = "per", "ipg"; 677 status = "disabled"; 678 }; 679 680 lpspi5: spi@426f0000 { 681 #address-cells = <1>; 682 #size-cells = <0>; 683 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 684 reg = <0x426f0000 0x10000>; 685 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&clk IMX93_CLK_LPSPI5_GATE>, 687 <&clk IMX93_CLK_BUS_WAKEUP>; 688 clock-names = "per", "ipg"; 689 status = "disabled"; 690 }; 691 692 lpspi6: spi@42700000 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 696 reg = <0x42700000 0x10000>; 697 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&clk IMX93_CLK_LPSPI6_GATE>, 699 <&clk IMX93_CLK_BUS_WAKEUP>; 700 clock-names = "per", "ipg"; 701 status = "disabled"; 702 }; 703 704 lpspi7: spi@42710000 { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 708 reg = <0x42710000 0x10000>; 709 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&clk IMX93_CLK_LPSPI7_GATE>, 711 <&clk IMX93_CLK_BUS_WAKEUP>; 712 clock-names = "per", "ipg"; 713 status = "disabled"; 714 }; 715 716 lpspi8: spi@42720000 { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 720 reg = <0x42720000 0x10000>; 721 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&clk IMX93_CLK_LPSPI8_GATE>, 723 <&clk IMX93_CLK_BUS_WAKEUP>; 724 clock-names = "per", "ipg"; 725 status = "disabled"; 726 }; 727 728 }; 729 730 aips3: bus@42800000 { 731 compatible = "fsl,aips-bus", "simple-bus"; 732 reg = <0x42800000 0x800000>; 733 #address-cells = <1>; 734 #size-cells = <1>; 735 ranges; 736 737 usdhc1: mmc@42850000 { 738 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 739 reg = <0x42850000 0x10000>; 740 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 742 <&clk IMX93_CLK_WAKEUP_AXI>, 743 <&clk IMX93_CLK_USDHC1_GATE>; 744 clock-names = "ipg", "ahb", "per"; 745 bus-width = <8>; 746 fsl,tuning-start-tap = <20>; 747 fsl,tuning-step = <2>; 748 status = "disabled"; 749 }; 750 751 usdhc2: mmc@42860000 { 752 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 753 reg = <0x42860000 0x10000>; 754 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 756 <&clk IMX93_CLK_WAKEUP_AXI>, 757 <&clk IMX93_CLK_USDHC2_GATE>; 758 clock-names = "ipg", "ahb", "per"; 759 bus-width = <4>; 760 fsl,tuning-start-tap = <20>; 761 fsl,tuning-step = <2>; 762 status = "disabled"; 763 }; 764 765 fec: ethernet@42890000 { 766 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 767 reg = <0x42890000 0x10000>; 768 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&clk IMX93_CLK_ENET1_GATE>, 773 <&clk IMX93_CLK_ENET1_GATE>, 774 <&clk IMX93_CLK_ENET_TIMER1>, 775 <&clk IMX93_CLK_ENET_REF>, 776 <&clk IMX93_CLK_ENET_REF_PHY>; 777 clock-names = "ipg", "ahb", "ptp", 778 "enet_clk_ref", "enet_out"; 779 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 780 <&clk IMX93_CLK_ENET_REF>, 781 <&clk IMX93_CLK_ENET_REF_PHY>; 782 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 783 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, 784 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 785 assigned-clock-rates = <100000000>, <250000000>, <50000000>; 786 fsl,num-tx-queues = <3>; 787 fsl,num-rx-queues = <3>; 788 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; 789 status = "disabled"; 790 }; 791 792 eqos: ethernet@428a0000 { 793 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; 794 reg = <0x428a0000 0x10000>; 795 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 797 interrupt-names = "macirq", "eth_wake_irq"; 798 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, 799 <&clk IMX93_CLK_ENET_QOS_GATE>, 800 <&clk IMX93_CLK_ENET_TIMER2>, 801 <&clk IMX93_CLK_ENET>, 802 <&clk IMX93_CLK_ENET_QOS_GATE>; 803 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; 804 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, 805 <&clk IMX93_CLK_ENET>; 806 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 807 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 808 assigned-clock-rates = <100000000>, <250000000>; 809 intf_mode = <&wakeupmix_gpr 0x28>; 810 snps,clk-csr = <0>; 811 status = "disabled"; 812 }; 813 814 usdhc3: mmc@428b0000 { 815 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 816 reg = <0x428b0000 0x10000>; 817 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 819 <&clk IMX93_CLK_WAKEUP_AXI>, 820 <&clk IMX93_CLK_USDHC3_GATE>; 821 clock-names = "ipg", "ahb", "per"; 822 bus-width = <4>; 823 fsl,tuning-start-tap = <20>; 824 fsl,tuning-step = <2>; 825 status = "disabled"; 826 }; 827 }; 828 829 gpio2: gpio@43810080 { 830 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 831 reg = <0x43810080 0x1000>, <0x43810040 0x40>; 832 gpio-controller; 833 #gpio-cells = <2>; 834 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 835 interrupt-controller; 836 #interrupt-cells = <2>; 837 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 838 <&clk IMX93_CLK_GPIO2_GATE>; 839 clock-names = "gpio", "port"; 840 gpio-ranges = <&iomuxc 0 4 30>; 841 }; 842 843 gpio3: gpio@43820080 { 844 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 845 reg = <0x43820080 0x1000>, <0x43820040 0x40>; 846 gpio-controller; 847 #gpio-cells = <2>; 848 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-controller; 850 #interrupt-cells = <2>; 851 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 852 <&clk IMX93_CLK_GPIO3_GATE>; 853 clock-names = "gpio", "port"; 854 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 855 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 856 }; 857 858 gpio4: gpio@43830080 { 859 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 860 reg = <0x43830080 0x1000>, <0x43830040 0x40>; 861 gpio-controller; 862 #gpio-cells = <2>; 863 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 864 interrupt-controller; 865 #interrupt-cells = <2>; 866 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 867 <&clk IMX93_CLK_GPIO4_GATE>; 868 clock-names = "gpio", "port"; 869 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 870 }; 871 872 gpio1: gpio@47400080 { 873 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 874 reg = <0x47400080 0x1000>, <0x47400040 0x40>; 875 gpio-controller; 876 #gpio-cells = <2>; 877 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 878 interrupt-controller; 879 #interrupt-cells = <2>; 880 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 881 <&clk IMX93_CLK_GPIO1_GATE>; 882 clock-names = "gpio", "port"; 883 gpio-ranges = <&iomuxc 0 92 16>; 884 }; 885 886 ocotp: efuse@47510000 { 887 compatible = "fsl,imx93-ocotp", "syscon"; 888 reg = <0x47510000 0x10000>; 889 #address-cells = <1>; 890 #size-cells = <1>; 891 }; 892 893 s4muap: mailbox@47520000 { 894 compatible = "fsl,imx93-mu-s4"; 895 reg = <0x47520000 0x10000>; 896 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 898 interrupt-names = "tx", "rx"; 899 #mbox-cells = <2>; 900 }; 901 902 media_blk_ctrl: system-controller@4ac10000 { 903 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 904 reg = <0x4ac10000 0x10000>; 905 power-domains = <&mediamix>; 906 clocks = <&clk IMX93_CLK_MEDIA_APB>, 907 <&clk IMX93_CLK_MEDIA_AXI>, 908 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 909 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 910 <&clk IMX93_CLK_CAM_PIX>, 911 <&clk IMX93_CLK_PXP_GATE>, 912 <&clk IMX93_CLK_LCDIF_GATE>, 913 <&clk IMX93_CLK_ISI_GATE>, 914 <&clk IMX93_CLK_MIPI_CSI_GATE>, 915 <&clk IMX93_CLK_MIPI_DSI_GATE>; 916 clock-names = "apb", "axi", "nic", "disp", "cam", 917 "pxp", "lcdif", "isi", "csi", "dsi"; 918 #power-domain-cells = <1>; 919 status = "disabled"; 920 }; 921 922 ddr-pmu@4e300dc0 { 923 compatible = "fsl,imx93-ddr-pmu"; 924 reg = <0x4e300dc0 0x200>; 925 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 926 }; 927 }; 928}; 929