1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/fsl,imx93-power.h> 11 12#include "imx93-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 gpio0 = &gpio1; 21 gpio1 = &gpio2; 22 gpio2 = &gpio3; 23 gpio3 = &gpio4; 24 i2c0 = &lpi2c1; 25 i2c1 = &lpi2c2; 26 i2c2 = &lpi2c3; 27 i2c3 = &lpi2c4; 28 i2c4 = &lpi2c5; 29 i2c5 = &lpi2c6; 30 i2c6 = &lpi2c7; 31 i2c7 = &lpi2c8; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &lpuart1; 36 serial1 = &lpuart2; 37 serial2 = &lpuart3; 38 serial3 = &lpuart4; 39 serial4 = &lpuart5; 40 serial5 = &lpuart6; 41 serial6 = &lpuart7; 42 serial7 = &lpuart8; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 A55_0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 reg = <0x0>; 53 enable-method = "psci"; 54 #cooling-cells = <2>; 55 }; 56 57 A55_1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a55"; 60 reg = <0x100>; 61 enable-method = "psci"; 62 #cooling-cells = <2>; 63 }; 64 65 }; 66 67 osc_32k: clock-osc-32k { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <32768>; 71 clock-output-names = "osc_32k"; 72 }; 73 74 osc_24m: clock-osc-24m { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <24000000>; 78 clock-output-names = "osc_24m"; 79 }; 80 81 clk_ext1: clock-ext1 { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <133000000>; 85 clock-output-names = "clk_ext1"; 86 }; 87 88 pmu { 89 compatible = "arm,cortex-a55-pmu"; 90 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 91 }; 92 93 psci { 94 compatible = "arm,psci-1.0"; 95 method = "smc"; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 104 clock-frequency = <24000000>; 105 arm,no-tick-in-suspend; 106 interrupt-parent = <&gic>; 107 }; 108 109 gic: interrupt-controller@48000000 { 110 compatible = "arm,gic-v3"; 111 reg = <0 0x48000000 0 0x10000>, 112 <0 0x48040000 0 0xc0000>; 113 #interrupt-cells = <3>; 114 interrupt-controller; 115 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-parent = <&gic>; 117 }; 118 119 soc@0 { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0x0 0x0 0x0 0x80000000>, 124 <0x28000000 0x0 0x28000000 0x10000000>; 125 126 aips1: bus@44000000 { 127 compatible = "fsl,aips-bus", "simple-bus"; 128 reg = <0x44000000 0x800000>; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 anomix_ns_gpr: syscon@44210000 { 134 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 135 reg = <0x44210000 0x1000>; 136 }; 137 138 mu1: mailbox@44230000 { 139 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 140 reg = <0x44230000 0x10000>; 141 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&clk IMX93_CLK_MU1_B_GATE>; 143 #mbox-cells = <2>; 144 status = "disabled"; 145 }; 146 147 system_counter: timer@44290000 { 148 compatible = "nxp,sysctr-timer"; 149 reg = <0x44290000 0x30000>; 150 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&osc_24m>; 152 clock-names = "per"; 153 nxp,no-divider; 154 }; 155 156 tpm2: pwm@44320000 { 157 compatible = "fsl,imx7ulp-pwm"; 158 reg = <0x44320000 0x10000>; 159 clocks = <&clk IMX93_CLK_TPM2_GATE>; 160 #pwm-cells = <3>; 161 status = "disabled"; 162 }; 163 164 lpi2c1: i2c@44340000 { 165 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 166 reg = <0x44340000 0x10000>; 167 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 169 <&clk IMX93_CLK_BUS_AON>; 170 clock-names = "per", "ipg"; 171 status = "disabled"; 172 }; 173 174 lpi2c2: i2c@44350000 { 175 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 176 reg = <0x44350000 0x10000>; 177 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 179 <&clk IMX93_CLK_BUS_AON>; 180 clock-names = "per", "ipg"; 181 status = "disabled"; 182 }; 183 184 lpspi1: spi@44360000 { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 188 reg = <0x44360000 0x10000>; 189 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 191 <&clk IMX93_CLK_BUS_AON>; 192 clock-names = "per", "ipg"; 193 status = "disabled"; 194 }; 195 196 lpspi2: spi@44370000 { 197 #address-cells = <1>; 198 #size-cells = <0>; 199 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 200 reg = <0x44370000 0x10000>; 201 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 203 <&clk IMX93_CLK_BUS_AON>; 204 clock-names = "per", "ipg"; 205 status = "disabled"; 206 }; 207 208 lpuart1: serial@44380000 { 209 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 210 reg = <0x44380000 0x1000>; 211 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 213 clock-names = "ipg"; 214 status = "disabled"; 215 }; 216 217 lpuart2: serial@44390000 { 218 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 219 reg = <0x44390000 0x1000>; 220 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 222 clock-names = "ipg"; 223 status = "disabled"; 224 }; 225 226 iomuxc: pinctrl@443c0000 { 227 compatible = "fsl,imx93-iomuxc"; 228 reg = <0x443c0000 0x10000>; 229 status = "okay"; 230 }; 231 232 clk: clock-controller@44450000 { 233 compatible = "fsl,imx93-ccm"; 234 reg = <0x44450000 0x10000>; 235 #clock-cells = <1>; 236 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 237 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 238 status = "okay"; 239 }; 240 241 src: system-controller@44460000 { 242 compatible = "fsl,imx93-src", "syscon"; 243 reg = <0x44460000 0x10000>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges; 247 248 mediamix: power-domain@44462400 { 249 compatible = "fsl,imx93-src-slice"; 250 reg = <0x44462400 0x400>, <0x44465800 0x400>; 251 #power-domain-cells = <0>; 252 clocks = <&clk IMX93_CLK_MEDIA_AXI>, 253 <&clk IMX93_CLK_MEDIA_APB>; 254 }; 255 256 mlmix: power-domain@44461800 { 257 compatible = "fsl,imx93-src-slice"; 258 reg = <0x44461800 0x400>, <0x44464800 0x400>; 259 #power-domain-cells = <0>; 260 clocks = <&clk IMX93_CLK_ML_APB>, 261 <&clk IMX93_CLK_ML>; 262 }; 263 }; 264 265 anatop: anatop@44480000 { 266 compatible = "fsl,imx93-anatop", "syscon"; 267 reg = <0x44480000 0x10000>; 268 }; 269 }; 270 271 aips2: bus@42000000 { 272 compatible = "fsl,aips-bus", "simple-bus"; 273 reg = <0x42000000 0x800000>; 274 #address-cells = <1>; 275 #size-cells = <1>; 276 ranges; 277 278 wakeupmix_gpr: syscon@42420000 { 279 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 280 reg = <0x42420000 0x1000>; 281 }; 282 283 mu2: mailbox@42440000 { 284 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 285 reg = <0x42440000 0x10000>; 286 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&clk IMX93_CLK_MU2_B_GATE>; 288 #mbox-cells = <2>; 289 status = "disabled"; 290 }; 291 292 tpm4: pwm@424f0000 { 293 compatible = "fsl,imx7ulp-pwm"; 294 reg = <0x424f0000 0x10000>; 295 clocks = <&clk IMX93_CLK_TPM4_GATE>; 296 #pwm-cells = <3>; 297 status = "disabled"; 298 }; 299 300 tpm5: pwm@42500000 { 301 compatible = "fsl,imx7ulp-pwm"; 302 reg = <0x42500000 0x10000>; 303 clocks = <&clk IMX93_CLK_TPM5_GATE>; 304 #pwm-cells = <3>; 305 status = "disabled"; 306 }; 307 308 tpm6: pwm@42510000 { 309 compatible = "fsl,imx7ulp-pwm"; 310 reg = <0x42510000 0x10000>; 311 clocks = <&clk IMX93_CLK_TPM6_GATE>; 312 #pwm-cells = <3>; 313 status = "disabled"; 314 }; 315 316 lpi2c3: i2c@42530000 { 317 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 318 reg = <0x42530000 0x10000>; 319 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 321 <&clk IMX93_CLK_BUS_WAKEUP>; 322 clock-names = "per", "ipg"; 323 status = "disabled"; 324 }; 325 326 lpi2c4: i2c@42540000 { 327 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 328 reg = <0x42540000 0x10000>; 329 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 331 <&clk IMX93_CLK_BUS_WAKEUP>; 332 clock-names = "per", "ipg"; 333 status = "disabled"; 334 }; 335 336 lpspi3: spi@42550000 { 337 #address-cells = <1>; 338 #size-cells = <0>; 339 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 340 reg = <0x42550000 0x10000>; 341 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&clk IMX93_CLK_LPSPI3_GATE>, 343 <&clk IMX93_CLK_BUS_WAKEUP>; 344 clock-names = "per", "ipg"; 345 status = "disabled"; 346 }; 347 348 lpspi4: spi@42560000 { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 352 reg = <0x42560000 0x10000>; 353 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&clk IMX93_CLK_LPSPI4_GATE>, 355 <&clk IMX93_CLK_BUS_WAKEUP>; 356 clock-names = "per", "ipg"; 357 status = "disabled"; 358 }; 359 360 lpuart3: serial@42570000 { 361 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 362 reg = <0x42570000 0x1000>; 363 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 365 clock-names = "ipg"; 366 status = "disabled"; 367 }; 368 369 lpuart4: serial@42580000 { 370 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 371 reg = <0x42580000 0x1000>; 372 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 374 clock-names = "ipg"; 375 status = "disabled"; 376 }; 377 378 lpuart5: serial@42590000 { 379 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 380 reg = <0x42590000 0x1000>; 381 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 383 clock-names = "ipg"; 384 status = "disabled"; 385 }; 386 387 lpuart6: serial@425a0000 { 388 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 389 reg = <0x425a0000 0x1000>; 390 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 392 clock-names = "ipg"; 393 status = "disabled"; 394 }; 395 396 lpuart7: serial@42690000 { 397 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 398 reg = <0x42690000 0x1000>; 399 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 401 clock-names = "ipg"; 402 status = "disabled"; 403 }; 404 405 lpuart8: serial@426a0000 { 406 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 407 reg = <0x426a0000 0x1000>; 408 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 410 clock-names = "ipg"; 411 status = "disabled"; 412 }; 413 414 lpi2c5: i2c@426b0000 { 415 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 416 reg = <0x426b0000 0x10000>; 417 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 419 <&clk IMX93_CLK_BUS_WAKEUP>; 420 clock-names = "per", "ipg"; 421 status = "disabled"; 422 }; 423 424 lpi2c6: i2c@426c0000 { 425 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 426 reg = <0x426c0000 0x10000>; 427 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 429 <&clk IMX93_CLK_BUS_WAKEUP>; 430 clock-names = "per", "ipg"; 431 status = "disabled"; 432 }; 433 434 lpi2c7: i2c@426d0000 { 435 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 436 reg = <0x426d0000 0x10000>; 437 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 439 <&clk IMX93_CLK_BUS_WAKEUP>; 440 clock-names = "per", "ipg"; 441 status = "disabled"; 442 }; 443 444 lpi2c8: i2c@426e0000 { 445 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 446 reg = <0x426e0000 0x10000>; 447 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 449 <&clk IMX93_CLK_BUS_WAKEUP>; 450 clock-names = "per", "ipg"; 451 status = "disabled"; 452 }; 453 454 lpspi5: spi@426f0000 { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 458 reg = <0x426f0000 0x10000>; 459 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clk IMX93_CLK_LPSPI5_GATE>, 461 <&clk IMX93_CLK_BUS_WAKEUP>; 462 clock-names = "per", "ipg"; 463 status = "disabled"; 464 }; 465 466 lpspi6: spi@42700000 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 470 reg = <0x42700000 0x10000>; 471 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&clk IMX93_CLK_LPSPI6_GATE>, 473 <&clk IMX93_CLK_BUS_WAKEUP>; 474 clock-names = "per", "ipg"; 475 status = "disabled"; 476 }; 477 478 lpspi7: spi@42710000 { 479 #address-cells = <1>; 480 #size-cells = <0>; 481 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 482 reg = <0x42710000 0x10000>; 483 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&clk IMX93_CLK_LPSPI7_GATE>, 485 <&clk IMX93_CLK_BUS_WAKEUP>; 486 clock-names = "per", "ipg"; 487 status = "disabled"; 488 }; 489 490 lpspi8: spi@42720000 { 491 #address-cells = <1>; 492 #size-cells = <0>; 493 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 494 reg = <0x42720000 0x10000>; 495 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&clk IMX93_CLK_LPSPI8_GATE>, 497 <&clk IMX93_CLK_BUS_WAKEUP>; 498 clock-names = "per", "ipg"; 499 status = "disabled"; 500 }; 501 502 }; 503 504 aips3: bus@42800000 { 505 compatible = "fsl,aips-bus", "simple-bus"; 506 reg = <0x42800000 0x800000>; 507 #address-cells = <1>; 508 #size-cells = <1>; 509 ranges; 510 511 usdhc1: mmc@42850000 { 512 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 513 reg = <0x42850000 0x10000>; 514 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 516 <&clk IMX93_CLK_WAKEUP_AXI>, 517 <&clk IMX93_CLK_USDHC1_GATE>; 518 clock-names = "ipg", "ahb", "per"; 519 bus-width = <8>; 520 fsl,tuning-start-tap = <20>; 521 fsl,tuning-step= <2>; 522 status = "disabled"; 523 }; 524 525 usdhc2: mmc@42860000 { 526 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 527 reg = <0x42860000 0x10000>; 528 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 530 <&clk IMX93_CLK_WAKEUP_AXI>, 531 <&clk IMX93_CLK_USDHC2_GATE>; 532 clock-names = "ipg", "ahb", "per"; 533 bus-width = <4>; 534 fsl,tuning-start-tap = <20>; 535 fsl,tuning-step= <2>; 536 status = "disabled"; 537 }; 538 539 usdhc3: mmc@428b0000 { 540 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 541 reg = <0x428b0000 0x10000>; 542 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 544 <&clk IMX93_CLK_WAKEUP_AXI>, 545 <&clk IMX93_CLK_USDHC3_GATE>; 546 clock-names = "ipg", "ahb", "per"; 547 bus-width = <4>; 548 fsl,tuning-start-tap = <20>; 549 fsl,tuning-step= <2>; 550 status = "disabled"; 551 }; 552 }; 553 554 gpio2: gpio@43810080 { 555 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 556 reg = <0x43810080 0x1000>, <0x43810040 0x40>; 557 gpio-controller; 558 #gpio-cells = <2>; 559 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 563 <&clk IMX93_CLK_GPIO2_GATE>; 564 clock-names = "gpio", "port"; 565 gpio-ranges = <&iomuxc 0 4 30>; 566 }; 567 568 gpio3: gpio@43820080 { 569 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 570 reg = <0x43820080 0x1000>, <0x43820040 0x40>; 571 gpio-controller; 572 #gpio-cells = <2>; 573 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 577 <&clk IMX93_CLK_GPIO3_GATE>; 578 clock-names = "gpio", "port"; 579 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 580 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 581 }; 582 583 gpio4: gpio@43830080 { 584 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 585 reg = <0x43830080 0x1000>, <0x43830040 0x40>; 586 gpio-controller; 587 #gpio-cells = <2>; 588 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 592 <&clk IMX93_CLK_GPIO4_GATE>; 593 clock-names = "gpio", "port"; 594 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 595 }; 596 597 gpio1: gpio@47400080 { 598 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 599 reg = <0x47400080 0x1000>, <0x47400040 0x40>; 600 gpio-controller; 601 #gpio-cells = <2>; 602 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 606 <&clk IMX93_CLK_GPIO1_GATE>; 607 clock-names = "gpio", "port"; 608 gpio-ranges = <&iomuxc 0 92 16>; 609 }; 610 611 s4muap: mailbox@47520000 { 612 compatible = "fsl,imx93-mu-s4"; 613 reg = <0x47520000 0x10000>; 614 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 616 interrupt-names = "tx", "rx"; 617 #mbox-cells = <2>; 618 }; 619 620 media_blk_ctrl: system-controller@4ac10000 { 621 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 622 reg = <0x4ac10000 0x10000>; 623 power-domains = <&mediamix>; 624 clocks = <&clk IMX93_CLK_MEDIA_APB>, 625 <&clk IMX93_CLK_MEDIA_AXI>, 626 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 627 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 628 <&clk IMX93_CLK_CAM_PIX>, 629 <&clk IMX93_CLK_PXP_GATE>, 630 <&clk IMX93_CLK_LCDIF_GATE>, 631 <&clk IMX93_CLK_ISI_GATE>, 632 <&clk IMX93_CLK_MIPI_CSI_GATE>, 633 <&clk IMX93_CLK_MIPI_DSI_GATE>; 634 clock-names = "apb", "axi", "nic", "disp", "cam", 635 "pxp", "lcdif", "isi", "csi", "dsi"; 636 #power-domain-cells = <1>; 637 status = "disabled"; 638 }; 639 }; 640}; 641