1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/fsl,imx93-power.h> 11 12#include "imx93-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 gpio0 = &gpio1; 21 gpio1 = &gpio2; 22 gpio2 = &gpio3; 23 gpio3 = &gpio4; 24 i2c0 = &lpi2c1; 25 i2c1 = &lpi2c2; 26 i2c2 = &lpi2c3; 27 i2c3 = &lpi2c4; 28 i2c4 = &lpi2c5; 29 i2c5 = &lpi2c6; 30 i2c6 = &lpi2c7; 31 i2c7 = &lpi2c8; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &lpuart1; 36 serial1 = &lpuart2; 37 serial2 = &lpuart3; 38 serial3 = &lpuart4; 39 serial4 = &lpuart5; 40 serial5 = &lpuart6; 41 serial6 = &lpuart7; 42 serial7 = &lpuart8; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 A55_0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 reg = <0x0>; 53 enable-method = "psci"; 54 #cooling-cells = <2>; 55 }; 56 57 A55_1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a55"; 60 reg = <0x100>; 61 enable-method = "psci"; 62 #cooling-cells = <2>; 63 }; 64 65 }; 66 67 osc_32k: clock-osc-32k { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <32768>; 71 clock-output-names = "osc_32k"; 72 }; 73 74 osc_24m: clock-osc-24m { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <24000000>; 78 clock-output-names = "osc_24m"; 79 }; 80 81 clk_ext1: clock-ext1 { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <133000000>; 85 clock-output-names = "clk_ext1"; 86 }; 87 88 pmu { 89 compatible = "arm,cortex-a55-pmu"; 90 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 91 }; 92 93 psci { 94 compatible = "arm,psci-1.0"; 95 method = "smc"; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 104 clock-frequency = <24000000>; 105 arm,no-tick-in-suspend; 106 interrupt-parent = <&gic>; 107 }; 108 109 gic: interrupt-controller@48000000 { 110 compatible = "arm,gic-v3"; 111 reg = <0 0x48000000 0 0x10000>, 112 <0 0x48040000 0 0xc0000>; 113 #interrupt-cells = <3>; 114 interrupt-controller; 115 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-parent = <&gic>; 117 }; 118 119 soc@0 { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0x0 0x0 0x0 0x80000000>, 124 <0x28000000 0x0 0x28000000 0x10000000>; 125 126 aips1: bus@44000000 { 127 compatible = "fsl,aips-bus", "simple-bus"; 128 reg = <0x44000000 0x800000>; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 anomix_ns_gpr: syscon@44210000 { 134 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 135 reg = <0x44210000 0x1000>; 136 }; 137 138 mu1: mailbox@44230000 { 139 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 140 reg = <0x44230000 0x10000>; 141 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&clk IMX93_CLK_MU1_B_GATE>; 143 #mbox-cells = <2>; 144 status = "disabled"; 145 }; 146 147 system_counter: timer@44290000 { 148 compatible = "nxp,sysctr-timer"; 149 reg = <0x44290000 0x30000>; 150 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&osc_24m>; 152 clock-names = "per"; 153 nxp,no-divider; 154 }; 155 156 tpm2: pwm@44320000 { 157 compatible = "fsl,imx7ulp-pwm"; 158 reg = <0x44320000 0x10000>; 159 clocks = <&clk IMX93_CLK_TPM2_GATE>; 160 #pwm-cells = <3>; 161 status = "disabled"; 162 }; 163 164 lpi2c1: i2c@44340000 { 165 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 166 reg = <0x44340000 0x10000>; 167 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 169 <&clk IMX93_CLK_BUS_AON>; 170 clock-names = "per", "ipg"; 171 status = "disabled"; 172 }; 173 174 lpi2c2: i2c@44350000 { 175 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 176 reg = <0x44350000 0x10000>; 177 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 179 <&clk IMX93_CLK_BUS_AON>; 180 clock-names = "per", "ipg"; 181 status = "disabled"; 182 }; 183 184 lpspi1: spi@44360000 { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 188 reg = <0x44360000 0x10000>; 189 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 191 <&clk IMX93_CLK_BUS_AON>; 192 clock-names = "per", "ipg"; 193 status = "disabled"; 194 }; 195 196 lpspi2: spi@44370000 { 197 #address-cells = <1>; 198 #size-cells = <0>; 199 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 200 reg = <0x44370000 0x10000>; 201 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 203 <&clk IMX93_CLK_BUS_AON>; 204 clock-names = "per", "ipg"; 205 status = "disabled"; 206 }; 207 208 lpuart1: serial@44380000 { 209 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 210 reg = <0x44380000 0x1000>; 211 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 212 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 213 clock-names = "ipg"; 214 status = "disabled"; 215 }; 216 217 lpuart2: serial@44390000 { 218 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 219 reg = <0x44390000 0x1000>; 220 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 222 clock-names = "ipg"; 223 status = "disabled"; 224 }; 225 226 flexcan1: can@443a0000 { 227 compatible = "fsl,imx93-flexcan"; 228 reg = <0x443a0000 0x10000>; 229 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&clk IMX93_CLK_BUS_AON>, 231 <&clk IMX93_CLK_CAN1_GATE>; 232 clock-names = "ipg", "per"; 233 assigned-clocks = <&clk IMX93_CLK_CAN1>; 234 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 235 assigned-clock-rates = <40000000>; 236 fsl,clk-source = /bits/ 8 <0>; 237 status = "disabled"; 238 }; 239 240 iomuxc: pinctrl@443c0000 { 241 compatible = "fsl,imx93-iomuxc"; 242 reg = <0x443c0000 0x10000>; 243 status = "okay"; 244 }; 245 246 clk: clock-controller@44450000 { 247 compatible = "fsl,imx93-ccm"; 248 reg = <0x44450000 0x10000>; 249 #clock-cells = <1>; 250 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 251 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 252 status = "okay"; 253 }; 254 255 src: system-controller@44460000 { 256 compatible = "fsl,imx93-src", "syscon"; 257 reg = <0x44460000 0x10000>; 258 #address-cells = <1>; 259 #size-cells = <1>; 260 ranges; 261 262 mediamix: power-domain@44462400 { 263 compatible = "fsl,imx93-src-slice"; 264 reg = <0x44462400 0x400>, <0x44465800 0x400>; 265 #power-domain-cells = <0>; 266 clocks = <&clk IMX93_CLK_MEDIA_AXI>, 267 <&clk IMX93_CLK_MEDIA_APB>; 268 }; 269 270 mlmix: power-domain@44461800 { 271 compatible = "fsl,imx93-src-slice"; 272 reg = <0x44461800 0x400>, <0x44464800 0x400>; 273 #power-domain-cells = <0>; 274 clocks = <&clk IMX93_CLK_ML_APB>, 275 <&clk IMX93_CLK_ML>; 276 }; 277 }; 278 279 anatop: anatop@44480000 { 280 compatible = "fsl,imx93-anatop", "syscon"; 281 reg = <0x44480000 0x10000>; 282 }; 283 284 adc1: adc@44530000 { 285 compatible = "nxp,imx93-adc"; 286 reg = <0x44530000 0x10000>; 287 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&clk IMX93_CLK_ADC1_GATE>; 292 clock-names = "ipg"; 293 #io-channel-cells = <1>; 294 status = "disabled"; 295 }; 296 }; 297 298 aips2: bus@42000000 { 299 compatible = "fsl,aips-bus", "simple-bus"; 300 reg = <0x42000000 0x800000>; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges; 304 305 wakeupmix_gpr: syscon@42420000 { 306 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 307 reg = <0x42420000 0x1000>; 308 }; 309 310 mu2: mailbox@42440000 { 311 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 312 reg = <0x42440000 0x10000>; 313 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&clk IMX93_CLK_MU2_B_GATE>; 315 #mbox-cells = <2>; 316 status = "disabled"; 317 }; 318 319 tpm4: pwm@424f0000 { 320 compatible = "fsl,imx7ulp-pwm"; 321 reg = <0x424f0000 0x10000>; 322 clocks = <&clk IMX93_CLK_TPM4_GATE>; 323 #pwm-cells = <3>; 324 status = "disabled"; 325 }; 326 327 tpm5: pwm@42500000 { 328 compatible = "fsl,imx7ulp-pwm"; 329 reg = <0x42500000 0x10000>; 330 clocks = <&clk IMX93_CLK_TPM5_GATE>; 331 #pwm-cells = <3>; 332 status = "disabled"; 333 }; 334 335 tpm6: pwm@42510000 { 336 compatible = "fsl,imx7ulp-pwm"; 337 reg = <0x42510000 0x10000>; 338 clocks = <&clk IMX93_CLK_TPM6_GATE>; 339 #pwm-cells = <3>; 340 status = "disabled"; 341 }; 342 343 lpi2c3: i2c@42530000 { 344 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 345 reg = <0x42530000 0x10000>; 346 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 348 <&clk IMX93_CLK_BUS_WAKEUP>; 349 clock-names = "per", "ipg"; 350 status = "disabled"; 351 }; 352 353 lpi2c4: i2c@42540000 { 354 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 355 reg = <0x42540000 0x10000>; 356 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 358 <&clk IMX93_CLK_BUS_WAKEUP>; 359 clock-names = "per", "ipg"; 360 status = "disabled"; 361 }; 362 363 lpspi3: spi@42550000 { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 367 reg = <0x42550000 0x10000>; 368 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&clk IMX93_CLK_LPSPI3_GATE>, 370 <&clk IMX93_CLK_BUS_WAKEUP>; 371 clock-names = "per", "ipg"; 372 status = "disabled"; 373 }; 374 375 lpspi4: spi@42560000 { 376 #address-cells = <1>; 377 #size-cells = <0>; 378 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 379 reg = <0x42560000 0x10000>; 380 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clk IMX93_CLK_LPSPI4_GATE>, 382 <&clk IMX93_CLK_BUS_WAKEUP>; 383 clock-names = "per", "ipg"; 384 status = "disabled"; 385 }; 386 387 lpuart3: serial@42570000 { 388 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 389 reg = <0x42570000 0x1000>; 390 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 392 clock-names = "ipg"; 393 status = "disabled"; 394 }; 395 396 lpuart4: serial@42580000 { 397 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 398 reg = <0x42580000 0x1000>; 399 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 401 clock-names = "ipg"; 402 status = "disabled"; 403 }; 404 405 lpuart5: serial@42590000 { 406 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 407 reg = <0x42590000 0x1000>; 408 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 410 clock-names = "ipg"; 411 status = "disabled"; 412 }; 413 414 lpuart6: serial@425a0000 { 415 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 416 reg = <0x425a0000 0x1000>; 417 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 419 clock-names = "ipg"; 420 status = "disabled"; 421 }; 422 423 flexcan2: can@425b0000 { 424 compatible = "fsl,imx93-flexcan"; 425 reg = <0x425b0000 0x10000>; 426 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 428 <&clk IMX93_CLK_CAN2_GATE>; 429 clock-names = "ipg", "per"; 430 assigned-clocks = <&clk IMX93_CLK_CAN2>; 431 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 432 assigned-clock-rates = <40000000>; 433 fsl,clk-source = /bits/ 8 <0>; 434 status = "disabled"; 435 }; 436 437 lpuart7: serial@42690000 { 438 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 439 reg = <0x42690000 0x1000>; 440 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 442 clock-names = "ipg"; 443 status = "disabled"; 444 }; 445 446 lpuart8: serial@426a0000 { 447 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 448 reg = <0x426a0000 0x1000>; 449 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 451 clock-names = "ipg"; 452 status = "disabled"; 453 }; 454 455 lpi2c5: i2c@426b0000 { 456 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 457 reg = <0x426b0000 0x10000>; 458 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 460 <&clk IMX93_CLK_BUS_WAKEUP>; 461 clock-names = "per", "ipg"; 462 status = "disabled"; 463 }; 464 465 lpi2c6: i2c@426c0000 { 466 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 467 reg = <0x426c0000 0x10000>; 468 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 470 <&clk IMX93_CLK_BUS_WAKEUP>; 471 clock-names = "per", "ipg"; 472 status = "disabled"; 473 }; 474 475 lpi2c7: i2c@426d0000 { 476 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 477 reg = <0x426d0000 0x10000>; 478 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 480 <&clk IMX93_CLK_BUS_WAKEUP>; 481 clock-names = "per", "ipg"; 482 status = "disabled"; 483 }; 484 485 lpi2c8: i2c@426e0000 { 486 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 487 reg = <0x426e0000 0x10000>; 488 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 490 <&clk IMX93_CLK_BUS_WAKEUP>; 491 clock-names = "per", "ipg"; 492 status = "disabled"; 493 }; 494 495 lpspi5: spi@426f0000 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 499 reg = <0x426f0000 0x10000>; 500 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&clk IMX93_CLK_LPSPI5_GATE>, 502 <&clk IMX93_CLK_BUS_WAKEUP>; 503 clock-names = "per", "ipg"; 504 status = "disabled"; 505 }; 506 507 lpspi6: spi@42700000 { 508 #address-cells = <1>; 509 #size-cells = <0>; 510 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 511 reg = <0x42700000 0x10000>; 512 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&clk IMX93_CLK_LPSPI6_GATE>, 514 <&clk IMX93_CLK_BUS_WAKEUP>; 515 clock-names = "per", "ipg"; 516 status = "disabled"; 517 }; 518 519 lpspi7: spi@42710000 { 520 #address-cells = <1>; 521 #size-cells = <0>; 522 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 523 reg = <0x42710000 0x10000>; 524 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&clk IMX93_CLK_LPSPI7_GATE>, 526 <&clk IMX93_CLK_BUS_WAKEUP>; 527 clock-names = "per", "ipg"; 528 status = "disabled"; 529 }; 530 531 lpspi8: spi@42720000 { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 535 reg = <0x42720000 0x10000>; 536 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&clk IMX93_CLK_LPSPI8_GATE>, 538 <&clk IMX93_CLK_BUS_WAKEUP>; 539 clock-names = "per", "ipg"; 540 status = "disabled"; 541 }; 542 543 }; 544 545 aips3: bus@42800000 { 546 compatible = "fsl,aips-bus", "simple-bus"; 547 reg = <0x42800000 0x800000>; 548 #address-cells = <1>; 549 #size-cells = <1>; 550 ranges; 551 552 usdhc1: mmc@42850000 { 553 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 554 reg = <0x42850000 0x10000>; 555 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 557 <&clk IMX93_CLK_WAKEUP_AXI>, 558 <&clk IMX93_CLK_USDHC1_GATE>; 559 clock-names = "ipg", "ahb", "per"; 560 bus-width = <8>; 561 fsl,tuning-start-tap = <20>; 562 fsl,tuning-step= <2>; 563 status = "disabled"; 564 }; 565 566 usdhc2: mmc@42860000 { 567 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 568 reg = <0x42860000 0x10000>; 569 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 571 <&clk IMX93_CLK_WAKEUP_AXI>, 572 <&clk IMX93_CLK_USDHC2_GATE>; 573 clock-names = "ipg", "ahb", "per"; 574 bus-width = <4>; 575 fsl,tuning-start-tap = <20>; 576 fsl,tuning-step= <2>; 577 status = "disabled"; 578 }; 579 580 usdhc3: mmc@428b0000 { 581 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 582 reg = <0x428b0000 0x10000>; 583 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 585 <&clk IMX93_CLK_WAKEUP_AXI>, 586 <&clk IMX93_CLK_USDHC3_GATE>; 587 clock-names = "ipg", "ahb", "per"; 588 bus-width = <4>; 589 fsl,tuning-start-tap = <20>; 590 fsl,tuning-step= <2>; 591 status = "disabled"; 592 }; 593 }; 594 595 gpio2: gpio@43810080 { 596 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 597 reg = <0x43810080 0x1000>, <0x43810040 0x40>; 598 gpio-controller; 599 #gpio-cells = <2>; 600 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 601 interrupt-controller; 602 #interrupt-cells = <2>; 603 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 604 <&clk IMX93_CLK_GPIO2_GATE>; 605 clock-names = "gpio", "port"; 606 gpio-ranges = <&iomuxc 0 4 30>; 607 }; 608 609 gpio3: gpio@43820080 { 610 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 611 reg = <0x43820080 0x1000>, <0x43820040 0x40>; 612 gpio-controller; 613 #gpio-cells = <2>; 614 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 615 interrupt-controller; 616 #interrupt-cells = <2>; 617 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 618 <&clk IMX93_CLK_GPIO3_GATE>; 619 clock-names = "gpio", "port"; 620 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 621 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 622 }; 623 624 gpio4: gpio@43830080 { 625 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 626 reg = <0x43830080 0x1000>, <0x43830040 0x40>; 627 gpio-controller; 628 #gpio-cells = <2>; 629 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 633 <&clk IMX93_CLK_GPIO4_GATE>; 634 clock-names = "gpio", "port"; 635 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 636 }; 637 638 gpio1: gpio@47400080 { 639 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 640 reg = <0x47400080 0x1000>, <0x47400040 0x40>; 641 gpio-controller; 642 #gpio-cells = <2>; 643 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 647 <&clk IMX93_CLK_GPIO1_GATE>; 648 clock-names = "gpio", "port"; 649 gpio-ranges = <&iomuxc 0 92 16>; 650 }; 651 652 s4muap: mailbox@47520000 { 653 compatible = "fsl,imx93-mu-s4"; 654 reg = <0x47520000 0x10000>; 655 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 657 interrupt-names = "tx", "rx"; 658 #mbox-cells = <2>; 659 }; 660 661 media_blk_ctrl: system-controller@4ac10000 { 662 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 663 reg = <0x4ac10000 0x10000>; 664 power-domains = <&mediamix>; 665 clocks = <&clk IMX93_CLK_MEDIA_APB>, 666 <&clk IMX93_CLK_MEDIA_AXI>, 667 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 668 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 669 <&clk IMX93_CLK_CAM_PIX>, 670 <&clk IMX93_CLK_PXP_GATE>, 671 <&clk IMX93_CLK_LCDIF_GATE>, 672 <&clk IMX93_CLK_ISI_GATE>, 673 <&clk IMX93_CLK_MIPI_CSI_GATE>, 674 <&clk IMX93_CLK_MIPI_DSI_GATE>; 675 clock-names = "apb", "axi", "nic", "disp", "cam", 676 "pxp", "lcdif", "isi", "csi", "dsi"; 677 #power-domain-cells = <1>; 678 status = "disabled"; 679 }; 680 }; 681}; 682