1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/fsl,imx93-power.h> 11 12#include "imx93-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 gpio0 = &gpio1; 21 gpio1 = &gpio2; 22 gpio2 = &gpio3; 23 gpio3 = &gpio4; 24 i2c0 = &lpi2c1; 25 i2c1 = &lpi2c2; 26 i2c2 = &lpi2c3; 27 i2c3 = &lpi2c4; 28 i2c4 = &lpi2c5; 29 i2c5 = &lpi2c6; 30 i2c6 = &lpi2c7; 31 i2c7 = &lpi2c8; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &lpuart1; 36 serial1 = &lpuart2; 37 serial2 = &lpuart3; 38 serial3 = &lpuart4; 39 serial4 = &lpuart5; 40 serial5 = &lpuart6; 41 serial6 = &lpuart7; 42 serial7 = &lpuart8; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 A55_0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 reg = <0x0>; 53 enable-method = "psci"; 54 #cooling-cells = <2>; 55 }; 56 57 A55_1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a55"; 60 reg = <0x100>; 61 enable-method = "psci"; 62 #cooling-cells = <2>; 63 }; 64 65 }; 66 67 osc_32k: clock-osc-32k { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <32768>; 71 clock-output-names = "osc_32k"; 72 }; 73 74 osc_24m: clock-osc-24m { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <24000000>; 78 clock-output-names = "osc_24m"; 79 }; 80 81 clk_ext1: clock-ext1 { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <133000000>; 85 clock-output-names = "clk_ext1"; 86 }; 87 88 pmu { 89 compatible = "arm,cortex-a55-pmu"; 90 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 91 }; 92 93 psci { 94 compatible = "arm,psci-1.0"; 95 method = "smc"; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 104 clock-frequency = <24000000>; 105 arm,no-tick-in-suspend; 106 interrupt-parent = <&gic>; 107 }; 108 109 gic: interrupt-controller@48000000 { 110 compatible = "arm,gic-v3"; 111 reg = <0 0x48000000 0 0x10000>, 112 <0 0x48040000 0 0xc0000>; 113 #interrupt-cells = <3>; 114 interrupt-controller; 115 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-parent = <&gic>; 117 }; 118 119 soc@0 { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0x0 0x0 0x0 0x80000000>, 124 <0x28000000 0x0 0x28000000 0x10000000>; 125 126 aips1: bus@44000000 { 127 compatible = "fsl,aips-bus", "simple-bus"; 128 reg = <0x44000000 0x800000>; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 anomix_ns_gpr: syscon@44210000 { 134 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 135 reg = <0x44210000 0x1000>; 136 }; 137 138 mu1: mailbox@44230000 { 139 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 140 reg = <0x44230000 0x10000>; 141 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&clk IMX93_CLK_MU1_B_GATE>; 143 #mbox-cells = <2>; 144 status = "disabled"; 145 }; 146 147 system_counter: timer@44290000 { 148 compatible = "nxp,sysctr-timer"; 149 reg = <0x44290000 0x30000>; 150 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&osc_24m>; 152 clock-names = "per"; 153 nxp,no-divider; 154 }; 155 156 tpm2: pwm@44320000 { 157 compatible = "fsl,imx7ulp-pwm"; 158 reg = <0x44320000 0x10000>; 159 clocks = <&clk IMX93_CLK_TPM2_GATE>; 160 #pwm-cells = <3>; 161 status = "disabled"; 162 }; 163 164 lpi2c1: i2c@44340000 { 165 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 166 reg = <0x44340000 0x10000>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 171 <&clk IMX93_CLK_BUS_AON>; 172 clock-names = "per", "ipg"; 173 status = "disabled"; 174 }; 175 176 lpi2c2: i2c@44350000 { 177 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 178 reg = <0x44350000 0x10000>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 183 <&clk IMX93_CLK_BUS_AON>; 184 clock-names = "per", "ipg"; 185 status = "disabled"; 186 }; 187 188 lpspi1: spi@44360000 { 189 #address-cells = <1>; 190 #size-cells = <0>; 191 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 192 reg = <0x44360000 0x10000>; 193 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 195 <&clk IMX93_CLK_BUS_AON>; 196 clock-names = "per", "ipg"; 197 status = "disabled"; 198 }; 199 200 lpspi2: spi@44370000 { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 204 reg = <0x44370000 0x10000>; 205 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 207 <&clk IMX93_CLK_BUS_AON>; 208 clock-names = "per", "ipg"; 209 status = "disabled"; 210 }; 211 212 lpuart1: serial@44380000 { 213 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 214 reg = <0x44380000 0x1000>; 215 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 217 clock-names = "ipg"; 218 status = "disabled"; 219 }; 220 221 lpuart2: serial@44390000 { 222 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 223 reg = <0x44390000 0x1000>; 224 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 226 clock-names = "ipg"; 227 status = "disabled"; 228 }; 229 230 flexcan1: can@443a0000 { 231 compatible = "fsl,imx93-flexcan"; 232 reg = <0x443a0000 0x10000>; 233 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&clk IMX93_CLK_BUS_AON>, 235 <&clk IMX93_CLK_CAN1_GATE>; 236 clock-names = "ipg", "per"; 237 assigned-clocks = <&clk IMX93_CLK_CAN1>; 238 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 239 assigned-clock-rates = <40000000>; 240 fsl,clk-source = /bits/ 8 <0>; 241 status = "disabled"; 242 }; 243 244 iomuxc: pinctrl@443c0000 { 245 compatible = "fsl,imx93-iomuxc"; 246 reg = <0x443c0000 0x10000>; 247 status = "okay"; 248 }; 249 250 clk: clock-controller@44450000 { 251 compatible = "fsl,imx93-ccm"; 252 reg = <0x44450000 0x10000>; 253 #clock-cells = <1>; 254 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 255 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 256 status = "okay"; 257 }; 258 259 src: system-controller@44460000 { 260 compatible = "fsl,imx93-src", "syscon"; 261 reg = <0x44460000 0x10000>; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges; 265 266 mediamix: power-domain@44462400 { 267 compatible = "fsl,imx93-src-slice"; 268 reg = <0x44462400 0x400>, <0x44465800 0x400>; 269 #power-domain-cells = <0>; 270 clocks = <&clk IMX93_CLK_MEDIA_AXI>, 271 <&clk IMX93_CLK_MEDIA_APB>; 272 }; 273 274 mlmix: power-domain@44461800 { 275 compatible = "fsl,imx93-src-slice"; 276 reg = <0x44461800 0x400>, <0x44464800 0x400>; 277 #power-domain-cells = <0>; 278 clocks = <&clk IMX93_CLK_ML_APB>, 279 <&clk IMX93_CLK_ML>; 280 }; 281 }; 282 283 anatop: anatop@44480000 { 284 compatible = "fsl,imx93-anatop", "syscon"; 285 reg = <0x44480000 0x10000>; 286 }; 287 288 adc1: adc@44530000 { 289 compatible = "nxp,imx93-adc"; 290 reg = <0x44530000 0x10000>; 291 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clk IMX93_CLK_ADC1_GATE>; 296 clock-names = "ipg"; 297 #io-channel-cells = <1>; 298 status = "disabled"; 299 }; 300 }; 301 302 aips2: bus@42000000 { 303 compatible = "fsl,aips-bus", "simple-bus"; 304 reg = <0x42000000 0x800000>; 305 #address-cells = <1>; 306 #size-cells = <1>; 307 ranges; 308 309 wakeupmix_gpr: syscon@42420000 { 310 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 311 reg = <0x42420000 0x1000>; 312 }; 313 314 mu2: mailbox@42440000 { 315 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; 316 reg = <0x42440000 0x10000>; 317 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&clk IMX93_CLK_MU2_B_GATE>; 319 #mbox-cells = <2>; 320 status = "disabled"; 321 }; 322 323 tpm4: pwm@424f0000 { 324 compatible = "fsl,imx7ulp-pwm"; 325 reg = <0x424f0000 0x10000>; 326 clocks = <&clk IMX93_CLK_TPM4_GATE>; 327 #pwm-cells = <3>; 328 status = "disabled"; 329 }; 330 331 tpm5: pwm@42500000 { 332 compatible = "fsl,imx7ulp-pwm"; 333 reg = <0x42500000 0x10000>; 334 clocks = <&clk IMX93_CLK_TPM5_GATE>; 335 #pwm-cells = <3>; 336 status = "disabled"; 337 }; 338 339 tpm6: pwm@42510000 { 340 compatible = "fsl,imx7ulp-pwm"; 341 reg = <0x42510000 0x10000>; 342 clocks = <&clk IMX93_CLK_TPM6_GATE>; 343 #pwm-cells = <3>; 344 status = "disabled"; 345 }; 346 347 lpi2c3: i2c@42530000 { 348 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 349 reg = <0x42530000 0x10000>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 354 <&clk IMX93_CLK_BUS_WAKEUP>; 355 clock-names = "per", "ipg"; 356 status = "disabled"; 357 }; 358 359 lpi2c4: i2c@42540000 { 360 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 361 reg = <0x42540000 0x10000>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 366 <&clk IMX93_CLK_BUS_WAKEUP>; 367 clock-names = "per", "ipg"; 368 status = "disabled"; 369 }; 370 371 lpspi3: spi@42550000 { 372 #address-cells = <1>; 373 #size-cells = <0>; 374 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 375 reg = <0x42550000 0x10000>; 376 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clk IMX93_CLK_LPSPI3_GATE>, 378 <&clk IMX93_CLK_BUS_WAKEUP>; 379 clock-names = "per", "ipg"; 380 status = "disabled"; 381 }; 382 383 lpspi4: spi@42560000 { 384 #address-cells = <1>; 385 #size-cells = <0>; 386 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 387 reg = <0x42560000 0x10000>; 388 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clk IMX93_CLK_LPSPI4_GATE>, 390 <&clk IMX93_CLK_BUS_WAKEUP>; 391 clock-names = "per", "ipg"; 392 status = "disabled"; 393 }; 394 395 lpuart3: serial@42570000 { 396 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 397 reg = <0x42570000 0x1000>; 398 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 400 clock-names = "ipg"; 401 status = "disabled"; 402 }; 403 404 lpuart4: serial@42580000 { 405 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 406 reg = <0x42580000 0x1000>; 407 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 409 clock-names = "ipg"; 410 status = "disabled"; 411 }; 412 413 lpuart5: serial@42590000 { 414 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 415 reg = <0x42590000 0x1000>; 416 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 418 clock-names = "ipg"; 419 status = "disabled"; 420 }; 421 422 lpuart6: serial@425a0000 { 423 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 424 reg = <0x425a0000 0x1000>; 425 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 427 clock-names = "ipg"; 428 status = "disabled"; 429 }; 430 431 flexcan2: can@425b0000 { 432 compatible = "fsl,imx93-flexcan"; 433 reg = <0x425b0000 0x10000>; 434 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 436 <&clk IMX93_CLK_CAN2_GATE>; 437 clock-names = "ipg", "per"; 438 assigned-clocks = <&clk IMX93_CLK_CAN2>; 439 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 440 assigned-clock-rates = <40000000>; 441 fsl,clk-source = /bits/ 8 <0>; 442 status = "disabled"; 443 }; 444 445 lpuart7: serial@42690000 { 446 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 447 reg = <0x42690000 0x1000>; 448 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 450 clock-names = "ipg"; 451 status = "disabled"; 452 }; 453 454 lpuart8: serial@426a0000 { 455 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; 456 reg = <0x426a0000 0x1000>; 457 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 459 clock-names = "ipg"; 460 status = "disabled"; 461 }; 462 463 lpi2c5: i2c@426b0000 { 464 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 465 reg = <0x426b0000 0x10000>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 470 <&clk IMX93_CLK_BUS_WAKEUP>; 471 clock-names = "per", "ipg"; 472 status = "disabled"; 473 }; 474 475 lpi2c6: i2c@426c0000 { 476 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 477 reg = <0x426c0000 0x10000>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 482 <&clk IMX93_CLK_BUS_WAKEUP>; 483 clock-names = "per", "ipg"; 484 status = "disabled"; 485 }; 486 487 lpi2c7: i2c@426d0000 { 488 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 489 reg = <0x426d0000 0x10000>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 494 <&clk IMX93_CLK_BUS_WAKEUP>; 495 clock-names = "per", "ipg"; 496 status = "disabled"; 497 }; 498 499 lpi2c8: i2c@426e0000 { 500 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 501 reg = <0x426e0000 0x10000>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 506 <&clk IMX93_CLK_BUS_WAKEUP>; 507 clock-names = "per", "ipg"; 508 status = "disabled"; 509 }; 510 511 lpspi5: spi@426f0000 { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 515 reg = <0x426f0000 0x10000>; 516 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clk IMX93_CLK_LPSPI5_GATE>, 518 <&clk IMX93_CLK_BUS_WAKEUP>; 519 clock-names = "per", "ipg"; 520 status = "disabled"; 521 }; 522 523 lpspi6: spi@42700000 { 524 #address-cells = <1>; 525 #size-cells = <0>; 526 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 527 reg = <0x42700000 0x10000>; 528 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&clk IMX93_CLK_LPSPI6_GATE>, 530 <&clk IMX93_CLK_BUS_WAKEUP>; 531 clock-names = "per", "ipg"; 532 status = "disabled"; 533 }; 534 535 lpspi7: spi@42710000 { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 539 reg = <0x42710000 0x10000>; 540 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&clk IMX93_CLK_LPSPI7_GATE>, 542 <&clk IMX93_CLK_BUS_WAKEUP>; 543 clock-names = "per", "ipg"; 544 status = "disabled"; 545 }; 546 547 lpspi8: spi@42720000 { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 551 reg = <0x42720000 0x10000>; 552 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clk IMX93_CLK_LPSPI8_GATE>, 554 <&clk IMX93_CLK_BUS_WAKEUP>; 555 clock-names = "per", "ipg"; 556 status = "disabled"; 557 }; 558 559 }; 560 561 aips3: bus@42800000 { 562 compatible = "fsl,aips-bus", "simple-bus"; 563 reg = <0x42800000 0x800000>; 564 #address-cells = <1>; 565 #size-cells = <1>; 566 ranges; 567 568 usdhc1: mmc@42850000 { 569 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 570 reg = <0x42850000 0x10000>; 571 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 573 <&clk IMX93_CLK_WAKEUP_AXI>, 574 <&clk IMX93_CLK_USDHC1_GATE>; 575 clock-names = "ipg", "ahb", "per"; 576 bus-width = <8>; 577 fsl,tuning-start-tap = <20>; 578 fsl,tuning-step= <2>; 579 status = "disabled"; 580 }; 581 582 usdhc2: mmc@42860000 { 583 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 584 reg = <0x42860000 0x10000>; 585 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 587 <&clk IMX93_CLK_WAKEUP_AXI>, 588 <&clk IMX93_CLK_USDHC2_GATE>; 589 clock-names = "ipg", "ahb", "per"; 590 bus-width = <4>; 591 fsl,tuning-start-tap = <20>; 592 fsl,tuning-step= <2>; 593 status = "disabled"; 594 }; 595 596 eqos: ethernet@428a0000 { 597 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; 598 reg = <0x428a0000 0x10000>; 599 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 601 interrupt-names = "macirq", "eth_wake_irq"; 602 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, 603 <&clk IMX93_CLK_ENET_QOS_GATE>, 604 <&clk IMX93_CLK_ENET_TIMER2>, 605 <&clk IMX93_CLK_ENET>, 606 <&clk IMX93_CLK_ENET_QOS_GATE>; 607 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; 608 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, 609 <&clk IMX93_CLK_ENET>; 610 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 611 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 612 assigned-clock-rates = <100000000>, <250000000>; 613 intf_mode = <&wakeupmix_gpr 0x28>; 614 snps,clk-csr = <0>; 615 status = "disabled"; 616 }; 617 618 fec: ethernet@42890000 { 619 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 620 reg = <0x42890000 0x10000>; 621 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&clk IMX93_CLK_ENET1_GATE>, 626 <&clk IMX93_CLK_ENET1_GATE>, 627 <&clk IMX93_CLK_ENET_TIMER1>, 628 <&clk IMX93_CLK_ENET_REF>, 629 <&clk IMX93_CLK_ENET_REF_PHY>; 630 clock-names = "ipg", "ahb", "ptp", 631 "enet_clk_ref", "enet_out"; 632 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 633 <&clk IMX93_CLK_ENET_REF>, 634 <&clk IMX93_CLK_ENET_REF_PHY>; 635 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 636 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, 637 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 638 assigned-clock-rates = <100000000>, <250000000>, <50000000>; 639 fsl,num-tx-queues = <3>; 640 fsl,num-rx-queues = <3>; 641 status = "disabled"; 642 }; 643 644 usdhc3: mmc@428b0000 { 645 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 646 reg = <0x428b0000 0x10000>; 647 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 649 <&clk IMX93_CLK_WAKEUP_AXI>, 650 <&clk IMX93_CLK_USDHC3_GATE>; 651 clock-names = "ipg", "ahb", "per"; 652 bus-width = <4>; 653 fsl,tuning-start-tap = <20>; 654 fsl,tuning-step= <2>; 655 status = "disabled"; 656 }; 657 }; 658 659 gpio2: gpio@43810080 { 660 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 661 reg = <0x43810080 0x1000>, <0x43810040 0x40>; 662 gpio-controller; 663 #gpio-cells = <2>; 664 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 665 interrupt-controller; 666 #interrupt-cells = <2>; 667 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 668 <&clk IMX93_CLK_GPIO2_GATE>; 669 clock-names = "gpio", "port"; 670 gpio-ranges = <&iomuxc 0 4 30>; 671 }; 672 673 gpio3: gpio@43820080 { 674 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 675 reg = <0x43820080 0x1000>, <0x43820040 0x40>; 676 gpio-controller; 677 #gpio-cells = <2>; 678 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 679 interrupt-controller; 680 #interrupt-cells = <2>; 681 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 682 <&clk IMX93_CLK_GPIO3_GATE>; 683 clock-names = "gpio", "port"; 684 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 685 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 686 }; 687 688 gpio4: gpio@43830080 { 689 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 690 reg = <0x43830080 0x1000>, <0x43830040 0x40>; 691 gpio-controller; 692 #gpio-cells = <2>; 693 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 694 interrupt-controller; 695 #interrupt-cells = <2>; 696 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 697 <&clk IMX93_CLK_GPIO4_GATE>; 698 clock-names = "gpio", "port"; 699 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 700 }; 701 702 gpio1: gpio@47400080 { 703 compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; 704 reg = <0x47400080 0x1000>, <0x47400040 0x40>; 705 gpio-controller; 706 #gpio-cells = <2>; 707 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-controller; 709 #interrupt-cells = <2>; 710 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 711 <&clk IMX93_CLK_GPIO1_GATE>; 712 clock-names = "gpio", "port"; 713 gpio-ranges = <&iomuxc 0 92 16>; 714 }; 715 716 s4muap: mailbox@47520000 { 717 compatible = "fsl,imx93-mu-s4"; 718 reg = <0x47520000 0x10000>; 719 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 721 interrupt-names = "tx", "rx"; 722 #mbox-cells = <2>; 723 }; 724 725 media_blk_ctrl: system-controller@4ac10000 { 726 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 727 reg = <0x4ac10000 0x10000>; 728 power-domains = <&mediamix>; 729 clocks = <&clk IMX93_CLK_MEDIA_APB>, 730 <&clk IMX93_CLK_MEDIA_AXI>, 731 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 732 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 733 <&clk IMX93_CLK_CAM_PIX>, 734 <&clk IMX93_CLK_PXP_GATE>, 735 <&clk IMX93_CLK_LCDIF_GATE>, 736 <&clk IMX93_CLK_ISI_GATE>, 737 <&clk IMX93_CLK_MIPI_CSI_GATE>, 738 <&clk IMX93_CLK_MIPI_DSI_GATE>; 739 clock-names = "apb", "axi", "nic", "disp", "cam", 740 "pxp", "lcdif", "isi", "csi", "dsi"; 741 #power-domain-cells = <1>; 742 status = "disabled"; 743 }; 744 }; 745}; 746