1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx93.dtsi" 9 10/ { 11 model = "NXP i.MX93 11X11 EVK board"; 12 compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 13 14 chosen { 15 stdout-path = &lpuart1; 16 }; 17 18 reg_vref_1v8: regulator-adc-vref { 19 compatible = "regulator-fixed"; 20 regulator-name = "vref_1v8"; 21 regulator-min-microvolt = <1800000>; 22 regulator-max-microvolt = <1800000>; 23 }; 24 25 reg_usdhc2_vmmc: regulator-usdhc2 { 26 compatible = "regulator-fixed"; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 29 regulator-name = "VSD_3V3"; 30 regulator-min-microvolt = <3300000>; 31 regulator-max-microvolt = <3300000>; 32 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 33 enable-active-high; 34 }; 35}; 36 37&adc1 { 38 vref-supply = <®_vref_1v8>; 39 status = "okay"; 40}; 41 42&mu1 { 43 status = "okay"; 44}; 45 46&mu2 { 47 status = "okay"; 48}; 49 50&eqos { 51 pinctrl-names = "default"; 52 pinctrl-0 = <&pinctrl_eqos>; 53 phy-mode = "rgmii-id"; 54 phy-handle = <ðphy1>; 55 status = "okay"; 56 57 mdio { 58 compatible = "snps,dwmac-mdio"; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 clock-frequency = <5000000>; 62 63 ethphy1: ethernet-phy@1 { 64 reg = <1>; 65 eee-broken-1000t; 66 }; 67 }; 68}; 69 70&fec { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_fec>; 73 phy-mode = "rgmii-id"; 74 phy-handle = <ðphy2>; 75 fsl,magic-packet; 76 status = "okay"; 77 78 mdio { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 clock-frequency = <5000000>; 82 83 ethphy2: ethernet-phy@2 { 84 reg = <2>; 85 eee-broken-1000t; 86 }; 87 }; 88}; 89 90&lpuart1 { /* console */ 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_uart1>; 93 status = "okay"; 94}; 95 96&usdhc1 { 97 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 98 pinctrl-0 = <&pinctrl_usdhc1>; 99 pinctrl-1 = <&pinctrl_usdhc1>; 100 pinctrl-2 = <&pinctrl_usdhc1>; 101 bus-width = <8>; 102 non-removable; 103 status = "okay"; 104}; 105 106&usdhc2 { 107 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 108 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 109 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 110 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 111 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 112 vmmc-supply = <®_usdhc2_vmmc>; 113 bus-width = <4>; 114 status = "okay"; 115 no-sdio; 116 no-mmc; 117}; 118 119&iomuxc { 120 pinctrl_eqos: eqosgrp { 121 fsl,pins = < 122 MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 123 MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 124 MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 125 MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 126 MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 127 MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 128 MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 129 MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 130 MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 131 MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 132 MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 133 MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 134 MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 135 MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 136 >; 137 }; 138 139 pinctrl_fec: fecgrp { 140 fsl,pins = < 141 MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 142 MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 143 MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 144 MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 145 MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 146 MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 147 MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 148 MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 149 MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 150 MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 151 MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 152 MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 153 MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe 154 MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 155 >; 156 }; 157 158 pinctrl_uart1: uart1grp { 159 fsl,pins = < 160 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 161 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 162 >; 163 }; 164 165 pinctrl_usdhc1: usdhc1grp { 166 fsl,pins = < 167 MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 168 MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe 169 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 170 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 171 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 172 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 173 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 174 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 175 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 176 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 177 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 178 >; 179 }; 180 181 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 182 fsl,pins = < 183 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 184 >; 185 }; 186 187 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 188 fsl,pins = < 189 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 190 >; 191 }; 192 193 pinctrl_usdhc2: usdhc2grp { 194 fsl,pins = < 195 MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 196 MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe 197 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 198 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 199 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 200 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 201 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 202 >; 203 }; 204}; 205