1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx93.dtsi" 9 10/ { 11 model = "NXP i.MX93 11X11 EVK board"; 12 compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 13 14 chosen { 15 stdout-path = &lpuart1; 16 }; 17 18 reg_vref_1v8: regulator-adc-vref { 19 compatible = "regulator-fixed"; 20 regulator-name = "vref_1v8"; 21 regulator-min-microvolt = <1800000>; 22 regulator-max-microvolt = <1800000>; 23 }; 24 25 reg_usdhc2_vmmc: regulator-usdhc2 { 26 compatible = "regulator-fixed"; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 29 regulator-name = "VSD_3V3"; 30 regulator-min-microvolt = <3300000>; 31 regulator-max-microvolt = <3300000>; 32 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 33 enable-active-high; 34 }; 35}; 36 37&adc1 { 38 vref-supply = <®_vref_1v8>; 39 status = "okay"; 40}; 41 42&mu1 { 43 status = "okay"; 44}; 45 46&mu2 { 47 status = "okay"; 48}; 49 50&lpuart1 { /* console */ 51 pinctrl-names = "default"; 52 pinctrl-0 = <&pinctrl_uart1>; 53 status = "okay"; 54}; 55 56&usdhc1 { 57 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 58 pinctrl-0 = <&pinctrl_usdhc1>; 59 pinctrl-1 = <&pinctrl_usdhc1>; 60 pinctrl-2 = <&pinctrl_usdhc1>; 61 bus-width = <8>; 62 non-removable; 63 status = "okay"; 64}; 65 66&usdhc2 { 67 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 68 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 69 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 70 pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 71 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 72 vmmc-supply = <®_usdhc2_vmmc>; 73 bus-width = <4>; 74 status = "okay"; 75 no-sdio; 76 no-mmc; 77}; 78 79&iomuxc { 80 pinctrl_uart1: uart1grp { 81 fsl,pins = < 82 MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 83 MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 84 >; 85 }; 86 87 pinctrl_usdhc1: usdhc1grp { 88 fsl,pins = < 89 MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe 90 MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe 91 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 92 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 93 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 94 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 95 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 96 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 97 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 98 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 99 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe 100 >; 101 }; 102 103 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 104 fsl,pins = < 105 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 106 >; 107 }; 108 109 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 110 fsl,pins = < 111 MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 112 >; 113 }; 114 115 pinctrl_usdhc2: usdhc2grp { 116 fsl,pins = < 117 MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe 118 MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe 119 MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 120 MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 121 MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 122 MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 123 MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 124 >; 125 }; 126}; 127