1e37907bdSPeng Fan// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2e37907bdSPeng Fan/* 3e37907bdSPeng Fan * Copyright 2022 NXP 4e37907bdSPeng Fan */ 5e37907bdSPeng Fan 6e37907bdSPeng Fan/dts-v1/; 7e37907bdSPeng Fan 8e37907bdSPeng Fan#include "imx93.dtsi" 9e37907bdSPeng Fan 10e37907bdSPeng Fan/ { 11e37907bdSPeng Fan model = "NXP i.MX93 11X11 EVK board"; 12e37907bdSPeng Fan compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; 13e37907bdSPeng Fan 14e37907bdSPeng Fan chosen { 15e37907bdSPeng Fan stdout-path = &lpuart1; 16e37907bdSPeng Fan }; 17e37907bdSPeng Fan 18fc94fbb9SPeng Fan reserved-memory { 19fc94fbb9SPeng Fan #address-cells = <2>; 20fc94fbb9SPeng Fan #size-cells = <2>; 21fc94fbb9SPeng Fan ranges; 22fc94fbb9SPeng Fan 23fc94fbb9SPeng Fan linux,cma { 24fc94fbb9SPeng Fan compatible = "shared-dma-pool"; 25fc94fbb9SPeng Fan reusable; 26fc94fbb9SPeng Fan alloc-ranges = <0 0x80000000 0 0x40000000>; 27fc94fbb9SPeng Fan size = <0 0x10000000>; 28fc94fbb9SPeng Fan linux,cma-default; 29fc94fbb9SPeng Fan }; 30*e1da7294SPeng Fan 31*e1da7294SPeng Fan vdev0vring0: vdev0vring0@a4000000 { 32*e1da7294SPeng Fan reg = <0 0xa4000000 0 0x8000>; 33*e1da7294SPeng Fan no-map; 34*e1da7294SPeng Fan }; 35*e1da7294SPeng Fan 36*e1da7294SPeng Fan vdev0vring1: vdev0vring1@a4008000 { 37*e1da7294SPeng Fan reg = <0 0xa4008000 0 0x8000>; 38*e1da7294SPeng Fan no-map; 39*e1da7294SPeng Fan }; 40*e1da7294SPeng Fan 41*e1da7294SPeng Fan vdev1vring0: vdev1vring0@a4000000 { 42*e1da7294SPeng Fan reg = <0 0xa4010000 0 0x8000>; 43*e1da7294SPeng Fan no-map; 44*e1da7294SPeng Fan }; 45*e1da7294SPeng Fan 46*e1da7294SPeng Fan vdev1vring1: vdev1vring1@a4018000 { 47*e1da7294SPeng Fan reg = <0 0xa4018000 0 0x8000>; 48*e1da7294SPeng Fan no-map; 49*e1da7294SPeng Fan }; 50*e1da7294SPeng Fan 51*e1da7294SPeng Fan rsc_table: rsc-table@2021f000 { 52*e1da7294SPeng Fan reg = <0 0x2021f000 0 0x1000>; 53*e1da7294SPeng Fan no-map; 54*e1da7294SPeng Fan }; 55*e1da7294SPeng Fan 56*e1da7294SPeng Fan vdevbuffer: vdevbuffer@a4020000 { 57*e1da7294SPeng Fan compatible = "shared-dma-pool"; 58*e1da7294SPeng Fan reg = <0 0xa4020000 0 0x100000>; 59*e1da7294SPeng Fan no-map; 60*e1da7294SPeng Fan }; 61*e1da7294SPeng Fan 62fc94fbb9SPeng Fan }; 63fc94fbb9SPeng Fan 645d11fe56SHaibo Chen reg_vref_1v8: regulator-adc-vref { 655d11fe56SHaibo Chen compatible = "regulator-fixed"; 665d11fe56SHaibo Chen regulator-name = "vref_1v8"; 675d11fe56SHaibo Chen regulator-min-microvolt = <1800000>; 685d11fe56SHaibo Chen regulator-max-microvolt = <1800000>; 695d11fe56SHaibo Chen }; 705d11fe56SHaibo Chen 71e37907bdSPeng Fan reg_usdhc2_vmmc: regulator-usdhc2 { 72e37907bdSPeng Fan compatible = "regulator-fixed"; 73e37907bdSPeng Fan pinctrl-names = "default"; 74e37907bdSPeng Fan pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 75e37907bdSPeng Fan regulator-name = "VSD_3V3"; 76e37907bdSPeng Fan regulator-min-microvolt = <3300000>; 77e37907bdSPeng Fan regulator-max-microvolt = <3300000>; 78e37907bdSPeng Fan gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 79e37907bdSPeng Fan enable-active-high; 80e37907bdSPeng Fan }; 81e37907bdSPeng Fan}; 82e37907bdSPeng Fan 835d11fe56SHaibo Chen&adc1 { 845d11fe56SHaibo Chen vref-supply = <®_vref_1v8>; 855d11fe56SHaibo Chen status = "okay"; 865d11fe56SHaibo Chen}; 875d11fe56SHaibo Chen 88*e1da7294SPeng Fan&cm33 { 89*e1da7294SPeng Fan mbox-names = "tx", "rx", "rxdb"; 90*e1da7294SPeng Fan mboxes = <&mu1 0 1>, 91*e1da7294SPeng Fan <&mu1 1 1>, 92*e1da7294SPeng Fan <&mu1 3 1>; 93*e1da7294SPeng Fan memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 94*e1da7294SPeng Fan <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 95*e1da7294SPeng Fan status = "okay"; 96*e1da7294SPeng Fan}; 97*e1da7294SPeng Fan 98e37907bdSPeng Fan&mu1 { 99e37907bdSPeng Fan status = "okay"; 100e37907bdSPeng Fan}; 101e37907bdSPeng Fan 102e37907bdSPeng Fan&mu2 { 103e37907bdSPeng Fan status = "okay"; 104e37907bdSPeng Fan}; 105e37907bdSPeng Fan 1061b110dd6SClark Wang&eqos { 1071b110dd6SClark Wang pinctrl-names = "default"; 1081b110dd6SClark Wang pinctrl-0 = <&pinctrl_eqos>; 1091b110dd6SClark Wang phy-mode = "rgmii-id"; 1101b110dd6SClark Wang phy-handle = <ðphy1>; 1111b110dd6SClark Wang status = "okay"; 1121b110dd6SClark Wang 1131b110dd6SClark Wang mdio { 1141b110dd6SClark Wang compatible = "snps,dwmac-mdio"; 1151b110dd6SClark Wang #address-cells = <1>; 1161b110dd6SClark Wang #size-cells = <0>; 1171b110dd6SClark Wang clock-frequency = <5000000>; 1181b110dd6SClark Wang 1191b110dd6SClark Wang ethphy1: ethernet-phy@1 { 1201b110dd6SClark Wang reg = <1>; 1211b110dd6SClark Wang eee-broken-1000t; 1221b110dd6SClark Wang }; 1231b110dd6SClark Wang }; 1241b110dd6SClark Wang}; 1251b110dd6SClark Wang 126c897dc7fSClark Wang&fec { 127c897dc7fSClark Wang pinctrl-names = "default"; 128c897dc7fSClark Wang pinctrl-0 = <&pinctrl_fec>; 129c897dc7fSClark Wang phy-mode = "rgmii-id"; 130c897dc7fSClark Wang phy-handle = <ðphy2>; 131c897dc7fSClark Wang fsl,magic-packet; 132c897dc7fSClark Wang status = "okay"; 133c897dc7fSClark Wang 134c897dc7fSClark Wang mdio { 135c897dc7fSClark Wang #address-cells = <1>; 136c897dc7fSClark Wang #size-cells = <0>; 137c897dc7fSClark Wang clock-frequency = <5000000>; 138c897dc7fSClark Wang 139c897dc7fSClark Wang ethphy2: ethernet-phy@2 { 140c897dc7fSClark Wang reg = <2>; 141c897dc7fSClark Wang eee-broken-1000t; 142c897dc7fSClark Wang }; 143c897dc7fSClark Wang }; 144c897dc7fSClark Wang}; 145c897dc7fSClark Wang 146e37907bdSPeng Fan&lpuart1 { /* console */ 147e37907bdSPeng Fan pinctrl-names = "default"; 148e37907bdSPeng Fan pinctrl-0 = <&pinctrl_uart1>; 149e37907bdSPeng Fan status = "okay"; 150e37907bdSPeng Fan}; 151e37907bdSPeng Fan 152e37907bdSPeng Fan&usdhc1 { 153e37907bdSPeng Fan pinctrl-names = "default", "state_100mhz", "state_200mhz"; 154e37907bdSPeng Fan pinctrl-0 = <&pinctrl_usdhc1>; 155e37907bdSPeng Fan pinctrl-1 = <&pinctrl_usdhc1>; 156e37907bdSPeng Fan pinctrl-2 = <&pinctrl_usdhc1>; 157e37907bdSPeng Fan bus-width = <8>; 158e37907bdSPeng Fan non-removable; 159e37907bdSPeng Fan status = "okay"; 160e37907bdSPeng Fan}; 161e37907bdSPeng Fan 162e37907bdSPeng Fan&usdhc2 { 163e37907bdSPeng Fan pinctrl-names = "default", "state_100mhz", "state_200mhz"; 164e37907bdSPeng Fan pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 165e37907bdSPeng Fan pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 166e37907bdSPeng Fan pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 167e37907bdSPeng Fan cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 168e37907bdSPeng Fan vmmc-supply = <®_usdhc2_vmmc>; 169e37907bdSPeng Fan bus-width = <4>; 170e37907bdSPeng Fan status = "okay"; 171e37907bdSPeng Fan no-mmc; 172e37907bdSPeng Fan}; 173e37907bdSPeng Fan 174b954d70aSPeng Fan&wdog3 { 175b954d70aSPeng Fan status = "okay"; 176b954d70aSPeng Fan}; 177b954d70aSPeng Fan 178e37907bdSPeng Fan&iomuxc { 1791b110dd6SClark Wang pinctrl_eqos: eqosgrp { 1801b110dd6SClark Wang fsl,pins = < 1811b110dd6SClark Wang MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 1821b110dd6SClark Wang MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 1831b110dd6SClark Wang MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 1841b110dd6SClark Wang MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 1851b110dd6SClark Wang MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 1861b110dd6SClark Wang MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 1871b110dd6SClark Wang MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe 1881b110dd6SClark Wang MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 1891b110dd6SClark Wang MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 1901b110dd6SClark Wang MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 1911b110dd6SClark Wang MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 1921b110dd6SClark Wang MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 1931b110dd6SClark Wang MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 1941b110dd6SClark Wang MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 1951b110dd6SClark Wang >; 1961b110dd6SClark Wang }; 1971b110dd6SClark Wang 198c897dc7fSClark Wang pinctrl_fec: fecgrp { 199c897dc7fSClark Wang fsl,pins = < 200c897dc7fSClark Wang MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e 201c897dc7fSClark Wang MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e 202c897dc7fSClark Wang MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e 203c897dc7fSClark Wang MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e 204c897dc7fSClark Wang MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e 205c897dc7fSClark Wang MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e 206c897dc7fSClark Wang MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe 207c897dc7fSClark Wang MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e 208c897dc7fSClark Wang MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e 209c897dc7fSClark Wang MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e 210c897dc7fSClark Wang MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e 211c897dc7fSClark Wang MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e 212c897dc7fSClark Wang MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe 213c897dc7fSClark Wang MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e 214c897dc7fSClark Wang >; 215c897dc7fSClark Wang }; 216c897dc7fSClark Wang 217e37907bdSPeng Fan pinctrl_uart1: uart1grp { 218e37907bdSPeng Fan fsl,pins = < 219e37907bdSPeng Fan MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 220e37907bdSPeng Fan MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 221e37907bdSPeng Fan >; 222e37907bdSPeng Fan }; 223e37907bdSPeng Fan 224e37907bdSPeng Fan pinctrl_usdhc1: usdhc1grp { 225e37907bdSPeng Fan fsl,pins = < 22662f0147fSHaibo Chen MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 227e37907bdSPeng Fan MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe 228e37907bdSPeng Fan MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 229e37907bdSPeng Fan MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 230e37907bdSPeng Fan MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 231e37907bdSPeng Fan MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 232e37907bdSPeng Fan MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 233e37907bdSPeng Fan MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 234e37907bdSPeng Fan MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 235e37907bdSPeng Fan MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 23662f0147fSHaibo Chen MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 237e37907bdSPeng Fan >; 238e37907bdSPeng Fan }; 239e37907bdSPeng Fan 240e37907bdSPeng Fan pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 241e37907bdSPeng Fan fsl,pins = < 242e37907bdSPeng Fan MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 243e37907bdSPeng Fan >; 244e37907bdSPeng Fan }; 245e37907bdSPeng Fan 246e37907bdSPeng Fan pinctrl_usdhc2_gpio: usdhc2gpiogrp { 247e37907bdSPeng Fan fsl,pins = < 248e37907bdSPeng Fan MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 249e37907bdSPeng Fan >; 250e37907bdSPeng Fan }; 251e37907bdSPeng Fan 252e37907bdSPeng Fan pinctrl_usdhc2: usdhc2grp { 253e37907bdSPeng Fan fsl,pins = < 25462f0147fSHaibo Chen MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 255e37907bdSPeng Fan MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe 256e37907bdSPeng Fan MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 257e37907bdSPeng Fan MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 258e37907bdSPeng Fan MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 259e37907bdSPeng Fan MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 260e37907bdSPeng Fan MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 261e37907bdSPeng Fan >; 262e37907bdSPeng Fan }; 263e37907bdSPeng Fan}; 264