1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2019 Toradex 4 */ 5 6/ { 7 chosen { 8 stdout-path = &lpuart3; 9 }; 10 11 colibri_gpio_keys: gpio-keys { 12 compatible = "gpio-keys"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_gpiokeys>; 15 status = "disabled"; 16 17 key-wakeup { 18 debounce-interval = <10>; 19 gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; 20 label = "Wake-Up"; 21 linux,code = <KEY_WAKEUP>; 22 wakeup-source; 23 }; 24 }; 25 26 reg_module_3v3: regulator-module-3v3 { 27 compatible = "regulator-fixed"; 28 regulator-name = "+V3.3"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 }; 32}; 33 34&cpu_alert0 { 35 hysteresis = <2000>; 36 temperature = <90000>; 37 type = "passive"; 38}; 39 40&cpu_crit0 { 41 hysteresis = <2000>; 42 temperature = <105000>; 43 type = "critical"; 44}; 45 46/* On-module I2C */ 47&i2c0 { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 clock-frequency = <100000>; 51 pinctrl-names = "default"; 52 pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; 53 status = "okay"; 54 55 /* Touch controller */ 56 touchscreen@2c { 57 compatible = "adi,ad7879-1"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_ad7879_int>; 60 reg = <0x2c>; 61 interrupt-parent = <&lsio_gpio3>; 62 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 63 touchscreen-max-pressure = <4096>; 64 adi,resistance-plate-x = <120>; 65 adi,first-conversion-delay = /bits/ 8 <3>; 66 adi,acquisition-time = /bits/ 8 <1>; 67 adi,median-filter-size = /bits/ 8 <2>; 68 adi,averaging = /bits/ 8 <1>; 69 adi,conversion-interval = /bits/ 8 <255>; 70 status = "disabled"; 71 }; 72}; 73 74/* Colibri I2C */ 75&i2c1 { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 clock-frequency = <100000>; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_i2c1>; 81}; 82 83&jpegdec { 84 status = "okay"; 85}; 86 87&jpegenc { 88 status = "okay"; 89}; 90 91/* Colibri UART_B */ 92&lpuart0 { 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_lpuart0>; 95}; 96 97/* Colibri UART_C */ 98&lpuart2 { 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_lpuart2>; 101}; 102 103/* Colibri UART_A */ 104&lpuart3 { 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; 107}; 108 109/* Colibri FastEthernet */ 110&fec1 { 111 pinctrl-names = "default", "sleep"; 112 pinctrl-0 = <&pinctrl_fec1>; 113 pinctrl-1 = <&pinctrl_fec1_sleep>; 114 phy-mode = "rmii"; 115 phy-handle = <ðphy0>; 116 fsl,magic-packet; 117 118 mdio { 119 #address-cells = <1>; 120 #size-cells = <0>; 121 122 ethphy0: ethernet-phy@2 { 123 compatible = "ethernet-phy-ieee802.3-c22"; 124 max-speed = <100>; 125 reg = <2>; 126 }; 127 }; 128}; 129 130/* Colibri SPI */ 131&lpspi2 { 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_lpspi2>; 134 cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; 135}; 136 137&lsio_gpio0 { 138 gpio-line-names = "", 139 "SODIMM_70", 140 "SODIMM_60", 141 "SODIMM_58", 142 "SODIMM_78", 143 "SODIMM_72", 144 "SODIMM_80", 145 "SODIMM_46", 146 "SODIMM_62", 147 "SODIMM_48", 148 "SODIMM_74", 149 "SODIMM_50", 150 "SODIMM_52", 151 "SODIMM_54", 152 "SODIMM_66", 153 "SODIMM_64", 154 "SODIMM_68", 155 "", 156 "", 157 "SODIMM_82", 158 "SODIMM_56", 159 "SODIMM_28", 160 "SODIMM_30", 161 "", 162 "SODIMM_61", 163 "SODIMM_103", 164 "", 165 "", 166 "", 167 "SODIMM_25", 168 "SODIMM_27", 169 "SODIMM_100"; 170}; 171 172&lsio_gpio1 { 173 gpio-line-names = "SODIMM_86", 174 "SODIMM_92", 175 "SODIMM_90", 176 "SODIMM_88", 177 "", 178 "", 179 "", 180 "SODIMM_59", 181 "", 182 "SODIMM_6", 183 "SODIMM_8", 184 "", 185 "", 186 "SODIMM_2", 187 "SODIMM_4", 188 "SODIMM_34", 189 "SODIMM_32", 190 "SODIMM_63", 191 "SODIMM_55", 192 "SODIMM_33", 193 "SODIMM_35", 194 "SODIMM_36", 195 "SODIMM_38", 196 "SODIMM_21", 197 "SODIMM_19", 198 "SODIMM_140", 199 "SODIMM_142", 200 "SODIMM_196", 201 "SODIMM_194", 202 "SODIMM_186", 203 "SODIMM_188", 204 "SODIMM_138"; 205}; 206 207&lsio_gpio2 { 208 gpio-line-names = "SODIMM_23", 209 "", 210 "", 211 "SODIMM_144"; 212}; 213 214&lsio_gpio3 { 215 gpio-line-names = "SODIMM_96", 216 "SODIMM_75", 217 "SODIMM_37", 218 "SODIMM_29", 219 "", 220 "", 221 "", 222 "", 223 "", 224 "SODIMM_43", 225 "SODIMM_45", 226 "SODIMM_69", 227 "SODIMM_71", 228 "SODIMM_73", 229 "SODIMM_77", 230 "SODIMM_89", 231 "SODIMM_93", 232 "SODIMM_95", 233 "SODIMM_99", 234 "SODIMM_105", 235 "SODIMM_107", 236 "SODIMM_98", 237 "SODIMM_102", 238 "SODIMM_104", 239 "SODIMM_106"; 240}; 241 242&lsio_gpio4 { 243 gpio-line-names = "", 244 "", 245 "", 246 "SODIMM_129", 247 "SODIMM_133", 248 "SODIMM_127", 249 "SODIMM_131", 250 "", 251 "", 252 "", 253 "", 254 "", 255 "", 256 "", 257 "", 258 "", 259 "", 260 "", 261 "", 262 "SODIMM_44", 263 "", 264 "SODIMM_76", 265 "SODIMM_31", 266 "SODIMM_47", 267 "SODIMM_190", 268 "SODIMM_192", 269 "SODIMM_49", 270 "SODIMM_51", 271 "SODIMM_53"; 272}; 273 274&lsio_gpio5 { 275 gpio-line-names = "", 276 "SODIMM_57", 277 "SODIMM_65", 278 "SODIMM_85", 279 "", 280 "", 281 "", 282 "", 283 "SODIMM_135", 284 "SODIMM_137", 285 "UNUSABLE_SODIMM_180", 286 "UNUSABLE_SODIMM_184"; 287}; 288 289/* Colibri PWM_B */ 290&lsio_pwm0 { 291 #pwm-cells = <3>; 292 pinctrl-0 = <&pinctrl_pwm_b>; 293 pinctrl-names = "default"; 294}; 295 296/* Colibri PWM_C */ 297&lsio_pwm1 { 298 #pwm-cells = <3>; 299 pinctrl-0 = <&pinctrl_pwm_c>; 300 pinctrl-names = "default"; 301}; 302 303/* Colibri PWM_D */ 304&lsio_pwm2 { 305 #pwm-cells = <3>; 306 pinctrl-0 = <&pinctrl_pwm_d>; 307 pinctrl-names = "default"; 308}; 309 310/* On-module eMMC */ 311&usdhc1 { 312 bus-width = <8>; 313 non-removable; 314 no-sd; 315 no-sdio; 316 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 317 pinctrl-0 = <&pinctrl_usdhc1>; 318 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 319 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 320 status = "okay"; 321}; 322 323/* Colibri SD/MMC Card */ 324&usdhc2 { 325 bus-width = <4>; 326 cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; 327 vmmc-supply = <®_module_3v3>; 328 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 329 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 330 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 331 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 332 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 333 disable-wp; 334 no-1-8-v; 335}; 336 337&iomuxc { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>, 340 <&pinctrl_hog2>, <&pinctrl_lpspi2_cs2>; 341 342 /* On-module touch pen-down interrupt */ 343 pinctrl_ad7879_int: ad7879intgrp { 344 fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21>; 345 }; 346 347 /* Colibri Analogue Inputs */ 348 pinctrl_adc0: adc0grp { 349 fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60>, /* SODIMM 8 */ 350 <IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60>, /* SODIMM 6 */ 351 <IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60>, /* SODIMM 4 */ 352 <IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60>; /* SODIMM 2 */ 353 }; 354 355 /* Atmel MXT touchsceen + Capacitive Touch Adapter */ 356 /* NOTE: This pingroup conflicts with pingroups 357 * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them 358 * simultaneously. 359 */ 360 pinctrl_atmel_adap: atmeladaptergrp { 361 fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21>, /* SODIMM 30 */ 362 <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021>; /* SODIMM 28 */ 363 }; 364 365 /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ 366 pinctrl_atmel_conn: atmelconnectorgrp { 367 fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021>, /* SODIMM 107 */ 368 <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21>; /* SODIMM 106 */ 369 }; 370 371 pinctrl_can_int: canintgrp { 372 fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40>; /* SODIMM 73 */ 373 }; 374 375 pinctrl_csi_ctl: csictlgrp { 376 fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20>, /* SODIMM 77 */ 377 <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20>; /* SODIMM 89 */ 378 }; 379 380 pinctrl_csi_mclk: csimclkgrp { 381 fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041>; /* SODIMM 75 / X3-12 */ 382 }; 383 384 pinctrl_ext_io0: extio0grp { 385 fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040>; /* SODIMM 135 */ 386 }; 387 388 /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ 389 pinctrl_fec1: fec1grp { 390 fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020>, 391 <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>, 392 <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61>, 393 <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061>, 394 <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61>, 395 <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61>, 396 <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61>, 397 <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61>, 398 <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61>, 399 <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61>; 400 }; 401 402 pinctrl_fec1_sleep: fec1slpgrp { 403 fsl,pins = <IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041>, 404 <IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041>, 405 <IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41>, 406 <IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41>, 407 <IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41>, 408 <IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41>, 409 <IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41>, 410 <IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41>, 411 <IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41>, 412 <IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41>; 413 }; 414 415 /* Colibri optional CAN on UART_B RTS/CTS */ 416 pinctrl_flexcan1: flexcan0grp { 417 fsl,pins = <IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21>, /* SODIMM 32 */ 418 <IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21>; /* SODIMM 34 */ 419 }; 420 421 /* Colibri optional CAN on PS2 */ 422 pinctrl_flexcan2: flexcan1grp { 423 fsl,pins = <IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21>, /* SODIMM 55 */ 424 <IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21>; /* SODIMM 63 */ 425 }; 426 427 /* Colibri optional CAN on UART_A TXD/RXD */ 428 pinctrl_flexcan3: flexcan2grp { 429 fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21>, /* SODIMM 35 */ 430 <IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21>; /* SODIMM 33 */ 431 }; 432 433 /* Colibri LCD Back-Light GPIO */ 434 pinctrl_gpio_bl_on: gpioblongrp { 435 fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60>; /* SODIMM 71 */ 436 }; 437 438 /* HDMI Hot Plug Detect on FFC (X2) */ 439 pinctrl_gpio_hpd: gpiohpdgrp { 440 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20>; /* SODIMM 138 */ 441 }; 442 443 pinctrl_gpiokeys: gpiokeysgrp { 444 fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */ 445 }; 446 447 pinctrl_hog0: hog0grp { 448 fsl,pins = <IMX8QXP_CSI_D07_CI_PI_D09 0x61>, /* SODIMM 65 */ 449 <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20>, /* SODIMM 69 */ 450 <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */ 451 <IMX8QXP_CSI_D02_CI_PI_D04 0x61>, /* SODIMM 79 */ 452 <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */ 453 <IMX8QXP_CSI_D06_CI_PI_D08 0x61>, /* SODIMM 85 */ 454 <IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */ 455 <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */ 456 <IMX8QXP_CSI_D03_CI_PI_D05 0x61>, /* SODIMM 97 */ 457 <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>, /* SODIMM 99 */ 458 <IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */ 459 <IMX8QXP_CSI_D00_CI_PI_D02 0x61>, /* SODIMM 101 */ 460 <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */ 461 <IMX8QXP_CSI_D01_CI_PI_D03 0x61>, /* SODIMM 103 */ 462 <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20>, /* SODIMM 105 */ 463 <IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20>, /* SODIMM 127 */ 464 <IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20>, /* SODIMM 131 */ 465 <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20>, /* SODIMM 133 */ 466 <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20>, /* SODIMM 96 */ 467 <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */ 468 <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>, /* SODIMM 100 */ 469 <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20>, /* SODIMM 102 */ 470 <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20>; /* SODIMM 104 */ 471 }; 472 473 pinctrl_hog1: hog1grp { 474 fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>, /* SODIMM 75 */ 475 <IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20>; /* SODIMM 93 */ 476 }; 477 478 pinctrl_hog2: hog2grp { 479 fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>; /* SODIMM 75 */ 480 }; 481 482 /* 483 * This pin is used in the SCFW as a UART. Using it from 484 * Linux would require rewritting the SCFW board file. 485 */ 486 pinctrl_hog_scfw: hogscfwgrp { 487 fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20>; /* SODIMM 144 */ 488 }; 489 490 /* On Module I2C */ 491 pinctrl_i2c0: i2c0grp { 492 fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021>, 493 <IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021>; 494 }; 495 496 /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ 497 pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp { 498 fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020>, /* SODIMM 140 */ 499 <IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020>; /* SODIMM 142 */ 500 }; 501 502 /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ 503 pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp { 504 fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020>, /* SODIMM 186 */ 505 <IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020>; /* SODIMM 188 */ 506 }; 507 508 /* Colibri I2C */ 509 pinctrl_i2c1: i2c1grp { 510 fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021>, /* SODIMM 196 */ 511 <IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021>; /* SODIMM 194 */ 512 }; 513 514 /* Colibri Parallel RGB LCD Interface */ 515 pinctrl_lcdif: lcdifgrp { 516 fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60>, /* SODIMM 56 */ 517 <IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60>, /* SODIMM 68 */ 518 <IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60>, /* SODIMM 82 */ 519 <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x40>, /* SODIMM 44 */ 520 <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x40>, /* SODIMM 44 */ 521 <IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60>, /* SODIMM 76 */ 522 <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60>, /* SODIMM 76 */ 523 <IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60>, /* SODIMM 70 */ 524 <IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60>, /* SODIMM 60 */ 525 <IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60>, /* SODIMM 58 */ 526 <IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60>, /* SODIMM 78 */ 527 <IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60>, /* SODIMM 72 */ 528 <IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60>, /* SODIMM 80 */ 529 <IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60>, /* SODIMM 46 */ 530 <IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60>, /* SODIMM 62 */ 531 <IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60>, /* SODIMM 48 */ 532 <IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60>, /* SODIMM 74 */ 533 <IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60>, /* SODIMM 50 */ 534 <IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60>, /* SODIMM 52 */ 535 <IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60>, /* SODIMM 54 */ 536 <IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60>, /* SODIMM 66 */ 537 <IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60>, /* SODIMM 64 */ 538 <IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60>, /* SODIMM 57 */ 539 <IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60>, /* SODIMM 57 */ 540 <IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60>; /* SODIMM 61 */ 541 }; 542 543 /* Colibri SPI */ 544 pinctrl_lpspi2: lpspi2grp { 545 fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21>, /* SODIMM 86 */ 546 <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040>, /* SODIMM 92 */ 547 <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040>, /* SODIMM 90 */ 548 <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040>; /* SODIMM 88 */ 549 }; 550 551 pinctrl_lpspi2_cs2: lpspi2cs2grp { 552 fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21>; /* SODIMM 65 */ 553 }; 554 555 /* Colibri UART_B */ 556 pinctrl_lpuart0: lpuart0grp { 557 fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020>, /* SODIMM 36 */ 558 <IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020>, /* SODIMM 38 */ 559 <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020>, /* SODIMM 34 */ 560 <IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020>; /* SODIMM 32 */ 561 }; 562 563 /* Colibri UART_C */ 564 pinctrl_lpuart2: lpuart2grp { 565 fsl,pins = <IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020>, /* SODIMM 19 */ 566 <IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020>; /* SODIMM 21 */ 567 }; 568 569 /* Colibri UART_A */ 570 pinctrl_lpuart3: lpuart3grp { 571 fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>, /* SODIMM 33 */ 572 <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>; /* SODIMM 35 */ 573 }; 574 575 /* Colibri UART_A Control */ 576 pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { 577 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20>, /* SODIMM 23 */ 578 <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20>, /* SODIMM 25 */ 579 <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20>, /* SODIMM 27 */ 580 <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20>, /* SODIMM 29 */ 581 <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20>, /* SODIMM 31 */ 582 <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20>; /* SODIMM 37 */ 583 }; 584 585 /* On module wifi module */ 586 pinctrl_pcieb: pciebgrp { 587 fsl,pins = <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061>, /* SODIMM 178 */ 588 <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061>, /* SODIMM 94 */ 589 <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60>; /* SODIMM 81 */ 590 }; 591 592 /* Colibri PWM_A */ 593 pinctrl_pwm_a: pwmagrp { 594 /* both pins are connected together, reserve the unused CSI_D05 */ 595 fsl,pins = <IMX8QXP_CSI_D05_CI_PI_D07 0x61>, /* SODIMM 59 */ 596 <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60>; /* SODIMM 59 */ 597 }; 598 599 /* Colibri PWM_B */ 600 pinctrl_pwm_b: pwmbgrp { 601 fsl,pins = <IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60>; /* SODIMM 28 */ 602 }; 603 604 /* Colibri PWM_C */ 605 pinctrl_pwm_c: pwmcgrp { 606 fsl,pins = <IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60>; /* SODIMM 30 */ 607 }; 608 609 /* Colibri PWM_D */ 610 pinctrl_pwm_d: pwmdgrp { 611 /* both pins are connected together, reserve the unused CSI_D04 */ 612 fsl,pins = <IMX8QXP_CSI_D04_CI_PI_D06 0x61>, /* SODIMM 67 */ 613 <IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60>; /* SODIMM 67 */ 614 }; 615 616 /* On-module I2S */ 617 pinctrl_sai0: sai0grp { 618 fsl,pins = <IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040>, 619 <IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040>, 620 <IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040>, 621 <IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040>; 622 }; 623 624 /* Colibri Audio Analogue Microphone GND */ 625 pinctrl_sgtl5000: sgtl5000grp { 626 fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41>; 627 }; 628 629 /* On-module SGTL5000 clock */ 630 pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp { 631 fsl,pins = <IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21>; 632 }; 633 634 /* On-module USB interrupt */ 635 pinctrl_usb3503a: usb3503agrp { 636 fsl,pins = <IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61>; 637 }; 638 639 /* Colibri USB Client Cable Detect */ 640 pinctrl_usbc_det: usbcdetgrp { 641 fsl,pins = <IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040>; /* SODIMM 137 */ 642 }; 643 644 /* USB Host Power Enable */ 645 pinctrl_usbh1_reg: usbh1reggrp { 646 fsl,pins = <IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040>; /* SODIMM 129 */ 647 }; 648 649 /* On-module eMMC */ 650 pinctrl_usdhc1: usdhc1grp { 651 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 652 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>, 653 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>, 654 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>, 655 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>, 656 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>, 657 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>, 658 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>, 659 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>, 660 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>, 661 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>, 662 <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>; 663 }; 664 665 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 666 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 667 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>, 668 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>, 669 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>, 670 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>, 671 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>, 672 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>, 673 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>, 674 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>, 675 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>, 676 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>, 677 <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>; 678 }; 679 680 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 681 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 682 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>, 683 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>, 684 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>, 685 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>, 686 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>, 687 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>, 688 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>, 689 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>, 690 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>, 691 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>, 692 <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>; 693 }; 694 695 /* Colibri SD/MMC Card Detect */ 696 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 697 fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021>; /* SODIMM 43 */ 698 }; 699 700 pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { 701 fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60>; /* SODIMM 43 */ 702 }; 703 704 /* Colibri SD/MMC Card */ 705 pinctrl_usdhc2: usdhc2grp { 706 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */ 707 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */ 708 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */ 709 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */ 710 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */ 711 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */ 712 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>; 713 }; 714 715 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 716 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */ 717 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */ 718 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */ 719 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */ 720 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */ 721 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */ 722 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>; 723 }; 724 725 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 726 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */ 727 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */ 728 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */ 729 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */ 730 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */ 731 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */ 732 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>; 733 }; 734 735 pinctrl_usdhc2_sleep: usdhc2slpgrp { 736 fsl,pins = <IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60>, /* SODIMM 47 */ 737 <IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60>, /* SODIMM 190 */ 738 <IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60>, /* SODIMM 192 */ 739 <IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60>, /* SODIMM 49 */ 740 <IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60>, /* SODIMM 51 */ 741 <IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60>, /* SODIMM 53 */ 742 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>; 743 }; 744 745 pinctrl_wifi: wifigrp { 746 fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20>; 747 }; 748}; 749