1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8ulp.dtsi"
9
10/ {
11	model = "NXP i.MX8ULP EVK";
12	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
13
14	chosen {
15		stdout-path = &lpuart5;
16	};
17
18	memory@80000000 {
19		device_type = "memory";
20		reg = <0x0 0x80000000 0 0x80000000>;
21	};
22
23	clock_ext_rmii: clock-ext-rmii {
24		compatible = "fixed-clock";
25		clock-frequency = <50000000>;
26		clock-output-names = "ext_rmii_clk";
27		#clock-cells = <0>;
28	};
29
30	clock_ext_ts: clock-ext-ts {
31		compatible = "fixed-clock";
32		/* External ts clock is 50MHZ from PHY on EVK board. */
33		clock-frequency = <50000000>;
34		clock-output-names = "ext_ts_clk";
35		#clock-cells = <0>;
36	};
37};
38
39&lpuart5 {
40	/* console */
41	pinctrl-names = "default", "sleep";
42	pinctrl-0 = <&pinctrl_lpuart5>;
43	pinctrl-1 = <&pinctrl_lpuart5>;
44	status = "okay";
45};
46
47&usdhc0 {
48	pinctrl-names = "default", "sleep";
49	pinctrl-0 = <&pinctrl_usdhc0>;
50	pinctrl-1 = <&pinctrl_usdhc0>;
51	non-removable;
52	bus-width = <8>;
53	status = "okay";
54};
55
56&fec {
57	pinctrl-names = "default", "sleep";
58	pinctrl-0 = <&pinctrl_enet>;
59	pinctrl-1 = <&pinctrl_enet>;
60	clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
61		 <&pcc4 IMX8ULP_CLK_ENET>,
62		 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
63		 <&clock_ext_rmii>;
64	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
65	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
66	assigned-clock-parents = <&clock_ext_ts>;
67	phy-mode = "rmii";
68	phy-handle = <&ethphy>;
69	status = "okay";
70
71	mdio {
72		#address-cells = <1>;
73		#size-cells = <0>;
74
75		ethphy: ethernet-phy@1 {
76			reg = <1>;
77			micrel,led-mode = <1>;
78		};
79	};
80};
81
82&iomuxc1 {
83	pinctrl_enet: enetgrp {
84		fsl,pins = <
85			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
86			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
87			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
88			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
89			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
90			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
91			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
92			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
93			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
94			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
95			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
96		>;
97	};
98
99	pinctrl_lpuart5: lpuart5grp {
100		fsl,pins = <
101			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
102			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
103		>;
104	};
105
106	pinctrl_usdhc0: usdhc0grp {
107		fsl,pins = <
108			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
109			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
110			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
111			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
112			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
113			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
114			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
115			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
116			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
117			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
118			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
119		>;
120	};
121};
122