1*a6e917b7SJacky Bai// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*a6e917b7SJacky Bai/* 3*a6e917b7SJacky Bai * Copyright 2021 NXP 4*a6e917b7SJacky Bai */ 5*a6e917b7SJacky Bai 6*a6e917b7SJacky Bai/dts-v1/; 7*a6e917b7SJacky Bai 8*a6e917b7SJacky Bai#include "imx8ulp.dtsi" 9*a6e917b7SJacky Bai 10*a6e917b7SJacky Bai/ { 11*a6e917b7SJacky Bai model = "NXP i.MX8ULP EVK"; 12*a6e917b7SJacky Bai compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; 13*a6e917b7SJacky Bai 14*a6e917b7SJacky Bai chosen { 15*a6e917b7SJacky Bai stdout-path = &lpuart5; 16*a6e917b7SJacky Bai }; 17*a6e917b7SJacky Bai 18*a6e917b7SJacky Bai memory@80000000 { 19*a6e917b7SJacky Bai device_type = "memory"; 20*a6e917b7SJacky Bai reg = <0x0 0x80000000 0 0x80000000>; 21*a6e917b7SJacky Bai }; 22*a6e917b7SJacky Bai}; 23*a6e917b7SJacky Bai 24*a6e917b7SJacky Bai&lpuart5 { 25*a6e917b7SJacky Bai /* console */ 26*a6e917b7SJacky Bai pinctrl-names = "default", "sleep"; 27*a6e917b7SJacky Bai pinctrl-0 = <&pinctrl_lpuart5>; 28*a6e917b7SJacky Bai pinctrl-1 = <&pinctrl_lpuart5>; 29*a6e917b7SJacky Bai status = "okay"; 30*a6e917b7SJacky Bai}; 31*a6e917b7SJacky Bai 32*a6e917b7SJacky Bai&usdhc0 { 33*a6e917b7SJacky Bai pinctrl-names = "default", "sleep"; 34*a6e917b7SJacky Bai pinctrl-0 = <&pinctrl_usdhc0>; 35*a6e917b7SJacky Bai pinctrl-1 = <&pinctrl_usdhc0>; 36*a6e917b7SJacky Bai non-removable; 37*a6e917b7SJacky Bai bus-width = <8>; 38*a6e917b7SJacky Bai status = "okay"; 39*a6e917b7SJacky Bai}; 40*a6e917b7SJacky Bai 41*a6e917b7SJacky Bai&iomuxc1 { 42*a6e917b7SJacky Bai pinctrl_lpuart5: lpuart5grp { 43*a6e917b7SJacky Bai fsl,pins = < 44*a6e917b7SJacky Bai MX8ULP_PAD_PTF14__LPUART5_TX 0x3 45*a6e917b7SJacky Bai MX8ULP_PAD_PTF15__LPUART5_RX 0x3 46*a6e917b7SJacky Bai >; 47*a6e917b7SJacky Bai }; 48*a6e917b7SJacky Bai 49*a6e917b7SJacky Bai pinctrl_usdhc0: usdhc0grp { 50*a6e917b7SJacky Bai fsl,pins = < 51*a6e917b7SJacky Bai MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 52*a6e917b7SJacky Bai MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 53*a6e917b7SJacky Bai MX8ULP_PAD_PTD10__SDHC0_D0 0x43 54*a6e917b7SJacky Bai MX8ULP_PAD_PTD9__SDHC0_D1 0x43 55*a6e917b7SJacky Bai MX8ULP_PAD_PTD8__SDHC0_D2 0x43 56*a6e917b7SJacky Bai MX8ULP_PAD_PTD7__SDHC0_D3 0x43 57*a6e917b7SJacky Bai MX8ULP_PAD_PTD6__SDHC0_D4 0x43 58*a6e917b7SJacky Bai MX8ULP_PAD_PTD5__SDHC0_D5 0x43 59*a6e917b7SJacky Bai MX8ULP_PAD_PTD4__SDHC0_D6 0x43 60*a6e917b7SJacky Bai MX8ULP_PAD_PTD3__SDHC0_D7 0x43 61*a6e917b7SJacky Bai MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 62*a6e917b7SJacky Bai >; 63*a6e917b7SJacky Bai }; 64*a6e917b7SJacky Bai}; 65