1a6e917b7SJacky Bai// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2a6e917b7SJacky Bai/* 3a6e917b7SJacky Bai * Copyright 2021 NXP 4a6e917b7SJacky Bai */ 5a6e917b7SJacky Bai 6a6e917b7SJacky Bai/dts-v1/; 7a6e917b7SJacky Bai 8a6e917b7SJacky Bai#include "imx8ulp.dtsi" 9a6e917b7SJacky Bai 10a6e917b7SJacky Bai/ { 11a6e917b7SJacky Bai model = "NXP i.MX8ULP EVK"; 12a6e917b7SJacky Bai compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; 13a6e917b7SJacky Bai 14a6e917b7SJacky Bai chosen { 15a6e917b7SJacky Bai stdout-path = &lpuart5; 16a6e917b7SJacky Bai }; 17a6e917b7SJacky Bai 18a6e917b7SJacky Bai memory@80000000 { 19a6e917b7SJacky Bai device_type = "memory"; 20a6e917b7SJacky Bai reg = <0x0 0x80000000 0 0x80000000>; 21a6e917b7SJacky Bai }; 221170826eSWei Fang 23d0da51bbSPeng Fan reserved-memory { 24d0da51bbSPeng Fan #address-cells = <2>; 25d0da51bbSPeng Fan #size-cells = <2>; 26d0da51bbSPeng Fan ranges; 27d0da51bbSPeng Fan 28d0da51bbSPeng Fan linux,cma { 29d0da51bbSPeng Fan compatible = "shared-dma-pool"; 30d0da51bbSPeng Fan reusable; 31d0da51bbSPeng Fan size = <0 0x28000000>; 32d0da51bbSPeng Fan linux,cma-default; 33d0da51bbSPeng Fan }; 34014fbffaSPeng Fan 35014fbffaSPeng Fan m33_reserved: noncacheable-section@a8600000 { 36014fbffaSPeng Fan reg = <0 0xa8600000 0 0x1000000>; 37014fbffaSPeng Fan no-map; 38014fbffaSPeng Fan }; 39014fbffaSPeng Fan 40014fbffaSPeng Fan rsc_table: rsc-table@1fff8000{ 41014fbffaSPeng Fan reg = <0 0x1fff8000 0 0x1000>; 42014fbffaSPeng Fan no-map; 43014fbffaSPeng Fan }; 44014fbffaSPeng Fan 45014fbffaSPeng Fan vdev0vring0: vdev0vring0@aff00000 { 46014fbffaSPeng Fan reg = <0 0xaff00000 0 0x8000>; 47014fbffaSPeng Fan no-map; 48014fbffaSPeng Fan }; 49014fbffaSPeng Fan 50014fbffaSPeng Fan vdev0vring1: vdev0vring1@aff08000 { 51014fbffaSPeng Fan reg = <0 0xaff08000 0 0x8000>; 52014fbffaSPeng Fan no-map; 53014fbffaSPeng Fan }; 54014fbffaSPeng Fan 55014fbffaSPeng Fan vdev1vring0: vdev1vring0@aff10000 { 56014fbffaSPeng Fan reg = <0 0xaff10000 0 0x8000>; 57014fbffaSPeng Fan no-map; 58014fbffaSPeng Fan }; 59014fbffaSPeng Fan 60014fbffaSPeng Fan vdev1vring1: vdev1vring1@aff18000 { 61014fbffaSPeng Fan reg = <0 0xaff18000 0 0x8000>; 62014fbffaSPeng Fan no-map; 63014fbffaSPeng Fan }; 64014fbffaSPeng Fan 65014fbffaSPeng Fan vdevbuffer: vdevbuffer@a8400000 { 66014fbffaSPeng Fan compatible = "shared-dma-pool"; 67014fbffaSPeng Fan reg = <0 0xa8400000 0 0x100000>; 68014fbffaSPeng Fan no-map; 69014fbffaSPeng Fan }; 70d0da51bbSPeng Fan }; 71d0da51bbSPeng Fan 721170826eSWei Fang clock_ext_rmii: clock-ext-rmii { 731170826eSWei Fang compatible = "fixed-clock"; 741170826eSWei Fang clock-frequency = <50000000>; 751170826eSWei Fang clock-output-names = "ext_rmii_clk"; 761170826eSWei Fang #clock-cells = <0>; 771170826eSWei Fang }; 781170826eSWei Fang 791170826eSWei Fang clock_ext_ts: clock-ext-ts { 801170826eSWei Fang compatible = "fixed-clock"; 811170826eSWei Fang /* External ts clock is 50MHZ from PHY on EVK board. */ 821170826eSWei Fang clock-frequency = <50000000>; 831170826eSWei Fang clock-output-names = "ext_ts_clk"; 841170826eSWei Fang #clock-cells = <0>; 851170826eSWei Fang }; 86a6e917b7SJacky Bai}; 87a6e917b7SJacky Bai 88014fbffaSPeng Fan&cm33 { 89014fbffaSPeng Fan mbox-names = "tx", "rx", "rxdb"; 90014fbffaSPeng Fan mboxes = <&mu 0 1>, 91014fbffaSPeng Fan <&mu 1 1>, 92014fbffaSPeng Fan <&mu 3 1>; 93014fbffaSPeng Fan memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 94014fbffaSPeng Fan <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 95014fbffaSPeng Fan status = "okay"; 96014fbffaSPeng Fan}; 97014fbffaSPeng Fan 983d256330SHan Xu&flexspi2 { 993d256330SHan Xu pinctrl-names = "default", "sleep"; 1003d256330SHan Xu pinctrl-0 = <&pinctrl_flexspi2_ptd>; 1013d256330SHan Xu pinctrl-1 = <&pinctrl_flexspi2_ptd>; 1023d256330SHan Xu status = "okay"; 1033d256330SHan Xu 1043d256330SHan Xu mx25uw51345gxdi00: flash@0 { 1053d256330SHan Xu compatible = "jedec,spi-nor"; 1063d256330SHan Xu reg = <0>; 1073d256330SHan Xu spi-max-frequency = <200000000>; 1083d256330SHan Xu spi-tx-bus-width = <8>; 1093d256330SHan Xu spi-rx-bus-width = <8>; 1103d256330SHan Xu }; 1113d256330SHan Xu}; 1123d256330SHan Xu 113a6e917b7SJacky Bai&lpuart5 { 114a6e917b7SJacky Bai /* console */ 115a6e917b7SJacky Bai pinctrl-names = "default", "sleep"; 116a6e917b7SJacky Bai pinctrl-0 = <&pinctrl_lpuart5>; 117a6e917b7SJacky Bai pinctrl-1 = <&pinctrl_lpuart5>; 118a6e917b7SJacky Bai status = "okay"; 119a6e917b7SJacky Bai}; 120a6e917b7SJacky Bai 121a6e917b7SJacky Bai&usdhc0 { 122*7adf8410SHaibo Chen pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 123a6e917b7SJacky Bai pinctrl-0 = <&pinctrl_usdhc0>; 124a6e917b7SJacky Bai pinctrl-1 = <&pinctrl_usdhc0>; 125*7adf8410SHaibo Chen pinctrl-2 = <&pinctrl_usdhc0>; 126*7adf8410SHaibo Chen pinctrl-3 = <&pinctrl_usdhc0>; 127a6e917b7SJacky Bai non-removable; 128a6e917b7SJacky Bai bus-width = <8>; 129a6e917b7SJacky Bai status = "okay"; 130a6e917b7SJacky Bai}; 131a6e917b7SJacky Bai 1321170826eSWei Fang&fec { 1331170826eSWei Fang pinctrl-names = "default", "sleep"; 1341170826eSWei Fang pinctrl-0 = <&pinctrl_enet>; 1351170826eSWei Fang pinctrl-1 = <&pinctrl_enet>; 1361170826eSWei Fang clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 1371170826eSWei Fang <&pcc4 IMX8ULP_CLK_ENET>, 1381170826eSWei Fang <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, 1391170826eSWei Fang <&clock_ext_rmii>; 1401170826eSWei Fang clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; 1411170826eSWei Fang assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>; 1421170826eSWei Fang assigned-clock-parents = <&clock_ext_ts>; 1431170826eSWei Fang phy-mode = "rmii"; 1441170826eSWei Fang phy-handle = <ðphy>; 1451170826eSWei Fang status = "okay"; 1461170826eSWei Fang 1471170826eSWei Fang mdio { 1481170826eSWei Fang #address-cells = <1>; 1491170826eSWei Fang #size-cells = <0>; 1501170826eSWei Fang 1511170826eSWei Fang ethphy: ethernet-phy@1 { 1521170826eSWei Fang reg = <1>; 1531170826eSWei Fang micrel,led-mode = <1>; 1541170826eSWei Fang }; 1551170826eSWei Fang }; 1561170826eSWei Fang}; 1571170826eSWei Fang 158014fbffaSPeng Fan&mu { 159014fbffaSPeng Fan status = "okay"; 160014fbffaSPeng Fan}; 161014fbffaSPeng Fan 162a6e917b7SJacky Bai&iomuxc1 { 1631170826eSWei Fang pinctrl_enet: enetgrp { 1641170826eSWei Fang fsl,pins = < 1651170826eSWei Fang MX8ULP_PAD_PTE15__ENET0_MDC 0x43 1661170826eSWei Fang MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 1671170826eSWei Fang MX8ULP_PAD_PTE17__ENET0_RXER 0x43 1681170826eSWei Fang MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 1691170826eSWei Fang MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 1701170826eSWei Fang MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 1711170826eSWei Fang MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 1721170826eSWei Fang MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 1731170826eSWei Fang MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 1741170826eSWei Fang MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 1751170826eSWei Fang MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 1761170826eSWei Fang >; 1771170826eSWei Fang }; 1781170826eSWei Fang 1793d256330SHan Xu pinctrl_flexspi2_ptd: flexspi2ptdgrp { 1803d256330SHan Xu fsl,pins = < 1813d256330SHan Xu 1823d256330SHan Xu MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42 1833d256330SHan Xu MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42 1843d256330SHan Xu MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42 1853d256330SHan Xu MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42 1863d256330SHan Xu MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42 1873d256330SHan Xu MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42 1883d256330SHan Xu MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42 1893d256330SHan Xu MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42 1903d256330SHan Xu MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42 1913d256330SHan Xu MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42 1923d256330SHan Xu MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42 1933d256330SHan Xu >; 1943d256330SHan Xu }; 1953d256330SHan Xu 196a6e917b7SJacky Bai pinctrl_lpuart5: lpuart5grp { 197a6e917b7SJacky Bai fsl,pins = < 198a6e917b7SJacky Bai MX8ULP_PAD_PTF14__LPUART5_TX 0x3 199a6e917b7SJacky Bai MX8ULP_PAD_PTF15__LPUART5_RX 0x3 200a6e917b7SJacky Bai >; 201a6e917b7SJacky Bai }; 202a6e917b7SJacky Bai 203a6e917b7SJacky Bai pinctrl_usdhc0: usdhc0grp { 204a6e917b7SJacky Bai fsl,pins = < 205*7adf8410SHaibo Chen MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 206*7adf8410SHaibo Chen MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 207*7adf8410SHaibo Chen MX8ULP_PAD_PTD10__SDHC0_D0 0x3 208*7adf8410SHaibo Chen MX8ULP_PAD_PTD9__SDHC0_D1 0x3 209*7adf8410SHaibo Chen MX8ULP_PAD_PTD8__SDHC0_D2 0x3 210*7adf8410SHaibo Chen MX8ULP_PAD_PTD7__SDHC0_D3 0x3 211*7adf8410SHaibo Chen MX8ULP_PAD_PTD6__SDHC0_D4 0x3 212*7adf8410SHaibo Chen MX8ULP_PAD_PTD5__SDHC0_D5 0x3 213*7adf8410SHaibo Chen MX8ULP_PAD_PTD4__SDHC0_D6 0x3 214*7adf8410SHaibo Chen MX8ULP_PAD_PTD3__SDHC0_D7 0x3 215*7adf8410SHaibo Chen MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 216a6e917b7SJacky Bai >; 217a6e917b7SJacky Bai }; 218a6e917b7SJacky Bai}; 219