1a6e917b7SJacky Bai// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2a6e917b7SJacky Bai/* 3a6e917b7SJacky Bai * Copyright 2021 NXP 4a6e917b7SJacky Bai */ 5a6e917b7SJacky Bai 6a6e917b7SJacky Bai/dts-v1/; 7a6e917b7SJacky Bai 8a6e917b7SJacky Bai#include "imx8ulp.dtsi" 9a6e917b7SJacky Bai 10a6e917b7SJacky Bai/ { 11a6e917b7SJacky Bai model = "NXP i.MX8ULP EVK"; 12a6e917b7SJacky Bai compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; 13a6e917b7SJacky Bai 14a6e917b7SJacky Bai chosen { 15a6e917b7SJacky Bai stdout-path = &lpuart5; 16a6e917b7SJacky Bai }; 17a6e917b7SJacky Bai 18a6e917b7SJacky Bai memory@80000000 { 19a6e917b7SJacky Bai device_type = "memory"; 20a6e917b7SJacky Bai reg = <0x0 0x80000000 0 0x80000000>; 21a6e917b7SJacky Bai }; 22*1170826eSWei Fang 23*1170826eSWei Fang clock_ext_rmii: clock-ext-rmii { 24*1170826eSWei Fang compatible = "fixed-clock"; 25*1170826eSWei Fang clock-frequency = <50000000>; 26*1170826eSWei Fang clock-output-names = "ext_rmii_clk"; 27*1170826eSWei Fang #clock-cells = <0>; 28*1170826eSWei Fang }; 29*1170826eSWei Fang 30*1170826eSWei Fang clock_ext_ts: clock-ext-ts { 31*1170826eSWei Fang compatible = "fixed-clock"; 32*1170826eSWei Fang /* External ts clock is 50MHZ from PHY on EVK board. */ 33*1170826eSWei Fang clock-frequency = <50000000>; 34*1170826eSWei Fang clock-output-names = "ext_ts_clk"; 35*1170826eSWei Fang #clock-cells = <0>; 36*1170826eSWei Fang }; 37a6e917b7SJacky Bai}; 38a6e917b7SJacky Bai 39a6e917b7SJacky Bai&lpuart5 { 40a6e917b7SJacky Bai /* console */ 41a6e917b7SJacky Bai pinctrl-names = "default", "sleep"; 42a6e917b7SJacky Bai pinctrl-0 = <&pinctrl_lpuart5>; 43a6e917b7SJacky Bai pinctrl-1 = <&pinctrl_lpuart5>; 44a6e917b7SJacky Bai status = "okay"; 45a6e917b7SJacky Bai}; 46a6e917b7SJacky Bai 47a6e917b7SJacky Bai&usdhc0 { 48a6e917b7SJacky Bai pinctrl-names = "default", "sleep"; 49a6e917b7SJacky Bai pinctrl-0 = <&pinctrl_usdhc0>; 50a6e917b7SJacky Bai pinctrl-1 = <&pinctrl_usdhc0>; 51a6e917b7SJacky Bai non-removable; 52a6e917b7SJacky Bai bus-width = <8>; 53a6e917b7SJacky Bai status = "okay"; 54a6e917b7SJacky Bai}; 55a6e917b7SJacky Bai 56*1170826eSWei Fang&fec { 57*1170826eSWei Fang pinctrl-names = "default", "sleep"; 58*1170826eSWei Fang pinctrl-0 = <&pinctrl_enet>; 59*1170826eSWei Fang pinctrl-1 = <&pinctrl_enet>; 60*1170826eSWei Fang clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 61*1170826eSWei Fang <&pcc4 IMX8ULP_CLK_ENET>, 62*1170826eSWei Fang <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, 63*1170826eSWei Fang <&clock_ext_rmii>; 64*1170826eSWei Fang clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; 65*1170826eSWei Fang assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>; 66*1170826eSWei Fang assigned-clock-parents = <&clock_ext_ts>; 67*1170826eSWei Fang phy-mode = "rmii"; 68*1170826eSWei Fang phy-handle = <ðphy>; 69*1170826eSWei Fang status = "okay"; 70*1170826eSWei Fang 71*1170826eSWei Fang mdio { 72*1170826eSWei Fang #address-cells = <1>; 73*1170826eSWei Fang #size-cells = <0>; 74*1170826eSWei Fang 75*1170826eSWei Fang ethphy: ethernet-phy@1 { 76*1170826eSWei Fang reg = <1>; 77*1170826eSWei Fang micrel,led-mode = <1>; 78*1170826eSWei Fang }; 79*1170826eSWei Fang }; 80*1170826eSWei Fang}; 81*1170826eSWei Fang 82a6e917b7SJacky Bai&iomuxc1 { 83*1170826eSWei Fang pinctrl_enet: enetgrp { 84*1170826eSWei Fang fsl,pins = < 85*1170826eSWei Fang MX8ULP_PAD_PTE15__ENET0_MDC 0x43 86*1170826eSWei Fang MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 87*1170826eSWei Fang MX8ULP_PAD_PTE17__ENET0_RXER 0x43 88*1170826eSWei Fang MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 89*1170826eSWei Fang MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 90*1170826eSWei Fang MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 91*1170826eSWei Fang MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 92*1170826eSWei Fang MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 93*1170826eSWei Fang MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 94*1170826eSWei Fang MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 95*1170826eSWei Fang MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 96*1170826eSWei Fang >; 97*1170826eSWei Fang }; 98*1170826eSWei Fang 99a6e917b7SJacky Bai pinctrl_lpuart5: lpuart5grp { 100a6e917b7SJacky Bai fsl,pins = < 101a6e917b7SJacky Bai MX8ULP_PAD_PTF14__LPUART5_TX 0x3 102a6e917b7SJacky Bai MX8ULP_PAD_PTF15__LPUART5_RX 0x3 103a6e917b7SJacky Bai >; 104a6e917b7SJacky Bai }; 105a6e917b7SJacky Bai 106a6e917b7SJacky Bai pinctrl_usdhc0: usdhc0grp { 107a6e917b7SJacky Bai fsl,pins = < 108a6e917b7SJacky Bai MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 109a6e917b7SJacky Bai MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 110a6e917b7SJacky Bai MX8ULP_PAD_PTD10__SDHC0_D0 0x43 111a6e917b7SJacky Bai MX8ULP_PAD_PTD9__SDHC0_D1 0x43 112a6e917b7SJacky Bai MX8ULP_PAD_PTD8__SDHC0_D2 0x43 113a6e917b7SJacky Bai MX8ULP_PAD_PTD7__SDHC0_D3 0x43 114a6e917b7SJacky Bai MX8ULP_PAD_PTD6__SDHC0_D4 0x43 115a6e917b7SJacky Bai MX8ULP_PAD_PTD5__SDHC0_D5 0x43 116a6e917b7SJacky Bai MX8ULP_PAD_PTD4__SDHC0_D6 0x43 117a6e917b7SJacky Bai MX8ULP_PAD_PTD3__SDHC0_D7 0x43 118a6e917b7SJacky Bai MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 119a6e917b7SJacky Bai >; 120a6e917b7SJacky Bai }; 121a6e917b7SJacky Bai}; 122