1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2020 NXP
5 *	Dong Aisheng <aisheng.dong@nxp.com>
6 */
7
8#include <dt-bindings/clock/imx8-clock.h>
9#include <dt-bindings/clock/imx8-lpcg.h>
10#include <dt-bindings/firmware/imx/rsrc.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/pinctrl/pads-imx8qxp.h>
15#include <dt-bindings/thermal/thermal.h>
16
17/ {
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		ethernet0 = &fec1;
24		ethernet1 = &fec2;
25		gpio0 = &lsio_gpio0;
26		gpio1 = &lsio_gpio1;
27		gpio2 = &lsio_gpio2;
28		gpio3 = &lsio_gpio3;
29		gpio4 = &lsio_gpio4;
30		gpio5 = &lsio_gpio5;
31		gpio6 = &lsio_gpio6;
32		gpio7 = &lsio_gpio7;
33		i2c0 = &i2c0;
34		i2c1 = &i2c1;
35		i2c2 = &i2c2;
36		i2c3 = &i2c3;
37		mmc0 = &usdhc1;
38		mmc1 = &usdhc2;
39		mmc2 = &usdhc3;
40		mu0 = &lsio_mu0;
41		mu1 = &lsio_mu1;
42		mu2 = &lsio_mu2;
43		mu3 = &lsio_mu3;
44		mu4 = &lsio_mu4;
45		serial0 = &lpuart0;
46		serial1 = &lpuart1;
47		serial2 = &lpuart2;
48		serial3 = &lpuart3;
49		vpu-core0 = &vpu_core0;
50		vpu-core1 = &vpu_core1;
51		vpu-core2 = &vpu_core2;
52	};
53
54	cpus {
55		#address-cells = <2>;
56		#size-cells = <0>;
57
58		/* We have 1 clusters with 4 Cortex-A35 cores */
59		A35_0: cpu@0 {
60			device_type = "cpu";
61			compatible = "arm,cortex-a35";
62			reg = <0x0 0x0>;
63			enable-method = "psci";
64			i-cache-size = <0x8000>;
65			i-cache-line-size = <64>;
66			i-cache-sets = <256>;
67			d-cache-size = <0x8000>;
68			d-cache-line-size = <64>;
69			d-cache-sets = <128>;
70			next-level-cache = <&A35_L2>;
71			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
72			operating-points-v2 = <&a35_opp_table>;
73			#cooling-cells = <2>;
74		};
75
76		A35_1: cpu@1 {
77			device_type = "cpu";
78			compatible = "arm,cortex-a35";
79			reg = <0x0 0x1>;
80			enable-method = "psci";
81			i-cache-size = <0x8000>;
82			i-cache-line-size = <64>;
83			i-cache-sets = <256>;
84			d-cache-size = <0x8000>;
85			d-cache-line-size = <64>;
86			d-cache-sets = <128>;
87			next-level-cache = <&A35_L2>;
88			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
89			operating-points-v2 = <&a35_opp_table>;
90			#cooling-cells = <2>;
91		};
92
93		A35_2: cpu@2 {
94			device_type = "cpu";
95			compatible = "arm,cortex-a35";
96			reg = <0x0 0x2>;
97			enable-method = "psci";
98			i-cache-size = <0x8000>;
99			i-cache-line-size = <64>;
100			i-cache-sets = <256>;
101			d-cache-size = <0x8000>;
102			d-cache-line-size = <64>;
103			d-cache-sets = <128>;
104			next-level-cache = <&A35_L2>;
105			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
106			operating-points-v2 = <&a35_opp_table>;
107			#cooling-cells = <2>;
108		};
109
110		A35_3: cpu@3 {
111			device_type = "cpu";
112			compatible = "arm,cortex-a35";
113			reg = <0x0 0x3>;
114			enable-method = "psci";
115			i-cache-size = <0x8000>;
116			i-cache-line-size = <64>;
117			i-cache-sets = <256>;
118			d-cache-size = <0x8000>;
119			d-cache-line-size = <64>;
120			d-cache-sets = <128>;
121			next-level-cache = <&A35_L2>;
122			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
123			operating-points-v2 = <&a35_opp_table>;
124			#cooling-cells = <2>;
125		};
126
127		A35_L2: l2-cache0 {
128			compatible = "cache";
129			cache-level = <2>;
130			cache-unified;
131			cache-size = <0x80000>;
132			cache-line-size = <64>;
133			cache-sets = <1024>;
134		};
135	};
136
137	a35_opp_table: opp-table {
138		compatible = "operating-points-v2";
139		opp-shared;
140
141		opp-900000000 {
142			opp-hz = /bits/ 64 <900000000>;
143			opp-microvolt = <1000000>;
144			clock-latency-ns = <150000>;
145		};
146
147		opp-1200000000 {
148			opp-hz = /bits/ 64 <1200000000>;
149			opp-microvolt = <1100000>;
150			clock-latency-ns = <150000>;
151			opp-suspend;
152		};
153	};
154
155	gic: interrupt-controller@51a00000 {
156		compatible = "arm,gic-v3";
157		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
158		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
159		#interrupt-cells = <3>;
160		interrupt-controller;
161		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
162	};
163
164	reserved-memory {
165		#address-cells = <2>;
166		#size-cells = <2>;
167		ranges;
168
169		decoder_boot: decoder-boot@84000000 {
170			reg = <0 0x84000000 0 0x2000000>;
171			no-map;
172		};
173
174		encoder_boot: encoder-boot@86000000 {
175			reg = <0 0x86000000 0 0x200000>;
176			no-map;
177		};
178
179		decoder_rpc: decoder-rpc@92000000 {
180			reg = <0 0x92000000 0 0x100000>;
181			no-map;
182		};
183
184		dsp_reserved: dsp@92400000 {
185			reg = <0 0x92400000 0 0x2000000>;
186			no-map;
187		};
188
189		encoder_rpc: encoder-rpc@94400000 {
190			reg = <0 0x94400000 0 0x700000>;
191			no-map;
192		};
193	};
194
195	pmu {
196		compatible = "arm,cortex-a35-pmu";
197		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
198	};
199
200	psci {
201		compatible = "arm,psci-1.0";
202		method = "smc";
203	};
204
205	system-controller {
206		compatible = "fsl,imx-scu";
207		mbox-names = "tx0",
208			     "rx0",
209			     "gip3";
210		mboxes = <&lsio_mu1 0 0
211			  &lsio_mu1 1 0
212			  &lsio_mu1 3 3>;
213
214		pd: power-controller {
215			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
216			#power-domain-cells = <1>;
217		};
218
219		clk: clock-controller {
220			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
221			#clock-cells = <2>;
222		};
223
224		iomuxc: pinctrl {
225			compatible = "fsl,imx8qxp-iomuxc";
226		};
227
228		ocotp: ocotp {
229			compatible = "fsl,imx8qxp-scu-ocotp";
230			#address-cells = <1>;
231			#size-cells = <1>;
232		};
233
234		scu_key: keys {
235			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
236			linux,keycodes = <KEY_POWER>;
237			status = "disabled";
238		};
239
240		rtc: rtc {
241			compatible = "fsl,imx8qxp-sc-rtc";
242		};
243
244		watchdog {
245			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
246			timeout-sec = <60>;
247		};
248
249		tsens: thermal-sensor {
250			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
251			#thermal-sensor-cells = <1>;
252		};
253	};
254
255	timer {
256		compatible = "arm,armv8-timer";
257		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
258			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
259			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
260			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
261	};
262
263	xtal32k: clock-xtal32k {
264		compatible = "fixed-clock";
265		#clock-cells = <0>;
266		clock-frequency = <32768>;
267		clock-output-names = "xtal_32KHz";
268	};
269
270	xtal24m: clock-xtal24m {
271		compatible = "fixed-clock";
272		#clock-cells = <0>;
273		clock-frequency = <24000000>;
274		clock-output-names = "xtal_24MHz";
275	};
276
277	thermal_zones: thermal-zones {
278		cpu0-thermal {
279			polling-delay-passive = <250>;
280			polling-delay = <2000>;
281			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
282
283			trips {
284				cpu_alert0: trip0 {
285					temperature = <107000>;
286					hysteresis = <2000>;
287					type = "passive";
288				};
289
290				cpu_crit0: trip1 {
291					temperature = <127000>;
292					hysteresis = <2000>;
293					type = "critical";
294				};
295			};
296
297			cooling-maps {
298				map0 {
299					trip = <&cpu_alert0>;
300					cooling-device =
301						<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
302						<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
303						<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
304						<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
305				};
306			};
307		};
308	};
309
310	/* sorted in register address */
311	#include "imx8-ss-img.dtsi"
312	#include "imx8-ss-vpu.dtsi"
313	#include "imx8-ss-adma.dtsi"
314	#include "imx8-ss-conn.dtsi"
315	#include "imx8-ss-ddr.dtsi"
316	#include "imx8-ss-lsio.dtsi"
317};
318
319#include "imx8qxp-ss-img.dtsi"
320#include "imx8qxp-ss-adma.dtsi"
321#include "imx8qxp-ss-conn.dtsi"
322#include "imx8qxp-ss-lsio.dtsi"
323