1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2020 NXP
5 *	Dong Aisheng <aisheng.dong@nxp.com>
6 */
7
8#include <dt-bindings/clock/imx8-clock.h>
9#include <dt-bindings/clock/imx8-lpcg.h>
10#include <dt-bindings/firmware/imx/rsrc.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/pinctrl/pads-imx8qxp.h>
15#include <dt-bindings/thermal/thermal.h>
16
17/ {
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		ethernet0 = &fec1;
24		ethernet1 = &fec2;
25		gpio0 = &lsio_gpio0;
26		gpio1 = &lsio_gpio1;
27		gpio2 = &lsio_gpio2;
28		gpio3 = &lsio_gpio3;
29		gpio4 = &lsio_gpio4;
30		gpio5 = &lsio_gpio5;
31		gpio6 = &lsio_gpio6;
32		gpio7 = &lsio_gpio7;
33		i2c0 = &i2c0;
34		i2c1 = &i2c1;
35		i2c2 = &i2c2;
36		i2c3 = &i2c3;
37		mmc0 = &usdhc1;
38		mmc1 = &usdhc2;
39		mmc2 = &usdhc3;
40		mu0 = &lsio_mu0;
41		mu1 = &lsio_mu1;
42		mu2 = &lsio_mu2;
43		mu3 = &lsio_mu3;
44		mu4 = &lsio_mu4;
45		serial0 = &lpuart0;
46		serial1 = &lpuart1;
47		serial2 = &lpuart2;
48		serial3 = &lpuart3;
49	};
50
51	cpus {
52		#address-cells = <2>;
53		#size-cells = <0>;
54
55		/* We have 1 clusters with 4 Cortex-A35 cores */
56		A35_0: cpu@0 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a35";
59			reg = <0x0 0x0>;
60			enable-method = "psci";
61			next-level-cache = <&A35_L2>;
62			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
63			operating-points-v2 = <&a35_opp_table>;
64			#cooling-cells = <2>;
65		};
66
67		A35_1: cpu@1 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a35";
70			reg = <0x0 0x1>;
71			enable-method = "psci";
72			next-level-cache = <&A35_L2>;
73			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
74			operating-points-v2 = <&a35_opp_table>;
75			#cooling-cells = <2>;
76		};
77
78		A35_2: cpu@2 {
79			device_type = "cpu";
80			compatible = "arm,cortex-a35";
81			reg = <0x0 0x2>;
82			enable-method = "psci";
83			next-level-cache = <&A35_L2>;
84			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
85			operating-points-v2 = <&a35_opp_table>;
86			#cooling-cells = <2>;
87		};
88
89		A35_3: cpu@3 {
90			device_type = "cpu";
91			compatible = "arm,cortex-a35";
92			reg = <0x0 0x3>;
93			enable-method = "psci";
94			next-level-cache = <&A35_L2>;
95			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
96			operating-points-v2 = <&a35_opp_table>;
97			#cooling-cells = <2>;
98		};
99
100		A35_L2: l2-cache0 {
101			compatible = "cache";
102		};
103	};
104
105	a35_opp_table: opp-table {
106		compatible = "operating-points-v2";
107		opp-shared;
108
109		opp-900000000 {
110			opp-hz = /bits/ 64 <900000000>;
111			opp-microvolt = <1000000>;
112			clock-latency-ns = <150000>;
113		};
114
115		opp-1200000000 {
116			opp-hz = /bits/ 64 <1200000000>;
117			opp-microvolt = <1100000>;
118			clock-latency-ns = <150000>;
119			opp-suspend;
120		};
121	};
122
123	gic: interrupt-controller@51a00000 {
124		compatible = "arm,gic-v3";
125		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
126		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
127		#interrupt-cells = <3>;
128		interrupt-controller;
129		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
130	};
131
132	reserved-memory {
133		#address-cells = <2>;
134		#size-cells = <2>;
135		ranges;
136
137		dsp_reserved: dsp@92400000 {
138			reg = <0 0x92400000 0 0x2000000>;
139			no-map;
140		};
141	};
142
143	pmu {
144		compatible = "arm,cortex-a35-pmu";
145		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
146	};
147
148	psci {
149		compatible = "arm,psci-1.0";
150		method = "smc";
151	};
152
153	scu {
154		compatible = "fsl,imx-scu";
155		mbox-names = "tx0",
156			     "rx0",
157			     "gip3";
158		mboxes = <&lsio_mu1 0 0
159			  &lsio_mu1 1 0
160			  &lsio_mu1 3 3>;
161
162		pd: imx8qx-pd {
163			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
164			#power-domain-cells = <1>;
165		};
166
167		clk: clock-controller {
168			compatible = "fsl,imx8qxp-clk";
169			#clock-cells = <2>;
170			clocks = <&xtal32k &xtal24m>;
171			clock-names = "xtal_32KHz", "xtal_24Mhz";
172		};
173
174		iomuxc: pinctrl {
175			compatible = "fsl,imx8qxp-iomuxc";
176		};
177
178		ocotp: imx8qx-ocotp {
179			compatible = "fsl,imx8qxp-scu-ocotp";
180			#address-cells = <1>;
181			#size-cells = <1>;
182		};
183
184		scu_key: scu-key {
185			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
186			linux,keycodes = <KEY_POWER>;
187			status = "disabled";
188		};
189
190		rtc: rtc {
191			compatible = "fsl,imx8qxp-sc-rtc";
192		};
193
194		watchdog {
195			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
196			timeout-sec = <60>;
197		};
198
199		tsens: thermal-sensor {
200			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
201			#thermal-sensor-cells = <1>;
202		};
203	};
204
205	timer {
206		compatible = "arm,armv8-timer";
207		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
208			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
209			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
210			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
211	};
212
213	xtal32k: clock-xtal32k {
214		compatible = "fixed-clock";
215		#clock-cells = <0>;
216		clock-frequency = <32768>;
217		clock-output-names = "xtal_32KHz";
218	};
219
220	xtal24m: clock-xtal24m {
221		compatible = "fixed-clock";
222		#clock-cells = <0>;
223		clock-frequency = <24000000>;
224		clock-output-names = "xtal_24MHz";
225	};
226
227	thermal_zones: thermal-zones {
228		cpu-thermal0 {
229			polling-delay-passive = <250>;
230			polling-delay = <2000>;
231			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
232
233			trips {
234				cpu_alert0: trip0 {
235					temperature = <107000>;
236					hysteresis = <2000>;
237					type = "passive";
238				};
239
240				cpu_crit0: trip1 {
241					temperature = <127000>;
242					hysteresis = <2000>;
243					type = "critical";
244				};
245			};
246
247			cooling-maps {
248				map0 {
249					trip = <&cpu_alert0>;
250					cooling-device =
251						<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252						<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
253						<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
254						<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
255				};
256			};
257		};
258	};
259
260	/* sorted in register address */
261	#include "imx8-ss-img.dtsi"
262	#include "imx8-ss-adma.dtsi"
263	#include "imx8-ss-conn.dtsi"
264	#include "imx8-ss-ddr.dtsi"
265	#include "imx8-ss-lsio.dtsi"
266};
267
268#include "imx8qxp-ss-img.dtsi"
269#include "imx8qxp-ss-adma.dtsi"
270#include "imx8qxp-ss-conn.dtsi"
271#include "imx8qxp-ss-lsio.dtsi"
272