13d91ba65SAisheng Dong// SPDX-License-Identifier: GPL-2.0+ 23d91ba65SAisheng Dong/* 33d91ba65SAisheng Dong * Copyright (C) 2016 Freescale Semiconductor, Inc. 40dcd27bdSDong Aisheng * Copyright 2017-2020 NXP 53d91ba65SAisheng Dong * Dong Aisheng <aisheng.dong@nxp.com> 63d91ba65SAisheng Dong */ 73d91ba65SAisheng Dong 83d91ba65SAisheng Dong#include <dt-bindings/clock/imx8-clock.h> 916c4ea75SDong Aisheng#include <dt-bindings/clock/imx8-lpcg.h> 103d91ba65SAisheng Dong#include <dt-bindings/firmware/imx/rsrc.h> 113d91ba65SAisheng Dong#include <dt-bindings/gpio/gpio.h> 1249dad0c1SAnson Huang#include <dt-bindings/input/input.h> 133d91ba65SAisheng Dong#include <dt-bindings/interrupt-controller/arm-gic.h> 143d91ba65SAisheng Dong#include <dt-bindings/pinctrl/pads-imx8qxp.h> 15f0cac141SAnson Huang#include <dt-bindings/thermal/thermal.h> 163d91ba65SAisheng Dong 173d91ba65SAisheng Dong/ { 183d91ba65SAisheng Dong interrupt-parent = <&gic>; 193d91ba65SAisheng Dong #address-cells = <2>; 203d91ba65SAisheng Dong #size-cells = <2>; 213d91ba65SAisheng Dong 223d91ba65SAisheng Dong aliases { 233c8f8d8fSPeng Fan ethernet0 = &fec1; 243c8f8d8fSPeng Fan ethernet1 = &fec2; 25ddabee1eSAnson Huang gpio0 = &lsio_gpio0; 26ddabee1eSAnson Huang gpio1 = &lsio_gpio1; 27ddabee1eSAnson Huang gpio2 = &lsio_gpio2; 28ddabee1eSAnson Huang gpio3 = &lsio_gpio3; 29ddabee1eSAnson Huang gpio4 = &lsio_gpio4; 30ddabee1eSAnson Huang gpio5 = &lsio_gpio5; 31ddabee1eSAnson Huang gpio6 = &lsio_gpio6; 32ddabee1eSAnson Huang gpio7 = &lsio_gpio7; 3335f4e9d7SDong Aisheng i2c0 = &i2c0; 3435f4e9d7SDong Aisheng i2c1 = &i2c1; 3535f4e9d7SDong Aisheng i2c2 = &i2c2; 3635f4e9d7SDong Aisheng i2c3 = &i2c3; 373d91ba65SAisheng Dong mmc0 = &usdhc1; 383d91ba65SAisheng Dong mmc1 = &usdhc2; 393d91ba65SAisheng Dong mmc2 = &usdhc3; 4044f45d5cSPeng Fan mu0 = &lsio_mu0; 416b2bcbd8SAnson Huang mu1 = &lsio_mu1; 4244f45d5cSPeng Fan mu2 = &lsio_mu2; 4344f45d5cSPeng Fan mu3 = &lsio_mu3; 4444f45d5cSPeng Fan mu4 = &lsio_mu4; 4535f4e9d7SDong Aisheng serial0 = &lpuart0; 4635f4e9d7SDong Aisheng serial1 = &lpuart1; 4735f4e9d7SDong Aisheng serial2 = &lpuart2; 4835f4e9d7SDong Aisheng serial3 = &lpuart3; 493d91ba65SAisheng Dong }; 503d91ba65SAisheng Dong 513d91ba65SAisheng Dong cpus { 523d91ba65SAisheng Dong #address-cells = <2>; 533d91ba65SAisheng Dong #size-cells = <0>; 543d91ba65SAisheng Dong 553d91ba65SAisheng Dong /* We have 1 clusters with 4 Cortex-A35 cores */ 563d91ba65SAisheng Dong A35_0: cpu@0 { 573d91ba65SAisheng Dong device_type = "cpu"; 583d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 593d91ba65SAisheng Dong reg = <0x0 0x0>; 603d91ba65SAisheng Dong enable-method = "psci"; 613d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 6226de33a1SDong Aisheng clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 637be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 647be494ddSAnson Huang #cooling-cells = <2>; 653d91ba65SAisheng Dong }; 663d91ba65SAisheng Dong 673d91ba65SAisheng Dong A35_1: cpu@1 { 683d91ba65SAisheng Dong device_type = "cpu"; 693d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 703d91ba65SAisheng Dong reg = <0x0 0x1>; 713d91ba65SAisheng Dong enable-method = "psci"; 723d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 7326de33a1SDong Aisheng clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 747be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 757be494ddSAnson Huang #cooling-cells = <2>; 763d91ba65SAisheng Dong }; 773d91ba65SAisheng Dong 783d91ba65SAisheng Dong A35_2: cpu@2 { 793d91ba65SAisheng Dong device_type = "cpu"; 803d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 813d91ba65SAisheng Dong reg = <0x0 0x2>; 823d91ba65SAisheng Dong enable-method = "psci"; 833d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 8426de33a1SDong Aisheng clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 857be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 867be494ddSAnson Huang #cooling-cells = <2>; 873d91ba65SAisheng Dong }; 883d91ba65SAisheng Dong 893d91ba65SAisheng Dong A35_3: cpu@3 { 903d91ba65SAisheng Dong device_type = "cpu"; 913d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 923d91ba65SAisheng Dong reg = <0x0 0x3>; 933d91ba65SAisheng Dong enable-method = "psci"; 943d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 9526de33a1SDong Aisheng clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 967be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 977be494ddSAnson Huang #cooling-cells = <2>; 983d91ba65SAisheng Dong }; 993d91ba65SAisheng Dong 1003d91ba65SAisheng Dong A35_L2: l2-cache0 { 1013d91ba65SAisheng Dong compatible = "cache"; 1023d91ba65SAisheng Dong }; 1033d91ba65SAisheng Dong }; 1043d91ba65SAisheng Dong 1057be494ddSAnson Huang a35_opp_table: opp-table { 1067be494ddSAnson Huang compatible = "operating-points-v2"; 1077be494ddSAnson Huang opp-shared; 1087be494ddSAnson Huang 1097be494ddSAnson Huang opp-900000000 { 1107be494ddSAnson Huang opp-hz = /bits/ 64 <900000000>; 1117be494ddSAnson Huang opp-microvolt = <1000000>; 1127be494ddSAnson Huang clock-latency-ns = <150000>; 1137be494ddSAnson Huang }; 1147be494ddSAnson Huang 1157be494ddSAnson Huang opp-1200000000 { 1167be494ddSAnson Huang opp-hz = /bits/ 64 <1200000000>; 1177be494ddSAnson Huang opp-microvolt = <1100000>; 1187be494ddSAnson Huang clock-latency-ns = <150000>; 1197be494ddSAnson Huang opp-suspend; 1207be494ddSAnson Huang }; 1217be494ddSAnson Huang }; 1227be494ddSAnson Huang 1233d91ba65SAisheng Dong gic: interrupt-controller@51a00000 { 1243d91ba65SAisheng Dong compatible = "arm,gic-v3"; 1253d91ba65SAisheng Dong reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 1263d91ba65SAisheng Dong <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 1273d91ba65SAisheng Dong #interrupt-cells = <3>; 1283d91ba65SAisheng Dong interrupt-controller; 1293d91ba65SAisheng Dong interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1303d91ba65SAisheng Dong }; 1313d91ba65SAisheng Dong 132cd42fa17SDaniel Baluta reserved-memory { 133cd42fa17SDaniel Baluta #address-cells = <2>; 134cd42fa17SDaniel Baluta #size-cells = <2>; 135cd42fa17SDaniel Baluta ranges; 136cd42fa17SDaniel Baluta 137cd42fa17SDaniel Baluta dsp_reserved: dsp@92400000 { 138cd42fa17SDaniel Baluta reg = <0 0x92400000 0 0x2000000>; 139cd42fa17SDaniel Baluta no-map; 140cd42fa17SDaniel Baluta }; 141cd42fa17SDaniel Baluta }; 142cd42fa17SDaniel Baluta 1433d91ba65SAisheng Dong pmu { 1443d91ba65SAisheng Dong compatible = "arm,armv8-pmuv3"; 1453d91ba65SAisheng Dong interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1463d91ba65SAisheng Dong }; 1473d91ba65SAisheng Dong 1483d91ba65SAisheng Dong psci { 1493d91ba65SAisheng Dong compatible = "arm,psci-1.0"; 1503d91ba65SAisheng Dong method = "smc"; 1513d91ba65SAisheng Dong }; 1523d91ba65SAisheng Dong 1533d91ba65SAisheng Dong scu { 1543d91ba65SAisheng Dong compatible = "fsl,imx-scu"; 15568956811SPeng Fan mbox-names = "tx0", 15668956811SPeng Fan "rx0", 1576b2bcbd8SAnson Huang "gip3"; 1583d91ba65SAisheng Dong mboxes = <&lsio_mu1 0 0 1593d91ba65SAisheng Dong &lsio_mu1 1 0 1606b2bcbd8SAnson Huang &lsio_mu1 3 3>; 1613d91ba65SAisheng Dong 162b1484229SDong Aisheng pd: imx8qx-pd { 163b1484229SDong Aisheng compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 164b1484229SDong Aisheng #power-domain-cells = <1>; 165b1484229SDong Aisheng }; 166b1484229SDong Aisheng 1673d91ba65SAisheng Dong clk: clock-controller { 1683d91ba65SAisheng Dong compatible = "fsl,imx8qxp-clk"; 16926de33a1SDong Aisheng #clock-cells = <2>; 1703d91ba65SAisheng Dong clocks = <&xtal32k &xtal24m>; 1713d91ba65SAisheng Dong clock-names = "xtal_32KHz", "xtal_24Mhz"; 1723d91ba65SAisheng Dong }; 1733d91ba65SAisheng Dong 1743d91ba65SAisheng Dong iomuxc: pinctrl { 1753d91ba65SAisheng Dong compatible = "fsl,imx8qxp-iomuxc"; 1763d91ba65SAisheng Dong }; 1773d91ba65SAisheng Dong 178ef9ed87eSPeng Fan ocotp: imx8qx-ocotp { 179ef9ed87eSPeng Fan compatible = "fsl,imx8qxp-scu-ocotp"; 180ef9ed87eSPeng Fan #address-cells = <1>; 181ef9ed87eSPeng Fan #size-cells = <1>; 182ef9ed87eSPeng Fan }; 183ef9ed87eSPeng Fan 18449dad0c1SAnson Huang scu_key: scu-key { 18549dad0c1SAnson Huang compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 18649dad0c1SAnson Huang linux,keycodes = <KEY_POWER>; 18749dad0c1SAnson Huang status = "disabled"; 18849dad0c1SAnson Huang }; 18949dad0c1SAnson Huang 1906334f879SAnson Huang rtc: rtc { 1916334f879SAnson Huang compatible = "fsl,imx8qxp-sc-rtc"; 1926334f879SAnson Huang }; 193db9693aaSAnson Huang 194db9693aaSAnson Huang watchdog { 195db9693aaSAnson Huang compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 196db9693aaSAnson Huang timeout-sec = <60>; 197db9693aaSAnson Huang }; 198f0cac141SAnson Huang 199f0cac141SAnson Huang tsens: thermal-sensor { 200f0cac141SAnson Huang compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 201f0cac141SAnson Huang #thermal-sensor-cells = <1>; 202f0cac141SAnson Huang }; 2033d91ba65SAisheng Dong }; 2043d91ba65SAisheng Dong 2053d91ba65SAisheng Dong timer { 2063d91ba65SAisheng Dong compatible = "arm,armv8-timer"; 2073d91ba65SAisheng Dong interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 2083d91ba65SAisheng Dong <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 2093d91ba65SAisheng Dong <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 2103d91ba65SAisheng Dong <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 2113d91ba65SAisheng Dong }; 2123d91ba65SAisheng Dong 2133d91ba65SAisheng Dong xtal32k: clock-xtal32k { 2143d91ba65SAisheng Dong compatible = "fixed-clock"; 2153d91ba65SAisheng Dong #clock-cells = <0>; 2163d91ba65SAisheng Dong clock-frequency = <32768>; 2173d91ba65SAisheng Dong clock-output-names = "xtal_32KHz"; 2183d91ba65SAisheng Dong }; 2193d91ba65SAisheng Dong 2203d91ba65SAisheng Dong xtal24m: clock-xtal24m { 2213d91ba65SAisheng Dong compatible = "fixed-clock"; 2223d91ba65SAisheng Dong #clock-cells = <0>; 2233d91ba65SAisheng Dong clock-frequency = <24000000>; 2243d91ba65SAisheng Dong clock-output-names = "xtal_24MHz"; 2253d91ba65SAisheng Dong }; 2263d91ba65SAisheng Dong 227f0cac141SAnson Huang thermal_zones: thermal-zones { 228f0cac141SAnson Huang cpu-thermal0 { 229f0cac141SAnson Huang polling-delay-passive = <250>; 230f0cac141SAnson Huang polling-delay = <2000>; 231f0cac141SAnson Huang thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 232f0cac141SAnson Huang 233f0cac141SAnson Huang trips { 234f0cac141SAnson Huang cpu_alert0: trip0 { 235f0cac141SAnson Huang temperature = <107000>; 236f0cac141SAnson Huang hysteresis = <2000>; 237f0cac141SAnson Huang type = "passive"; 238f0cac141SAnson Huang }; 239f0cac141SAnson Huang 240f0cac141SAnson Huang cpu_crit0: trip1 { 241f0cac141SAnson Huang temperature = <127000>; 242f0cac141SAnson Huang hysteresis = <2000>; 243f0cac141SAnson Huang type = "critical"; 244f0cac141SAnson Huang }; 245f0cac141SAnson Huang }; 246f0cac141SAnson Huang 247f0cac141SAnson Huang cooling-maps { 248f0cac141SAnson Huang map0 { 249f0cac141SAnson Huang trip = <&cpu_alert0>; 250f0cac141SAnson Huang cooling-device = 251f0cac141SAnson Huang <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252f0cac141SAnson Huang <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253f0cac141SAnson Huang <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 254f0cac141SAnson Huang <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 255f0cac141SAnson Huang }; 256f0cac141SAnson Huang }; 257f0cac141SAnson Huang }; 258f0cac141SAnson Huang }; 2590dcd27bdSDong Aisheng 2600dcd27bdSDong Aisheng /* sorted in register address */ 261*5bb27917SMirela Rabulea #include "imx8-ss-img.dtsi" 2620dcd27bdSDong Aisheng #include "imx8-ss-adma.dtsi" 2630dcd27bdSDong Aisheng #include "imx8-ss-conn.dtsi" 2640dcd27bdSDong Aisheng #include "imx8-ss-ddr.dtsi" 2650dcd27bdSDong Aisheng #include "imx8-ss-lsio.dtsi" 2663d91ba65SAisheng Dong}; 2670dcd27bdSDong Aisheng 268*5bb27917SMirela Rabulea#include "imx8qxp-ss-img.dtsi" 2690dcd27bdSDong Aisheng#include "imx8qxp-ss-adma.dtsi" 2700dcd27bdSDong Aisheng#include "imx8qxp-ss-conn.dtsi" 2710dcd27bdSDong Aisheng#include "imx8qxp-ss-lsio.dtsi" 272