13d91ba65SAisheng Dong// SPDX-License-Identifier: GPL-2.0+ 23d91ba65SAisheng Dong/* 33d91ba65SAisheng Dong * Copyright (C) 2016 Freescale Semiconductor, Inc. 43d91ba65SAisheng Dong * Copyright 2017-2018 NXP 53d91ba65SAisheng Dong * Dong Aisheng <aisheng.dong@nxp.com> 63d91ba65SAisheng Dong */ 73d91ba65SAisheng Dong 83d91ba65SAisheng Dong#include <dt-bindings/clock/imx8-clock.h> 93d91ba65SAisheng Dong#include <dt-bindings/firmware/imx/rsrc.h> 103d91ba65SAisheng Dong#include <dt-bindings/gpio/gpio.h> 113d91ba65SAisheng Dong#include <dt-bindings/interrupt-controller/arm-gic.h> 123d91ba65SAisheng Dong#include <dt-bindings/pinctrl/pads-imx8qxp.h> 133d91ba65SAisheng Dong 143d91ba65SAisheng Dong/ { 153d91ba65SAisheng Dong interrupt-parent = <&gic>; 163d91ba65SAisheng Dong #address-cells = <2>; 173d91ba65SAisheng Dong #size-cells = <2>; 183d91ba65SAisheng Dong 193d91ba65SAisheng Dong aliases { 20ddabee1eSAnson Huang gpio0 = &lsio_gpio0; 21ddabee1eSAnson Huang gpio1 = &lsio_gpio1; 22ddabee1eSAnson Huang gpio2 = &lsio_gpio2; 23ddabee1eSAnson Huang gpio3 = &lsio_gpio3; 24ddabee1eSAnson Huang gpio4 = &lsio_gpio4; 25ddabee1eSAnson Huang gpio5 = &lsio_gpio5; 26ddabee1eSAnson Huang gpio6 = &lsio_gpio6; 27ddabee1eSAnson Huang gpio7 = &lsio_gpio7; 283d91ba65SAisheng Dong mmc0 = &usdhc1; 293d91ba65SAisheng Dong mmc1 = &usdhc2; 303d91ba65SAisheng Dong mmc2 = &usdhc3; 316b2bcbd8SAnson Huang mu1 = &lsio_mu1; 3274d82a30SShawn Guo serial0 = &adma_lpuart0; 333d91ba65SAisheng Dong }; 343d91ba65SAisheng Dong 353d91ba65SAisheng Dong cpus { 363d91ba65SAisheng Dong #address-cells = <2>; 373d91ba65SAisheng Dong #size-cells = <0>; 383d91ba65SAisheng Dong 393d91ba65SAisheng Dong /* We have 1 clusters with 4 Cortex-A35 cores */ 403d91ba65SAisheng Dong A35_0: cpu@0 { 413d91ba65SAisheng Dong device_type = "cpu"; 423d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 433d91ba65SAisheng Dong reg = <0x0 0x0>; 443d91ba65SAisheng Dong enable-method = "psci"; 453d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 467be494ddSAnson Huang clocks = <&clk IMX_A35_CLK>; 477be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 487be494ddSAnson Huang #cooling-cells = <2>; 493d91ba65SAisheng Dong }; 503d91ba65SAisheng Dong 513d91ba65SAisheng Dong A35_1: cpu@1 { 523d91ba65SAisheng Dong device_type = "cpu"; 533d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 543d91ba65SAisheng Dong reg = <0x0 0x1>; 553d91ba65SAisheng Dong enable-method = "psci"; 563d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 577be494ddSAnson Huang clocks = <&clk IMX_A35_CLK>; 587be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 597be494ddSAnson Huang #cooling-cells = <2>; 603d91ba65SAisheng Dong }; 613d91ba65SAisheng Dong 623d91ba65SAisheng Dong A35_2: cpu@2 { 633d91ba65SAisheng Dong device_type = "cpu"; 643d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 653d91ba65SAisheng Dong reg = <0x0 0x2>; 663d91ba65SAisheng Dong enable-method = "psci"; 673d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 687be494ddSAnson Huang clocks = <&clk IMX_A35_CLK>; 697be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 707be494ddSAnson Huang #cooling-cells = <2>; 713d91ba65SAisheng Dong }; 723d91ba65SAisheng Dong 733d91ba65SAisheng Dong A35_3: cpu@3 { 743d91ba65SAisheng Dong device_type = "cpu"; 753d91ba65SAisheng Dong compatible = "arm,cortex-a35"; 763d91ba65SAisheng Dong reg = <0x0 0x3>; 773d91ba65SAisheng Dong enable-method = "psci"; 783d91ba65SAisheng Dong next-level-cache = <&A35_L2>; 797be494ddSAnson Huang clocks = <&clk IMX_A35_CLK>; 807be494ddSAnson Huang operating-points-v2 = <&a35_opp_table>; 817be494ddSAnson Huang #cooling-cells = <2>; 823d91ba65SAisheng Dong }; 833d91ba65SAisheng Dong 843d91ba65SAisheng Dong A35_L2: l2-cache0 { 853d91ba65SAisheng Dong compatible = "cache"; 863d91ba65SAisheng Dong }; 873d91ba65SAisheng Dong }; 883d91ba65SAisheng Dong 897be494ddSAnson Huang a35_opp_table: opp-table { 907be494ddSAnson Huang compatible = "operating-points-v2"; 917be494ddSAnson Huang opp-shared; 927be494ddSAnson Huang 937be494ddSAnson Huang opp-900000000 { 947be494ddSAnson Huang opp-hz = /bits/ 64 <900000000>; 957be494ddSAnson Huang opp-microvolt = <1000000>; 967be494ddSAnson Huang clock-latency-ns = <150000>; 977be494ddSAnson Huang }; 987be494ddSAnson Huang 997be494ddSAnson Huang opp-1200000000 { 1007be494ddSAnson Huang opp-hz = /bits/ 64 <1200000000>; 1017be494ddSAnson Huang opp-microvolt = <1100000>; 1027be494ddSAnson Huang clock-latency-ns = <150000>; 1037be494ddSAnson Huang opp-suspend; 1047be494ddSAnson Huang }; 1057be494ddSAnson Huang }; 1067be494ddSAnson Huang 1073d91ba65SAisheng Dong gic: interrupt-controller@51a00000 { 1083d91ba65SAisheng Dong compatible = "arm,gic-v3"; 1093d91ba65SAisheng Dong reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 1103d91ba65SAisheng Dong <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 1113d91ba65SAisheng Dong #interrupt-cells = <3>; 1123d91ba65SAisheng Dong interrupt-controller; 1133d91ba65SAisheng Dong interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1143d91ba65SAisheng Dong }; 1153d91ba65SAisheng Dong 1163d91ba65SAisheng Dong pmu { 1173d91ba65SAisheng Dong compatible = "arm,armv8-pmuv3"; 1183d91ba65SAisheng Dong interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1193d91ba65SAisheng Dong }; 1203d91ba65SAisheng Dong 1213d91ba65SAisheng Dong psci { 1223d91ba65SAisheng Dong compatible = "arm,psci-1.0"; 1233d91ba65SAisheng Dong method = "smc"; 1243d91ba65SAisheng Dong }; 1253d91ba65SAisheng Dong 1263d91ba65SAisheng Dong scu { 1273d91ba65SAisheng Dong compatible = "fsl,imx-scu"; 1283d91ba65SAisheng Dong mbox-names = "tx0", "tx1", "tx2", "tx3", 1296b2bcbd8SAnson Huang "rx0", "rx1", "rx2", "rx3", 1306b2bcbd8SAnson Huang "gip3"; 1313d91ba65SAisheng Dong mboxes = <&lsio_mu1 0 0 1323d91ba65SAisheng Dong &lsio_mu1 0 1 1333d91ba65SAisheng Dong &lsio_mu1 0 2 1343d91ba65SAisheng Dong &lsio_mu1 0 3 1353d91ba65SAisheng Dong &lsio_mu1 1 0 1363d91ba65SAisheng Dong &lsio_mu1 1 1 1373d91ba65SAisheng Dong &lsio_mu1 1 2 1386b2bcbd8SAnson Huang &lsio_mu1 1 3 1396b2bcbd8SAnson Huang &lsio_mu1 3 3>; 1403d91ba65SAisheng Dong 1413d91ba65SAisheng Dong clk: clock-controller { 1423d91ba65SAisheng Dong compatible = "fsl,imx8qxp-clk"; 1433d91ba65SAisheng Dong #clock-cells = <1>; 1443d91ba65SAisheng Dong clocks = <&xtal32k &xtal24m>; 1453d91ba65SAisheng Dong clock-names = "xtal_32KHz", "xtal_24Mhz"; 1463d91ba65SAisheng Dong }; 1473d91ba65SAisheng Dong 1483d91ba65SAisheng Dong iomuxc: pinctrl { 1493d91ba65SAisheng Dong compatible = "fsl,imx8qxp-iomuxc"; 1503d91ba65SAisheng Dong }; 1513d91ba65SAisheng Dong 152ef9ed87eSPeng Fan ocotp: imx8qx-ocotp { 153ef9ed87eSPeng Fan compatible = "fsl,imx8qxp-scu-ocotp"; 154ef9ed87eSPeng Fan #address-cells = <1>; 155ef9ed87eSPeng Fan #size-cells = <1>; 156ef9ed87eSPeng Fan }; 157ef9ed87eSPeng Fan 1583d91ba65SAisheng Dong pd: imx8qx-pd { 1593d91ba65SAisheng Dong compatible = "fsl,imx8qxp-scu-pd"; 1603d91ba65SAisheng Dong #power-domain-cells = <1>; 1613d91ba65SAisheng Dong }; 1626334f879SAnson Huang 1636334f879SAnson Huang rtc: rtc { 1646334f879SAnson Huang compatible = "fsl,imx8qxp-sc-rtc"; 1656334f879SAnson Huang }; 166db9693aaSAnson Huang 167db9693aaSAnson Huang watchdog { 168db9693aaSAnson Huang compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 169db9693aaSAnson Huang timeout-sec = <60>; 170db9693aaSAnson Huang }; 1713d91ba65SAisheng Dong }; 1723d91ba65SAisheng Dong 1733d91ba65SAisheng Dong timer { 1743d91ba65SAisheng Dong compatible = "arm,armv8-timer"; 1753d91ba65SAisheng Dong interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 1763d91ba65SAisheng Dong <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 1773d91ba65SAisheng Dong <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 1783d91ba65SAisheng Dong <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 1793d91ba65SAisheng Dong }; 1803d91ba65SAisheng Dong 1813d91ba65SAisheng Dong xtal32k: clock-xtal32k { 1823d91ba65SAisheng Dong compatible = "fixed-clock"; 1833d91ba65SAisheng Dong #clock-cells = <0>; 1843d91ba65SAisheng Dong clock-frequency = <32768>; 1853d91ba65SAisheng Dong clock-output-names = "xtal_32KHz"; 1863d91ba65SAisheng Dong }; 1873d91ba65SAisheng Dong 1883d91ba65SAisheng Dong xtal24m: clock-xtal24m { 1893d91ba65SAisheng Dong compatible = "fixed-clock"; 1903d91ba65SAisheng Dong #clock-cells = <0>; 1913d91ba65SAisheng Dong clock-frequency = <24000000>; 1923d91ba65SAisheng Dong clock-output-names = "xtal_24MHz"; 1933d91ba65SAisheng Dong }; 1943d91ba65SAisheng Dong 1953d91ba65SAisheng Dong adma_subsys: bus@59000000 { 1963d91ba65SAisheng Dong compatible = "simple-bus"; 1973d91ba65SAisheng Dong #address-cells = <1>; 1983d91ba65SAisheng Dong #size-cells = <1>; 1993d91ba65SAisheng Dong ranges = <0x59000000 0x0 0x59000000 0x2000000>; 2003d91ba65SAisheng Dong 2013d91ba65SAisheng Dong adma_lpcg: clock-controller@59000000 { 2023d91ba65SAisheng Dong compatible = "fsl,imx8qxp-lpcg-adma"; 2033d91ba65SAisheng Dong reg = <0x59000000 0x2000000>; 2043d91ba65SAisheng Dong #clock-cells = <1>; 2053d91ba65SAisheng Dong }; 2063d91ba65SAisheng Dong 2073d91ba65SAisheng Dong adma_lpuart0: serial@5a060000 { 2083d91ba65SAisheng Dong compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 2093d91ba65SAisheng Dong reg = <0x5a060000 0x1000>; 2103d91ba65SAisheng Dong interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 2113d91ba65SAisheng Dong interrupt-parent = <&gic>; 2123d91ba65SAisheng Dong clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 2133d91ba65SAisheng Dong clock-names = "ipg"; 2143d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_UART_0>; 2153d91ba65SAisheng Dong status = "disabled"; 2163d91ba65SAisheng Dong }; 2173d91ba65SAisheng Dong 21829fdb6b8SDaniel Baluta adma_lpuart1: serial@5a070000 { 21929fdb6b8SDaniel Baluta compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 22029fdb6b8SDaniel Baluta reg = <0x5a070000 0x1000>; 22129fdb6b8SDaniel Baluta interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 22229fdb6b8SDaniel Baluta interrupt-parent = <&gic>; 22329fdb6b8SDaniel Baluta clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 22429fdb6b8SDaniel Baluta clock-names = "ipg"; 22529fdb6b8SDaniel Baluta power-domains = <&pd IMX_SC_R_UART_1>; 22629fdb6b8SDaniel Baluta status = "disabled"; 22729fdb6b8SDaniel Baluta }; 22829fdb6b8SDaniel Baluta 22929fdb6b8SDaniel Baluta adma_lpuart2: serial@5a080000 { 23029fdb6b8SDaniel Baluta compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 23129fdb6b8SDaniel Baluta reg = <0x5a080000 0x1000>; 23229fdb6b8SDaniel Baluta interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 23329fdb6b8SDaniel Baluta interrupt-parent = <&gic>; 23429fdb6b8SDaniel Baluta clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 23529fdb6b8SDaniel Baluta clock-names = "ipg"; 23629fdb6b8SDaniel Baluta power-domains = <&pd IMX_SC_R_UART_2>; 23729fdb6b8SDaniel Baluta status = "disabled"; 23829fdb6b8SDaniel Baluta }; 23929fdb6b8SDaniel Baluta 24029fdb6b8SDaniel Baluta adma_lpuart3: serial@5a090000 { 24129fdb6b8SDaniel Baluta compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 24229fdb6b8SDaniel Baluta reg = <0x5a090000 0x1000>; 24329fdb6b8SDaniel Baluta interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 24429fdb6b8SDaniel Baluta interrupt-parent = <&gic>; 24529fdb6b8SDaniel Baluta clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 24629fdb6b8SDaniel Baluta clock-names = "ipg"; 24729fdb6b8SDaniel Baluta power-domains = <&pd IMX_SC_R_UART_3>; 24829fdb6b8SDaniel Baluta status = "disabled"; 24929fdb6b8SDaniel Baluta }; 25029fdb6b8SDaniel Baluta 2513d91ba65SAisheng Dong adma_i2c0: i2c@5a800000 { 2523d91ba65SAisheng Dong compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 2533d91ba65SAisheng Dong reg = <0x5a800000 0x4000>; 2543d91ba65SAisheng Dong interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 2553d91ba65SAisheng Dong interrupt-parent = <&gic>; 2563d91ba65SAisheng Dong clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 2573d91ba65SAisheng Dong clock-names = "per"; 2583d91ba65SAisheng Dong assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 2593d91ba65SAisheng Dong assigned-clock-rates = <24000000>; 2603d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_I2C_0>; 2613d91ba65SAisheng Dong status = "disabled"; 2623d91ba65SAisheng Dong }; 2633d91ba65SAisheng Dong 2643d91ba65SAisheng Dong adma_i2c1: i2c@5a810000 { 2653d91ba65SAisheng Dong compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 2663d91ba65SAisheng Dong reg = <0x5a810000 0x4000>; 2673d91ba65SAisheng Dong interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2683d91ba65SAisheng Dong interrupt-parent = <&gic>; 2693d91ba65SAisheng Dong clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 2703d91ba65SAisheng Dong clock-names = "per"; 2713d91ba65SAisheng Dong assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 2723d91ba65SAisheng Dong assigned-clock-rates = <24000000>; 2733d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_I2C_1>; 2743d91ba65SAisheng Dong status = "disabled"; 2753d91ba65SAisheng Dong }; 2763d91ba65SAisheng Dong 2773d91ba65SAisheng Dong adma_i2c2: i2c@5a820000 { 2783d91ba65SAisheng Dong compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 2793d91ba65SAisheng Dong reg = <0x5a820000 0x4000>; 2803d91ba65SAisheng Dong interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2813d91ba65SAisheng Dong interrupt-parent = <&gic>; 2823d91ba65SAisheng Dong clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 2833d91ba65SAisheng Dong clock-names = "per"; 2843d91ba65SAisheng Dong assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 2853d91ba65SAisheng Dong assigned-clock-rates = <24000000>; 2863d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_I2C_2>; 2873d91ba65SAisheng Dong status = "disabled"; 2883d91ba65SAisheng Dong }; 2893d91ba65SAisheng Dong 2903d91ba65SAisheng Dong adma_i2c3: i2c@5a830000 { 2913d91ba65SAisheng Dong compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 2923d91ba65SAisheng Dong reg = <0x5a830000 0x4000>; 2933d91ba65SAisheng Dong interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2943d91ba65SAisheng Dong interrupt-parent = <&gic>; 2953d91ba65SAisheng Dong clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 2963d91ba65SAisheng Dong clock-names = "per"; 2973d91ba65SAisheng Dong assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 2983d91ba65SAisheng Dong assigned-clock-rates = <24000000>; 2993d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_I2C_3>; 3003d91ba65SAisheng Dong status = "disabled"; 3013d91ba65SAisheng Dong }; 3023d91ba65SAisheng Dong }; 3033d91ba65SAisheng Dong 3043d91ba65SAisheng Dong conn_subsys: bus@5b000000 { 3053d91ba65SAisheng Dong compatible = "simple-bus"; 3063d91ba65SAisheng Dong #address-cells = <1>; 3073d91ba65SAisheng Dong #size-cells = <1>; 3083d91ba65SAisheng Dong ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 3093d91ba65SAisheng Dong 3103d91ba65SAisheng Dong conn_lpcg: clock-controller@5b200000 { 3113d91ba65SAisheng Dong compatible = "fsl,imx8qxp-lpcg-conn"; 3123d91ba65SAisheng Dong reg = <0x5b200000 0xb0000>; 3133d91ba65SAisheng Dong #clock-cells = <1>; 3143d91ba65SAisheng Dong }; 3153d91ba65SAisheng Dong 3163d91ba65SAisheng Dong usdhc1: mmc@5b010000 { 3173d91ba65SAisheng Dong compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 3183d91ba65SAisheng Dong interrupt-parent = <&gic>; 3193d91ba65SAisheng Dong interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 3203d91ba65SAisheng Dong reg = <0x5b010000 0x10000>; 3213d91ba65SAisheng Dong clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 3223d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 3233d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 3243d91ba65SAisheng Dong clock-names = "ipg", "per", "ahb"; 3253d91ba65SAisheng Dong assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 3263d91ba65SAisheng Dong assigned-clock-rates = <200000000>; 3273d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_SDHC_0>; 3283d91ba65SAisheng Dong status = "disabled"; 3293d91ba65SAisheng Dong }; 3303d91ba65SAisheng Dong 3313d91ba65SAisheng Dong usdhc2: mmc@5b020000 { 3323d91ba65SAisheng Dong compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 3333d91ba65SAisheng Dong interrupt-parent = <&gic>; 3343d91ba65SAisheng Dong interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 3353d91ba65SAisheng Dong reg = <0x5b020000 0x10000>; 3363d91ba65SAisheng Dong clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 3373d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 3383d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 3393d91ba65SAisheng Dong clock-names = "ipg", "per", "ahb"; 3403d91ba65SAisheng Dong assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 3413d91ba65SAisheng Dong assigned-clock-rates = <200000000>; 3423d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_SDHC_1>; 3433d91ba65SAisheng Dong fsl,tuning-start-tap = <20>; 3443d91ba65SAisheng Dong fsl,tuning-step= <2>; 3453d91ba65SAisheng Dong status = "disabled"; 3463d91ba65SAisheng Dong }; 3473d91ba65SAisheng Dong 3483d91ba65SAisheng Dong usdhc3: mmc@5b030000 { 3493d91ba65SAisheng Dong compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 3503d91ba65SAisheng Dong interrupt-parent = <&gic>; 3513d91ba65SAisheng Dong interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 3523d91ba65SAisheng Dong reg = <0x5b030000 0x10000>; 3533d91ba65SAisheng Dong clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 3543d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 3553d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 3563d91ba65SAisheng Dong clock-names = "ipg", "per", "ahb"; 3573d91ba65SAisheng Dong assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; 3583d91ba65SAisheng Dong assigned-clock-rates = <200000000>; 3593d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_SDHC_2>; 3603d91ba65SAisheng Dong status = "disabled"; 3613d91ba65SAisheng Dong }; 3623d91ba65SAisheng Dong 3633d91ba65SAisheng Dong fec1: ethernet@5b040000 { 3643d91ba65SAisheng Dong compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 3653d91ba65SAisheng Dong reg = <0x5b040000 0x10000>; 3663d91ba65SAisheng Dong interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 3673d91ba65SAisheng Dong <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 3683d91ba65SAisheng Dong <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 3693d91ba65SAisheng Dong <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 3703d91ba65SAisheng Dong clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 3713d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 3723d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 3733d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 3743d91ba65SAisheng Dong clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 3753d91ba65SAisheng Dong fsl,num-tx-queues=<3>; 3763d91ba65SAisheng Dong fsl,num-rx-queues=<3>; 3773d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_ENET_0>; 3783d91ba65SAisheng Dong status = "disabled"; 3793d91ba65SAisheng Dong }; 3803d91ba65SAisheng Dong 3813d91ba65SAisheng Dong fec2: ethernet@5b050000 { 3823d91ba65SAisheng Dong compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 3833d91ba65SAisheng Dong reg = <0x5b050000 0x10000>; 3843d91ba65SAisheng Dong interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 3853d91ba65SAisheng Dong <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 3863d91ba65SAisheng Dong <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3873d91ba65SAisheng Dong <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 3883d91ba65SAisheng Dong clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 3893d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 3903d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 3913d91ba65SAisheng Dong <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 3923d91ba65SAisheng Dong clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 3933d91ba65SAisheng Dong fsl,num-tx-queues=<3>; 3943d91ba65SAisheng Dong fsl,num-rx-queues=<3>; 3953d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_ENET_1>; 3963d91ba65SAisheng Dong status = "disabled"; 3973d91ba65SAisheng Dong }; 3983d91ba65SAisheng Dong }; 3993d91ba65SAisheng Dong 4003d91ba65SAisheng Dong lsio_subsys: bus@5d000000 { 4013d91ba65SAisheng Dong compatible = "simple-bus"; 4023d91ba65SAisheng Dong #address-cells = <1>; 4033d91ba65SAisheng Dong #size-cells = <1>; 4043d91ba65SAisheng Dong ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 4053d91ba65SAisheng Dong 4063d91ba65SAisheng Dong lsio_gpio0: gpio@5d080000 { 4073d91ba65SAisheng Dong compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 4083d91ba65SAisheng Dong reg = <0x5d080000 0x10000>; 4093d91ba65SAisheng Dong interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 4103d91ba65SAisheng Dong gpio-controller; 4113d91ba65SAisheng Dong #gpio-cells = <2>; 4123d91ba65SAisheng Dong interrupt-controller; 4133d91ba65SAisheng Dong #interrupt-cells = <2>; 4143d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_GPIO_0>; 4153d91ba65SAisheng Dong }; 4163d91ba65SAisheng Dong 4173d91ba65SAisheng Dong lsio_gpio1: gpio@5d090000 { 4183d91ba65SAisheng Dong compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 4193d91ba65SAisheng Dong reg = <0x5d090000 0x10000>; 4203d91ba65SAisheng Dong interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 4213d91ba65SAisheng Dong gpio-controller; 4223d91ba65SAisheng Dong #gpio-cells = <2>; 4233d91ba65SAisheng Dong interrupt-controller; 4243d91ba65SAisheng Dong #interrupt-cells = <2>; 4253d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_GPIO_1>; 4263d91ba65SAisheng Dong }; 4273d91ba65SAisheng Dong 4283d91ba65SAisheng Dong lsio_gpio2: gpio@5d0a0000 { 4293d91ba65SAisheng Dong compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 4303d91ba65SAisheng Dong reg = <0x5d0a0000 0x10000>; 4313d91ba65SAisheng Dong interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4323d91ba65SAisheng Dong gpio-controller; 4333d91ba65SAisheng Dong #gpio-cells = <2>; 4343d91ba65SAisheng Dong interrupt-controller; 4353d91ba65SAisheng Dong #interrupt-cells = <2>; 4363d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_GPIO_2>; 4373d91ba65SAisheng Dong }; 4383d91ba65SAisheng Dong 4393d91ba65SAisheng Dong lsio_gpio3: gpio@5d0b0000 { 4403d91ba65SAisheng Dong compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 4413d91ba65SAisheng Dong reg = <0x5d0b0000 0x10000>; 4423d91ba65SAisheng Dong interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 4433d91ba65SAisheng Dong gpio-controller; 4443d91ba65SAisheng Dong #gpio-cells = <2>; 4453d91ba65SAisheng Dong interrupt-controller; 4463d91ba65SAisheng Dong #interrupt-cells = <2>; 4473d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_GPIO_3>; 4483d91ba65SAisheng Dong }; 4493d91ba65SAisheng Dong 4503d91ba65SAisheng Dong lsio_gpio4: gpio@5d0c0000 { 4513d91ba65SAisheng Dong compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 4523d91ba65SAisheng Dong reg = <0x5d0c0000 0x10000>; 4533d91ba65SAisheng Dong interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4543d91ba65SAisheng Dong gpio-controller; 4553d91ba65SAisheng Dong #gpio-cells = <2>; 4563d91ba65SAisheng Dong interrupt-controller; 4573d91ba65SAisheng Dong #interrupt-cells = <2>; 4583d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_GPIO_4>; 4593d91ba65SAisheng Dong }; 4603d91ba65SAisheng Dong 4613d91ba65SAisheng Dong lsio_gpio5: gpio@5d0d0000 { 4623d91ba65SAisheng Dong compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 4633d91ba65SAisheng Dong reg = <0x5d0d0000 0x10000>; 4643d91ba65SAisheng Dong interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 4653d91ba65SAisheng Dong gpio-controller; 4663d91ba65SAisheng Dong #gpio-cells = <2>; 4673d91ba65SAisheng Dong interrupt-controller; 4683d91ba65SAisheng Dong #interrupt-cells = <2>; 4693d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_GPIO_5>; 4703d91ba65SAisheng Dong }; 4713d91ba65SAisheng Dong 4723d91ba65SAisheng Dong lsio_gpio6: gpio@5d0e0000 { 4733d91ba65SAisheng Dong compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 4743d91ba65SAisheng Dong reg = <0x5d0e0000 0x10000>; 4753d91ba65SAisheng Dong interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 4763d91ba65SAisheng Dong gpio-controller; 4773d91ba65SAisheng Dong #gpio-cells = <2>; 4783d91ba65SAisheng Dong interrupt-controller; 4793d91ba65SAisheng Dong #interrupt-cells = <2>; 4803d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_GPIO_6>; 4813d91ba65SAisheng Dong }; 4823d91ba65SAisheng Dong 4833d91ba65SAisheng Dong lsio_gpio7: gpio@5d0f0000 { 4843d91ba65SAisheng Dong compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 4853d91ba65SAisheng Dong reg = <0x5d0f0000 0x10000>; 4863d91ba65SAisheng Dong interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 4873d91ba65SAisheng Dong gpio-controller; 4883d91ba65SAisheng Dong #gpio-cells = <2>; 4893d91ba65SAisheng Dong interrupt-controller; 4903d91ba65SAisheng Dong #interrupt-cells = <2>; 4913d91ba65SAisheng Dong power-domains = <&pd IMX_SC_R_GPIO_7>; 4923d91ba65SAisheng Dong }; 493107529cfSShawn Guo 494107529cfSShawn Guo lsio_mu0: mailbox@5d1b0000 { 495107529cfSShawn Guo compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 496107529cfSShawn Guo reg = <0x5d1b0000 0x10000>; 497107529cfSShawn Guo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 498107529cfSShawn Guo #mbox-cells = <2>; 499107529cfSShawn Guo status = "disabled"; 500107529cfSShawn Guo }; 501107529cfSShawn Guo 502107529cfSShawn Guo lsio_mu1: mailbox@5d1c0000 { 503107529cfSShawn Guo compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 504107529cfSShawn Guo reg = <0x5d1c0000 0x10000>; 505107529cfSShawn Guo interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 506107529cfSShawn Guo #mbox-cells = <2>; 507107529cfSShawn Guo }; 508107529cfSShawn Guo 509107529cfSShawn Guo lsio_mu2: mailbox@5d1d0000 { 510107529cfSShawn Guo compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 511107529cfSShawn Guo reg = <0x5d1d0000 0x10000>; 512107529cfSShawn Guo interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 513107529cfSShawn Guo #mbox-cells = <2>; 514107529cfSShawn Guo status = "disabled"; 515107529cfSShawn Guo }; 516107529cfSShawn Guo 517107529cfSShawn Guo lsio_mu3: mailbox@5d1e0000 { 518107529cfSShawn Guo compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 519107529cfSShawn Guo reg = <0x5d1e0000 0x10000>; 520107529cfSShawn Guo interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 521107529cfSShawn Guo #mbox-cells = <2>; 522107529cfSShawn Guo status = "disabled"; 523107529cfSShawn Guo }; 524107529cfSShawn Guo 525107529cfSShawn Guo lsio_mu4: mailbox@5d1f0000 { 526107529cfSShawn Guo compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 527107529cfSShawn Guo reg = <0x5d1f0000 0x10000>; 528107529cfSShawn Guo interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 529107529cfSShawn Guo #mbox-cells = <2>; 530107529cfSShawn Guo status = "disabled"; 531107529cfSShawn Guo }; 532107529cfSShawn Guo 533107529cfSShawn Guo lsio_mu13: mailbox@5d280000 { 534107529cfSShawn Guo compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 535107529cfSShawn Guo reg = <0x5d280000 0x10000>; 536107529cfSShawn Guo interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 537107529cfSShawn Guo #mbox-cells = <2>; 538107529cfSShawn Guo power-domains = <&pd IMX_SC_R_MU_13A>; 539107529cfSShawn Guo }; 540107529cfSShawn Guo 541107529cfSShawn Guo lsio_lpcg: clock-controller@5d400000 { 542107529cfSShawn Guo compatible = "fsl,imx8qxp-lpcg-lsio"; 543107529cfSShawn Guo reg = <0x5d400000 0x400000>; 544107529cfSShawn Guo #clock-cells = <1>; 545107529cfSShawn Guo }; 5463d91ba65SAisheng Dong }; 5473d91ba65SAisheng Dong}; 548