1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017~2018 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8qxp.dtsi"
9
10/ {
11	model = "Freescale i.MX8QXP MEK";
12	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
13
14	chosen {
15		stdout-path = &adma_lpuart0;
16	};
17
18	memory@80000000 {
19		device_type = "memory";
20		reg = <0x00000000 0x80000000 0 0x40000000>;
21	};
22
23	reg_usdhc2_vmmc: usdhc2-vmmc {
24		compatible = "regulator-fixed";
25		regulator-name = "SD1_SPWR";
26		regulator-min-microvolt = <3000000>;
27		regulator-max-microvolt = <3000000>;
28		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
29		enable-active-high;
30	};
31};
32
33&adma_lpuart0 {
34	pinctrl-names = "default";
35	pinctrl-0 = <&pinctrl_lpuart0>;
36	status = "okay";
37};
38
39&fec1 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pinctrl_fec1>;
42	phy-mode = "rgmii-id";
43	phy-handle = <&ethphy0>;
44	fsl,magic-packet;
45	status = "okay";
46
47	mdio {
48		#address-cells = <1>;
49		#size-cells = <0>;
50
51		ethphy0: ethernet-phy@0 {
52			compatible = "ethernet-phy-ieee802.3-c22";
53			reg = <0>;
54		};
55
56		ethphy1: ethernet-phy@1 {
57			compatible = "ethernet-phy-ieee802.3-c22";
58			reg = <1>;
59		};
60	};
61};
62
63&adma_i2c1 {
64	#address-cells = <1>;
65	#size-cells = <0>;
66	clock-frequency = <100000>;
67	pinctrl-names = "default";
68	pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
69	status = "okay";
70
71	i2c-switch@71 {
72		compatible = "nxp,pca9646", "nxp,pca9546";
73		#address-cells = <1>;
74		#size-cells = <0>;
75		reg = <0x71>;
76		reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
77
78		i2c@0 {
79			#address-cells = <1>;
80			#size-cells = <0>;
81			reg = <0>;
82
83			max7322: gpio@68 {
84				compatible = "maxim,max7322";
85				reg = <0x68>;
86				gpio-controller;
87				#gpio-cells = <2>;
88			};
89		};
90
91		i2c@1 {
92			#address-cells = <1>;
93			#size-cells = <0>;
94			reg = <1>;
95		};
96
97		i2c@2 {
98			#address-cells = <1>;
99			#size-cells = <0>;
100			reg = <2>;
101
102			pressure-sensor@60 {
103				compatible = "fsl,mpl3115";
104				reg = <0x60>;
105			};
106		};
107
108		i2c@3 {
109			#address-cells = <1>;
110			#size-cells = <0>;
111			reg = <3>;
112
113			pca9557_a: gpio@1a {
114				compatible = "nxp,pca9557";
115				reg = <0x1a>;
116				gpio-controller;
117				#gpio-cells = <2>;
118			};
119
120			pca9557_b: gpio@1d {
121				compatible = "nxp,pca9557";
122				reg = <0x1d>;
123				gpio-controller;
124				#gpio-cells = <2>;
125			};
126
127			light-sensor@44 {
128				pinctrl-names = "default";
129				pinctrl-0 = <&pinctrl_isl29023>;
130				compatible = "isil,isl29023";
131				reg = <0x44>;
132				interrupt-parent = <&lsio_gpio1>;
133				interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
134			};
135		};
136	};
137};
138
139&usdhc1 {
140	pinctrl-names = "default";
141	pinctrl-0 = <&pinctrl_usdhc1>;
142	bus-width = <8>;
143	no-sd;
144	no-sdio;
145	non-removable;
146	status = "okay";
147};
148
149&usdhc2 {
150	pinctrl-names = "default";
151	pinctrl-0 = <&pinctrl_usdhc2>;
152	bus-width = <4>;
153	vmmc-supply = <&reg_usdhc2_vmmc>;
154	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
155	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
156	status = "okay";
157};
158
159&iomuxc {
160	pinctrl_fec1: fec1grp {
161		fsl,pins = <
162			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
163			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
164			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
165			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
166			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
167			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
168			IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
169			IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
170			IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
171			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
172			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
173			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
174			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
175			IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
176		>;
177	};
178
179	pinctrl_ioexp_rst: ioexp_rst_grp {
180		fsl,pins = <
181			IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01			0x06000021
182		>;
183	};
184
185	pinctrl_isl29023: isl29023grp {
186		fsl,pins = <
187			IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02			0x00000021
188		>;
189	};
190
191	pinctrl_lpi2c1: lpi2c1grp {
192		fsl,pins = <
193			IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL			0x06000021
194			IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA			0x06000021
195		>;
196	};
197
198	pinctrl_lpuart0: lpuart0grp {
199		fsl,pins = <
200			IMX8QXP_UART0_RX_ADMA_UART0_RX				0x06000020
201			IMX8QXP_UART0_TX_ADMA_UART0_TX				0x06000020
202		>;
203	};
204
205	pinctrl_usdhc1: usdhc1grp {
206		fsl,pins = <
207			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
208			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
209			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
210			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
211			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
212			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
213			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
214			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
215			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
216			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
217			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
218		>;
219	};
220
221	pinctrl_usdhc2: usdhc2grp {
222		fsl,pins = <
223			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
224			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
225			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
226			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
227			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
228			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
229			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
230		>;
231	};
232};
233