1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017~2018 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8qxp.dtsi"
9
10/ {
11	model = "Freescale i.MX8QXP MEK";
12	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
13
14	chosen {
15		stdout-path = &adma_lpuart0;
16	};
17
18	memory@80000000 {
19		device_type = "memory";
20		reg = <0x00000000 0x80000000 0 0x40000000>;
21	};
22
23	reg_usdhc2_vmmc: usdhc2-vmmc {
24		compatible = "regulator-fixed";
25		regulator-name = "SD1_SPWR";
26		regulator-min-microvolt = <3000000>;
27		regulator-max-microvolt = <3000000>;
28		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
29		enable-active-high;
30	};
31};
32
33&adma_lpuart0 {
34	pinctrl-names = "default";
35	pinctrl-0 = <&pinctrl_lpuart0>;
36	status = "okay";
37};
38
39&fec1 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pinctrl_fec1>;
42	phy-mode = "rgmii-id";
43	phy-handle = <&ethphy0>;
44	fsl,magic-packet;
45	status = "okay";
46
47	mdio {
48		#address-cells = <1>;
49		#size-cells = <0>;
50
51		ethphy0: ethernet-phy@0 {
52			compatible = "ethernet-phy-ieee802.3-c22";
53			reg = <0>;
54		};
55	};
56};
57
58&adma_i2c1 {
59	#address-cells = <1>;
60	#size-cells = <0>;
61	clock-frequency = <100000>;
62	pinctrl-names = "default";
63	pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
64	status = "okay";
65
66	i2c-switch@71 {
67		compatible = "nxp,pca9646", "nxp,pca9546";
68		#address-cells = <1>;
69		#size-cells = <0>;
70		reg = <0x71>;
71		reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
72
73		i2c@0 {
74			#address-cells = <1>;
75			#size-cells = <0>;
76			reg = <0>;
77
78			max7322: gpio@68 {
79				compatible = "maxim,max7322";
80				reg = <0x68>;
81				gpio-controller;
82				#gpio-cells = <2>;
83			};
84		};
85
86		i2c@1 {
87			#address-cells = <1>;
88			#size-cells = <0>;
89			reg = <1>;
90		};
91
92		i2c@2 {
93			#address-cells = <1>;
94			#size-cells = <0>;
95			reg = <2>;
96
97			pressure-sensor@60 {
98				compatible = "fsl,mpl3115";
99				reg = <0x60>;
100			};
101		};
102
103		i2c@3 {
104			#address-cells = <1>;
105			#size-cells = <0>;
106			reg = <3>;
107
108			pca9557_a: gpio@1a {
109				compatible = "nxp,pca9557";
110				reg = <0x1a>;
111				gpio-controller;
112				#gpio-cells = <2>;
113			};
114
115			pca9557_b: gpio@1d {
116				compatible = "nxp,pca9557";
117				reg = <0x1d>;
118				gpio-controller;
119				#gpio-cells = <2>;
120			};
121
122			light-sensor@44 {
123				pinctrl-names = "default";
124				pinctrl-0 = <&pinctrl_isl29023>;
125				compatible = "isil,isl29023";
126				reg = <0x44>;
127				interrupt-parent = <&lsio_gpio1>;
128				interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
129			};
130		};
131	};
132};
133
134&usdhc1 {
135	assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
136	assigned-clock-rates = <200000000>;
137	pinctrl-names = "default";
138	pinctrl-0 = <&pinctrl_usdhc1>;
139	bus-width = <8>;
140	no-sd;
141	no-sdio;
142	non-removable;
143	status = "okay";
144};
145
146&usdhc2 {
147	assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
148	assigned-clock-rates = <200000000>;
149	pinctrl-names = "default";
150	pinctrl-0 = <&pinctrl_usdhc2>;
151	bus-width = <4>;
152	vmmc-supply = <&reg_usdhc2_vmmc>;
153	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
154	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
155	status = "okay";
156};
157
158&iomuxc {
159	pinctrl_fec1: fec1grp {
160		fsl,pins = <
161			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
162			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
163			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
164			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
165			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
166			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
167			IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
168			IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
169			IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
170			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
171			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
172			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
173			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
174			IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
175		>;
176	};
177
178	pinctrl_ioexp_rst: ioexp_rst_grp {
179		fsl,pins = <
180			IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01			0x06000021
181		>;
182	};
183
184	pinctrl_isl29023: isl29023grp {
185		fsl,pins = <
186			IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02			0x00000021
187		>;
188	};
189
190	pinctrl_lpi2c1: lpi2c1grp {
191		fsl,pins = <
192			IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL			0x06000021
193			IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA			0x06000021
194		>;
195	};
196
197	pinctrl_lpuart0: lpuart0grp {
198		fsl,pins = <
199			IMX8QXP_UART0_RX_ADMA_UART0_RX				0x06000020
200			IMX8QXP_UART0_TX_ADMA_UART0_TX				0x06000020
201		>;
202	};
203
204	pinctrl_usdhc1: usdhc1grp {
205		fsl,pins = <
206			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
207			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
208			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
209			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
210			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
211			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
212			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
213			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
214			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
215			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
216			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
217		>;
218	};
219
220	pinctrl_usdhc2: usdhc2grp {
221		fsl,pins = <
222			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
223			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
224			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
225			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
226			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
227			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
228			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
229		>;
230	};
231};
232
233&adma_dsp {
234	status = "okay";
235};
236
237&scu_key {
238	status = "okay";
239};
240