1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017~2018 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8qxp.dtsi"
9
10/ {
11	model = "Freescale i.MX8QXP MEK";
12	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
13
14	chosen {
15		stdout-path = &adma_lpuart0;
16	};
17
18	memory@80000000 {
19		device_type = "memory";
20		reg = <0x00000000 0x80000000 0 0x40000000>;
21	};
22
23	reg_usdhc2_vmmc: usdhc2-vmmc {
24		compatible = "regulator-fixed";
25		regulator-name = "SD1_SPWR";
26		regulator-min-microvolt = <3000000>;
27		regulator-max-microvolt = <3000000>;
28		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
29		enable-active-high;
30	};
31};
32
33&adma_lpuart0 {
34	pinctrl-names = "default";
35	pinctrl-0 = <&pinctrl_lpuart0>;
36	status = "okay";
37};
38
39&fec1 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pinctrl_fec1>;
42	phy-mode = "rgmii-id";
43	phy-handle = <&ethphy0>;
44	fsl,magic-packet;
45	status = "okay";
46
47	mdio {
48		#address-cells = <1>;
49		#size-cells = <0>;
50
51		ethphy0: ethernet-phy@0 {
52			compatible = "ethernet-phy-ieee802.3-c22";
53			reg = <0>;
54		};
55
56		ethphy1: ethernet-phy@1 {
57			compatible = "ethernet-phy-ieee802.3-c22";
58			reg = <1>;
59		};
60	};
61};
62
63&usdhc1 {
64	pinctrl-names = "default";
65	pinctrl-0 = <&pinctrl_usdhc1>;
66	bus-width = <8>;
67	no-sd;
68	no-sdio;
69	non-removable;
70	status = "okay";
71};
72
73&usdhc2 {
74	pinctrl-names = "default";
75	pinctrl-0 = <&pinctrl_usdhc2>;
76	bus-width = <4>;
77	vmmc-supply = <&reg_usdhc2_vmmc>;
78	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
79	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
80	status = "okay";
81};
82
83&iomuxc {
84	pinctrl_fec1: fec1grp {
85		fsl,pins = <
86			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
87			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
88			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
89			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
90			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
91			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
92			IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
93			IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
94			IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
95			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
96			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
97			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
98			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
99			IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
100		>;
101	};
102
103	pinctrl_lpuart0: lpuart0grp {
104		fsl,pins = <
105			IMX8QXP_UART0_RX_ADMA_UART0_RX				0x06000020
106			IMX8QXP_UART0_TX_ADMA_UART0_TX				0x06000020
107		>;
108	};
109
110	pinctrl_usdhc1: usdhc1grp {
111		fsl,pins = <
112			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
113			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
114			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
115			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
116			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
117			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
118			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
119			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
120			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
121			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
122			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
123		>;
124	};
125
126	pinctrl_usdhc2: usdhc2grp {
127		fsl,pins = <
128			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
129			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
130			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
131			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
132			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
133			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
134			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
135		>;
136	};
137};
138