1ba5a5615SMarcel Ziswiler// SPDX-License-Identifier: GPL-2.0+ OR MIT
2ba5a5615SMarcel Ziswiler/*
3ba5a5615SMarcel Ziswiler * Copyright 2019 Toradex
4ba5a5615SMarcel Ziswiler */
5ba5a5615SMarcel Ziswiler
6ba5a5615SMarcel Ziswiler#include "imx8qxp.dtsi"
7ba5a5615SMarcel Ziswiler
8ba5a5615SMarcel Ziswiler/ {
9ba5a5615SMarcel Ziswiler	model = "Toradex Colibri iMX8QXP/DX Module";
10ba5a5615SMarcel Ziswiler	compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
11ba5a5615SMarcel Ziswiler
12ba5a5615SMarcel Ziswiler	chosen {
13ba5a5615SMarcel Ziswiler		stdout-path = &adma_lpuart3;
14ba5a5615SMarcel Ziswiler	};
15ba5a5615SMarcel Ziswiler
16ba5a5615SMarcel Ziswiler	reg_module_3v3: regulator-module-3v3 {
17ba5a5615SMarcel Ziswiler		compatible = "regulator-fixed";
18ba5a5615SMarcel Ziswiler		regulator-name = "+V3.3";
19ba5a5615SMarcel Ziswiler		regulator-min-microvolt = <3300000>;
20ba5a5615SMarcel Ziswiler		regulator-max-microvolt = <3300000>;
21ba5a5615SMarcel Ziswiler	};
22ba5a5615SMarcel Ziswiler};
23ba5a5615SMarcel Ziswiler
24ba5a5615SMarcel Ziswiler/* On-module I2C */
25ba5a5615SMarcel Ziswiler&adma_i2c0 {
26ba5a5615SMarcel Ziswiler	#address-cells = <1>;
27ba5a5615SMarcel Ziswiler	#size-cells = <0>;
28ba5a5615SMarcel Ziswiler	clock-frequency = <100000>;
29ba5a5615SMarcel Ziswiler	pinctrl-names = "default";
30ba5a5615SMarcel Ziswiler	pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
31ba5a5615SMarcel Ziswiler	status = "okay";
32ba5a5615SMarcel Ziswiler
33ba5a5615SMarcel Ziswiler	/* Touch controller */
34ba5a5615SMarcel Ziswiler	touchscreen@2c {
35ba5a5615SMarcel Ziswiler		compatible = "adi,ad7879-1";
36ba5a5615SMarcel Ziswiler		pinctrl-names = "default";
37ba5a5615SMarcel Ziswiler		pinctrl-0 = <&pinctrl_ad7879_int>;
38ba5a5615SMarcel Ziswiler		reg = <0x2c>;
39ba5a5615SMarcel Ziswiler		interrupt-parent = <&lsio_gpio3>;
40ba5a5615SMarcel Ziswiler		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
41ba5a5615SMarcel Ziswiler		touchscreen-max-pressure = <4096>;
42ba5a5615SMarcel Ziswiler		adi,resistance-plate-x = <120>;
43ba5a5615SMarcel Ziswiler		adi,first-conversion-delay = /bits/ 8 <3>;
44ba5a5615SMarcel Ziswiler		adi,acquisition-time = /bits/ 8 <1>;
45ba5a5615SMarcel Ziswiler		adi,median-filter-size = /bits/ 8 <2>;
46ba5a5615SMarcel Ziswiler		adi,averaging = /bits/ 8 <1>;
47ba5a5615SMarcel Ziswiler		adi,conversion-interval = /bits/ 8 <255>;
48ba5a5615SMarcel Ziswiler	};
49ba5a5615SMarcel Ziswiler};
50ba5a5615SMarcel Ziswiler
51ba5a5615SMarcel Ziswiler/* Colibri I2C */
52ba5a5615SMarcel Ziswiler&adma_i2c1 {
53ba5a5615SMarcel Ziswiler	#address-cells = <1>;
54ba5a5615SMarcel Ziswiler	#size-cells = <0>;
55ba5a5615SMarcel Ziswiler	clock-frequency = <100000>;
56ba5a5615SMarcel Ziswiler	pinctrl-names = "default";
57ba5a5615SMarcel Ziswiler	pinctrl-0 = <&pinctrl_i2c1>;
58ba5a5615SMarcel Ziswiler};
59ba5a5615SMarcel Ziswiler
60ba5a5615SMarcel Ziswiler/* Colibri UART_B */
61ba5a5615SMarcel Ziswiler&adma_lpuart0 {
62ba5a5615SMarcel Ziswiler	pinctrl-names = "default";
63ba5a5615SMarcel Ziswiler	pinctrl-0 = <&pinctrl_lpuart0>;
64ba5a5615SMarcel Ziswiler};
65ba5a5615SMarcel Ziswiler
66ba5a5615SMarcel Ziswiler/* Colibri UART_C */
67ba5a5615SMarcel Ziswiler&adma_lpuart2 {
68ba5a5615SMarcel Ziswiler	pinctrl-names = "default";
69ba5a5615SMarcel Ziswiler	pinctrl-0 = <&pinctrl_lpuart2>;
70ba5a5615SMarcel Ziswiler};
71ba5a5615SMarcel Ziswiler
72ba5a5615SMarcel Ziswiler/* Colibri UART_A */
73ba5a5615SMarcel Ziswiler&adma_lpuart3 {
74ba5a5615SMarcel Ziswiler	pinctrl-names = "default";
75ba5a5615SMarcel Ziswiler	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
76ba5a5615SMarcel Ziswiler};
77ba5a5615SMarcel Ziswiler
78ba5a5615SMarcel Ziswiler/* Colibri FastEthernet */
79ba5a5615SMarcel Ziswiler&fec1 {
80ba5a5615SMarcel Ziswiler	pinctrl-names = "default", "sleep";
81ba5a5615SMarcel Ziswiler	pinctrl-0 = <&pinctrl_fec1>;
82ba5a5615SMarcel Ziswiler	pinctrl-1 = <&pinctrl_fec1_sleep>;
83ba5a5615SMarcel Ziswiler	phy-mode = "rmii";
84ba5a5615SMarcel Ziswiler	phy-handle = <&ethphy0>;
85ba5a5615SMarcel Ziswiler	fsl,magic-packet;
86ba5a5615SMarcel Ziswiler
87ba5a5615SMarcel Ziswiler	mdio {
88ba5a5615SMarcel Ziswiler		#address-cells = <1>;
89ba5a5615SMarcel Ziswiler		#size-cells = <0>;
90ba5a5615SMarcel Ziswiler
91ba5a5615SMarcel Ziswiler		ethphy0: ethernet-phy@2 {
92ba5a5615SMarcel Ziswiler			compatible = "ethernet-phy-ieee802.3-c22";
93ba5a5615SMarcel Ziswiler			max-speed = <100>;
94ba5a5615SMarcel Ziswiler			reg = <2>;
95ba5a5615SMarcel Ziswiler		};
96ba5a5615SMarcel Ziswiler	};
97ba5a5615SMarcel Ziswiler};
98ba5a5615SMarcel Ziswiler
99ba5a5615SMarcel Ziswiler/* On-module eMMC */
100ba5a5615SMarcel Ziswiler&usdhc1 {
101ba5a5615SMarcel Ziswiler	bus-width = <8>;
102ba5a5615SMarcel Ziswiler	non-removable;
103ba5a5615SMarcel Ziswiler	no-sd;
104ba5a5615SMarcel Ziswiler	no-sdio;
105ba5a5615SMarcel Ziswiler	pinctrl-names = "default", "state_100mhz", "state_200mhz";
106ba5a5615SMarcel Ziswiler	pinctrl-0 = <&pinctrl_usdhc1>;
107ba5a5615SMarcel Ziswiler	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
108ba5a5615SMarcel Ziswiler	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
109ba5a5615SMarcel Ziswiler	status = "okay";
110ba5a5615SMarcel Ziswiler};
111ba5a5615SMarcel Ziswiler
112ba5a5615SMarcel Ziswiler/* Colibri SD/MMC Card */
113ba5a5615SMarcel Ziswiler&usdhc2 {
114ba5a5615SMarcel Ziswiler	bus-width = <4>;
115ba5a5615SMarcel Ziswiler	cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
116ba5a5615SMarcel Ziswiler	vmmc-supply = <&reg_module_3v3>;
117ba5a5615SMarcel Ziswiler	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
118ba5a5615SMarcel Ziswiler	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
119ba5a5615SMarcel Ziswiler	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
120ba5a5615SMarcel Ziswiler	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
121ba5a5615SMarcel Ziswiler	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
122ba5a5615SMarcel Ziswiler	disable-wp;
123ba5a5615SMarcel Ziswiler};
124ba5a5615SMarcel Ziswiler
125ba5a5615SMarcel Ziswiler&iomuxc {
126ba5a5615SMarcel Ziswiler	pinctrl-names = "default";
127ba5a5615SMarcel Ziswiler	pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;
128ba5a5615SMarcel Ziswiler
129ba5a5615SMarcel Ziswiler	/* On-module touch pen-down interrupt */
130ba5a5615SMarcel Ziswiler	pinctrl_ad7879_int: ad7879intgrp {
131ba5a5615SMarcel Ziswiler		fsl,pins = <
132ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05	0x21
133ba5a5615SMarcel Ziswiler		>;
134ba5a5615SMarcel Ziswiler	};
135ba5a5615SMarcel Ziswiler
136ba5a5615SMarcel Ziswiler	/* Colibri Analogue Inputs */
137ba5a5615SMarcel Ziswiler	pinctrl_adc0: adc0grp {
138ba5a5615SMarcel Ziswiler		fsl,pins = <
139ba5a5615SMarcel Ziswiler			IMX8QXP_ADC_IN0_ADMA_ADC_IN0			0x60		/* SODIMM   8 */
140ba5a5615SMarcel Ziswiler			IMX8QXP_ADC_IN1_ADMA_ADC_IN1			0x60		/* SODIMM   6 */
141ba5a5615SMarcel Ziswiler			IMX8QXP_ADC_IN4_ADMA_ADC_IN4			0x60		/* SODIMM   4 */
142ba5a5615SMarcel Ziswiler			IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60		/* SODIMM   2 */
143ba5a5615SMarcel Ziswiler		>;
144ba5a5615SMarcel Ziswiler	};
145ba5a5615SMarcel Ziswiler
146ba5a5615SMarcel Ziswiler	pinctrl_can_int: canintgrp {
147ba5a5615SMarcel Ziswiler		fsl,pins = <
148ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13		0x40		/* SODIMM  73 */
149ba5a5615SMarcel Ziswiler		>;
150ba5a5615SMarcel Ziswiler	};
151ba5a5615SMarcel Ziswiler
152ba5a5615SMarcel Ziswiler	pinctrl_csi_ctl: csictlgrp {
153ba5a5615SMarcel Ziswiler		fsl,pins = <
154ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14		0x20		/* SODIMM  77 */
155ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15		0x20		/* SODIMM  89 */
156ba5a5615SMarcel Ziswiler		>;
157ba5a5615SMarcel Ziswiler	};
158ba5a5615SMarcel Ziswiler
159ba5a5615SMarcel Ziswiler	pinctrl_ext_io0: extio0grp {
160ba5a5615SMarcel Ziswiler		fsl,pins = <
161ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08	0x06000040	/* SODIMM 135 */
162ba5a5615SMarcel Ziswiler		>;
163ba5a5615SMarcel Ziswiler	};
164ba5a5615SMarcel Ziswiler
165ba5a5615SMarcel Ziswiler	/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
166ba5a5615SMarcel Ziswiler	pinctrl_fec1: fec1grp {
167ba5a5615SMarcel Ziswiler		fsl,pins = <
168ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
169ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
170ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61
171ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT		0x06000061
172ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x61
173ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x61
174ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61
175ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x61
176ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x61
177ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER		0x61
178ba5a5615SMarcel Ziswiler		>;
179ba5a5615SMarcel Ziswiler	};
180ba5a5615SMarcel Ziswiler
181ba5a5615SMarcel Ziswiler	pinctrl_fec1_sleep: fec1slpgrp {
182ba5a5615SMarcel Ziswiler		fsl,pins = <
183ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11		0x06000041
184ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10		0x06000041
185ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x41
186ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x41
187ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31	0x41
188ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x41
189ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04	0x41
190ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05	0x41
191ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06	0x41
192ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07	0x41
193ba5a5615SMarcel Ziswiler		>;
194ba5a5615SMarcel Ziswiler	};
195ba5a5615SMarcel Ziswiler
196ba5a5615SMarcel Ziswiler	/* Colibri optional CAN on UART_B RTS/CTS */
197ba5a5615SMarcel Ziswiler	pinctrl_flexcan1: flexcan0grp {
198ba5a5615SMarcel Ziswiler		fsl,pins = <
199ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21		/* SODIMM  32 */
200ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21		/* SODIMM  34 */
201ba5a5615SMarcel Ziswiler		>;
202ba5a5615SMarcel Ziswiler	};
203ba5a5615SMarcel Ziswiler
204ba5a5615SMarcel Ziswiler	/* Colibri optional CAN on PS2 */
205ba5a5615SMarcel Ziswiler	pinctrl_flexcan2: flexcan1grp {
206ba5a5615SMarcel Ziswiler		fsl,pins = <
207ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21		/* SODIMM  55 */
208ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21		/* SODIMM  63 */
209ba5a5615SMarcel Ziswiler		>;
210ba5a5615SMarcel Ziswiler	};
211ba5a5615SMarcel Ziswiler
212ba5a5615SMarcel Ziswiler	/* Colibri optional CAN on UART_A TXD/RXD */
213ba5a5615SMarcel Ziswiler	pinctrl_flexcan3: flexcan2grp {
214ba5a5615SMarcel Ziswiler		fsl,pins = <
215ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX		0x21		/* SODIMM  35 */
216ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX		0x21		/* SODIMM  33 */
217ba5a5615SMarcel Ziswiler		>;
218ba5a5615SMarcel Ziswiler	};
219ba5a5615SMarcel Ziswiler
220ba5a5615SMarcel Ziswiler	/* Colibri LCD Back-Light GPIO */
221ba5a5615SMarcel Ziswiler	pinctrl_gpio_bl_on: gpioblongrp {
222ba5a5615SMarcel Ziswiler		fsl,pins = <
223ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12		0x60		/* SODIMM  71 */
224ba5a5615SMarcel Ziswiler		>;
225ba5a5615SMarcel Ziswiler	};
226ba5a5615SMarcel Ziswiler
227ba5a5615SMarcel Ziswiler	pinctrl_gpiokeys: gpiokeysgrp {
228ba5a5615SMarcel Ziswiler		fsl,pins = <
229ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10		0x06700041	/* SODIMM  45 */
230ba5a5615SMarcel Ziswiler		>;
231ba5a5615SMarcel Ziswiler	};
232ba5a5615SMarcel Ziswiler
233ba5a5615SMarcel Ziswiler	pinctrl_hog0: hog0grp {
234ba5a5615SMarcel Ziswiler		fsl,pins = <
235ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x06000020	/* SODIMM  65 */
236ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_D07_CI_PI_D09			0x61		/* SODIMM  65 */
237ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20		/* SODIMM  69 */
238ba5a5615SMarcel Ziswiler			IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26		0x20		/* SODIMM  79 */
239ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_D02_CI_PI_D04			0x61		/* SODIMM  79 */
240ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03		0x06000020	/* SODIMM  85 */
241ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_D06_CI_PI_D08			0x61		/* SODIMM  85 */
242ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17		0x20		/* SODIMM  95 */
243ba5a5615SMarcel Ziswiler			IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27		0x20		/* SODIMM  97 */
244ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_D03_CI_PI_D05			0x61		/* SODIMM  97 */
245ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20		/* SODIMM  99 */
246ba5a5615SMarcel Ziswiler			IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28		0x20		/* SODIMM 101 */
247ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_D00_CI_PI_D02			0x61		/* SODIMM 101 */
248ba5a5615SMarcel Ziswiler			IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25		0x20		/* SODIMM 103 */
249ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_D01_CI_PI_D03			0x61		/* SODIMM 103 */
250ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20		/* SODIMM 105 */
251ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x20		/* SODIMM 107 */
252ba5a5615SMarcel Ziswiler			IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05		0x20		/* SODIMM 127 */
253ba5a5615SMarcel Ziswiler			IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06		0x20		/* SODIMM 131 */
254ba5a5615SMarcel Ziswiler			IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04		0x20		/* SODIMM 133 */
255ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00		0x20		/* SODIMM  96 */
256ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20		/* SODIMM  98 */
257ba5a5615SMarcel Ziswiler			IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31		0x20		/* SODIMM 100 */
258ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22		0x20		/* SODIMM 102 */
259ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20		/* SODIMM 104 */
260ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x20		/* SODIMM 106 */
261ba5a5615SMarcel Ziswiler		>;
262ba5a5615SMarcel Ziswiler	};
263ba5a5615SMarcel Ziswiler
264ba5a5615SMarcel Ziswiler	pinctrl_hog1: hog1grp {
265ba5a5615SMarcel Ziswiler		fsl,pins = <
266ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01		0x20		/* SODIMM  75 */
267ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16		0x20		/* SODIMM  93 */
268ba5a5615SMarcel Ziswiler		>;
269ba5a5615SMarcel Ziswiler	};
270ba5a5615SMarcel Ziswiler
271ba5a5615SMarcel Ziswiler	/*
272ba5a5615SMarcel Ziswiler	 * This pin is used in the SCFW as a UART. Using it from
273ba5a5615SMarcel Ziswiler	 * Linux would require rewritting the SCFW board file.
274ba5a5615SMarcel Ziswiler	 */
275ba5a5615SMarcel Ziswiler	pinctrl_hog_scfw: hogscfwgrp {
276ba5a5615SMarcel Ziswiler		fsl,pins = <
277ba5a5615SMarcel Ziswiler			IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03		0x20		/* SODIMM 144 */
278ba5a5615SMarcel Ziswiler		>;
279ba5a5615SMarcel Ziswiler	};
280ba5a5615SMarcel Ziswiler
281ba5a5615SMarcel Ziswiler	/* On Module I2C */
282ba5a5615SMarcel Ziswiler	pinctrl_i2c0: i2c0grp {
283ba5a5615SMarcel Ziswiler		fsl,pins = <
284ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x06000021
285ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x06000021
286ba5a5615SMarcel Ziswiler		>;
287ba5a5615SMarcel Ziswiler	};
288ba5a5615SMarcel Ziswiler
289ba5a5615SMarcel Ziswiler	/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
290ba5a5615SMarcel Ziswiler	pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
291ba5a5615SMarcel Ziswiler		fsl,pins = <
292ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0xc6000020	/* SODIMM 140 */
293ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0xc6000020	/* SODIMM 142 */
294ba5a5615SMarcel Ziswiler		>;
295ba5a5615SMarcel Ziswiler	};
296ba5a5615SMarcel Ziswiler
297ba5a5615SMarcel Ziswiler	/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
298ba5a5615SMarcel Ziswiler	pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
299ba5a5615SMarcel Ziswiler		fsl,pins = <
300ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL	0xc6000020	/* SODIMM 186 */
301ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA	0xc6000020	/* SODIMM 188 */
302ba5a5615SMarcel Ziswiler		>;
303ba5a5615SMarcel Ziswiler	};
304ba5a5615SMarcel Ziswiler
305ba5a5615SMarcel Ziswiler	/* Colibri I2C */
306ba5a5615SMarcel Ziswiler	pinctrl_i2c1: i2c1grp {
307ba5a5615SMarcel Ziswiler		fsl,pins = <
308ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021	/* SODIMM 196 */
309ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021	/* SODIMM 194 */
310ba5a5615SMarcel Ziswiler		>;
311ba5a5615SMarcel Ziswiler	};
312ba5a5615SMarcel Ziswiler
313ba5a5615SMarcel Ziswiler	/* Colibri Parallel RGB LCD Interface */
314ba5a5615SMarcel Ziswiler	pinctrl_lcdif: lcdifgrp {
315ba5a5615SMarcel Ziswiler		fsl,pins = <
316ba5a5615SMarcel Ziswiler			IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK		0x60		/* SODIMM  56 */
317ba5a5615SMarcel Ziswiler			IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC		0x60		/* SODIMM  68 */
318ba5a5615SMarcel Ziswiler			IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC		0x60		/* SODIMM  82 */
319ba5a5615SMarcel Ziswiler			IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x60		/* SODIMM  44 */
320ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x60		/* SODIMM  44 */
321ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00		0x60		/* SODIMM  76 */
322ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x60		/* SODIMM  76 */
323ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01		0x60		/* SODIMM  70 */
324ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02		0x60		/* SODIMM  60 */
325ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03		0x60		/* SODIMM  58 */
326ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04		0x60		/* SODIMM  78 */
327ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05		0x60		/* SODIMM  72 */
328ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06		0x60		/* SODIMM  80 */
329ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07		0x60		/* SODIMM  46 */
330ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08		0x60		/* SODIMM  62 */
331ba5a5615SMarcel Ziswiler			IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09		0x60		/* SODIMM  48 */
332ba5a5615SMarcel Ziswiler			IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10		0x60		/* SODIMM  74 */
333ba5a5615SMarcel Ziswiler			IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11		0x60		/* SODIMM  50 */
334ba5a5615SMarcel Ziswiler			IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12		0x60		/* SODIMM  52 */
335ba5a5615SMarcel Ziswiler			IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13			0x60		/* SODIMM  54 */
336ba5a5615SMarcel Ziswiler			IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14			0x60		/* SODIMM  66 */
337ba5a5615SMarcel Ziswiler			IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15			0x60		/* SODIMM  64 */
338ba5a5615SMarcel Ziswiler			IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16			0x60		/* SODIMM  57 */
339ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x60		/* SODIMM  57 */
340ba5a5615SMarcel Ziswiler			IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17		0x60		/* SODIMM  61 */
341ba5a5615SMarcel Ziswiler		>;
342ba5a5615SMarcel Ziswiler	};
343ba5a5615SMarcel Ziswiler
344ba5a5615SMarcel Ziswiler	/* Colibri SPI */
345ba5a5615SMarcel Ziswiler	pinctrl_lpspi2: lpspi2grp {
346ba5a5615SMarcel Ziswiler		fsl,pins = <
347ba5a5615SMarcel Ziswiler			IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00		0x21		/* SODIMM  86 */
348ba5a5615SMarcel Ziswiler			IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO			0x06000040	/* SODIMM  92 */
349ba5a5615SMarcel Ziswiler			IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI			0x06000040	/* SODIMM  90 */
350ba5a5615SMarcel Ziswiler			IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK			0x06000040	/* SODIMM  88 */
351ba5a5615SMarcel Ziswiler		>;
352ba5a5615SMarcel Ziswiler	};
353ba5a5615SMarcel Ziswiler
354ba5a5615SMarcel Ziswiler	/* Colibri UART_B */
355ba5a5615SMarcel Ziswiler	pinctrl_lpuart0: lpuart0grp {
356ba5a5615SMarcel Ziswiler		fsl,pins = <
357ba5a5615SMarcel Ziswiler			IMX8QXP_UART0_RX_ADMA_UART0_RX			0x06000020	/* SODIMM  36 */
358ba5a5615SMarcel Ziswiler			IMX8QXP_UART0_TX_ADMA_UART0_TX			0x06000020	/* SODIMM  38 */
359ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B		0x06000020	/* SODIMM  34 */
360ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B		0x06000020	/* SODIMM  32 */
361ba5a5615SMarcel Ziswiler		>;
362ba5a5615SMarcel Ziswiler	};
363ba5a5615SMarcel Ziswiler
364ba5a5615SMarcel Ziswiler	/* Colibri UART_C */
365ba5a5615SMarcel Ziswiler	pinctrl_lpuart2: lpuart2grp {
366ba5a5615SMarcel Ziswiler		fsl,pins = <
367ba5a5615SMarcel Ziswiler			IMX8QXP_UART2_RX_ADMA_UART2_RX			0x06000020	/* SODIMM  19 */
368ba5a5615SMarcel Ziswiler			IMX8QXP_UART2_TX_ADMA_UART2_TX			0x06000020	/* SODIMM  21 */
369ba5a5615SMarcel Ziswiler		>;
370ba5a5615SMarcel Ziswiler	};
371ba5a5615SMarcel Ziswiler
372ba5a5615SMarcel Ziswiler	/* Colibri UART_A */
373ba5a5615SMarcel Ziswiler	pinctrl_lpuart3: lpuart3grp {
374ba5a5615SMarcel Ziswiler		fsl,pins = <
375ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX		0x06000020	/* SODIMM  33 */
376ba5a5615SMarcel Ziswiler			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX		0x06000020	/* SODIMM  35 */
377ba5a5615SMarcel Ziswiler		>;
378ba5a5615SMarcel Ziswiler	};
379ba5a5615SMarcel Ziswiler
380ba5a5615SMarcel Ziswiler	/* Colibri UART_A Control */
381ba5a5615SMarcel Ziswiler	pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
382ba5a5615SMarcel Ziswiler		fsl,pins = <
383ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0x20		/* SODIMM  23 */
384ba5a5615SMarcel Ziswiler			IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29		0x20		/* SODIMM  25 */
385ba5a5615SMarcel Ziswiler			IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30		0x20		/* SODIMM  27 */
386ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x20		/* SODIMM  29 */
387ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22		0x20		/* SODIMM  31 */
388ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_EN_LSIO_GPIO3_IO02			0x20		/* SODIMM  37 */
389ba5a5615SMarcel Ziswiler		>;
390ba5a5615SMarcel Ziswiler	};
391ba5a5615SMarcel Ziswiler
392ba5a5615SMarcel Ziswiler	/* On module wifi module */
393ba5a5615SMarcel Ziswiler	pinctrl_pcieb: pciebgrp {
394ba5a5615SMarcel Ziswiler		fsl,pins = <
395ba5a5615SMarcel Ziswiler			IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x04000061	/* SODIMM 178 */
396ba5a5615SMarcel Ziswiler			IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02	0x04000061	/* SODIMM  94 */
397ba5a5615SMarcel Ziswiler			IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00	0x60		/* SODIMM  81 */
398ba5a5615SMarcel Ziswiler		>;
399ba5a5615SMarcel Ziswiler	};
400ba5a5615SMarcel Ziswiler
401ba5a5615SMarcel Ziswiler	/* Colibri PWM_A */
402ba5a5615SMarcel Ziswiler	pinctrl_pwm_a: pwmagrp {
403ba5a5615SMarcel Ziswiler	/* both pins are connected together, reserve the unused CSI_D05 */
404ba5a5615SMarcel Ziswiler		fsl,pins = <
405ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_D05_CI_PI_D07			0x61		/* SODIMM  59 */
406ba5a5615SMarcel Ziswiler			IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT		0x60		/* SODIMM  59 */
407ba5a5615SMarcel Ziswiler		>;
408ba5a5615SMarcel Ziswiler	};
409ba5a5615SMarcel Ziswiler
410ba5a5615SMarcel Ziswiler	/* Colibri PWM_B */
411ba5a5615SMarcel Ziswiler	pinctrl_pwm_b: pwmbgrp {
412ba5a5615SMarcel Ziswiler		fsl,pins = <
413ba5a5615SMarcel Ziswiler			IMX8QXP_UART1_TX_LSIO_PWM0_OUT			0x60		/* SODIMM  28 */
414ba5a5615SMarcel Ziswiler		>;
415ba5a5615SMarcel Ziswiler	};
416ba5a5615SMarcel Ziswiler
417ba5a5615SMarcel Ziswiler	/* Colibri PWM_C */
418ba5a5615SMarcel Ziswiler	pinctrl_pwm_c: pwmcgrp {
419ba5a5615SMarcel Ziswiler		fsl,pins = <
420ba5a5615SMarcel Ziswiler			IMX8QXP_UART1_RX_LSIO_PWM1_OUT			0x60		/* SODIMM  30 */
421ba5a5615SMarcel Ziswiler		>;
422ba5a5615SMarcel Ziswiler	};
423ba5a5615SMarcel Ziswiler
424ba5a5615SMarcel Ziswiler	/* Colibri PWM_D */
425ba5a5615SMarcel Ziswiler	pinctrl_pwm_d: pwmdgrp {
426ba5a5615SMarcel Ziswiler	/* both pins are connected together, reserve the unused CSI_D04 */
427ba5a5615SMarcel Ziswiler		fsl,pins = <
428ba5a5615SMarcel Ziswiler			IMX8QXP_CSI_D04_CI_PI_D06			0x61		/* SODIMM  67 */
429ba5a5615SMarcel Ziswiler			IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT		0x60		/* SODIMM  67 */
430ba5a5615SMarcel Ziswiler		>;
431ba5a5615SMarcel Ziswiler	};
432ba5a5615SMarcel Ziswiler
433ba5a5615SMarcel Ziswiler	/* On-module I2S */
434ba5a5615SMarcel Ziswiler	pinctrl_sai0: sai0grp {
435ba5a5615SMarcel Ziswiler		fsl,pins = <
436ba5a5615SMarcel Ziswiler			IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD			0x06000040
437ba5a5615SMarcel Ziswiler			IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD			0x06000040
438ba5a5615SMarcel Ziswiler			IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC			0x06000040
439ba5a5615SMarcel Ziswiler			IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS			0x06000040
440ba5a5615SMarcel Ziswiler		>;
441ba5a5615SMarcel Ziswiler	};
442ba5a5615SMarcel Ziswiler
443ba5a5615SMarcel Ziswiler	/* Colibri Audio Analogue Microphone GND */
444ba5a5615SMarcel Ziswiler	pinctrl_sgtl5000: sgtl5000grp {
445ba5a5615SMarcel Ziswiler		fsl,pins = <
446ba5a5615SMarcel Ziswiler			/* MIC GND EN */
447ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06	0x41
448ba5a5615SMarcel Ziswiler		>;
449ba5a5615SMarcel Ziswiler	};
450ba5a5615SMarcel Ziswiler
451ba5a5615SMarcel Ziswiler	/* On-module SGTL5000 clock */
452ba5a5615SMarcel Ziswiler	pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
453ba5a5615SMarcel Ziswiler		fsl,pins = <
454ba5a5615SMarcel Ziswiler			IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0		0x21
455ba5a5615SMarcel Ziswiler		>;
456ba5a5615SMarcel Ziswiler	};
457ba5a5615SMarcel Ziswiler
458ba5a5615SMarcel Ziswiler	/* On-module USB interrupt */
459ba5a5615SMarcel Ziswiler	pinctrl_usb3503a: usb3503agrp {
460ba5a5615SMarcel Ziswiler		fsl,pins = <
461ba5a5615SMarcel Ziswiler			IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04	0x61
462ba5a5615SMarcel Ziswiler		>;
463ba5a5615SMarcel Ziswiler	};
464ba5a5615SMarcel Ziswiler
465ba5a5615SMarcel Ziswiler	/* Colibri USB Client Cable Detect */
466ba5a5615SMarcel Ziswiler	pinctrl_usbc_det: usbcdetgrp {
467ba5a5615SMarcel Ziswiler		fsl,pins = <
468ba5a5615SMarcel Ziswiler			IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040	/* SODIMM 137 */
469ba5a5615SMarcel Ziswiler		>;
470ba5a5615SMarcel Ziswiler	};
471ba5a5615SMarcel Ziswiler
472ba5a5615SMarcel Ziswiler	/* USB Host Power Enable */
473ba5a5615SMarcel Ziswiler	pinctrl_usbh1_reg: usbh1reggrp {
474ba5a5615SMarcel Ziswiler		fsl,pins = <
475ba5a5615SMarcel Ziswiler			IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03		0x06000040	/* SODIMM 129 */
476ba5a5615SMarcel Ziswiler		>;
477ba5a5615SMarcel Ziswiler	};
478ba5a5615SMarcel Ziswiler
479ba5a5615SMarcel Ziswiler	/* On-module eMMC */
480ba5a5615SMarcel Ziswiler	pinctrl_usdhc1: usdhc1grp {
481ba5a5615SMarcel Ziswiler		fsl,pins = <
482ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
483ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
484ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
485ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
486ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
487ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
488ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
489ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
490ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
491ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
492ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
493ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
494ba5a5615SMarcel Ziswiler		>;
495ba5a5615SMarcel Ziswiler	};
496ba5a5615SMarcel Ziswiler
497ba5a5615SMarcel Ziswiler	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
498ba5a5615SMarcel Ziswiler		fsl,pins = <
499ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
500ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
501ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
502ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
503ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
504ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
505ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
506ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
507ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
508ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
509ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
510ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
511ba5a5615SMarcel Ziswiler		>;
512ba5a5615SMarcel Ziswiler	};
513ba5a5615SMarcel Ziswiler
514ba5a5615SMarcel Ziswiler	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
515ba5a5615SMarcel Ziswiler		fsl,pins = <
516ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
517ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
518ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
519ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
520ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
521ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
522ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
523ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
524ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
525ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
526ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
527ba5a5615SMarcel Ziswiler			IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
528ba5a5615SMarcel Ziswiler		>;
529ba5a5615SMarcel Ziswiler	};
530ba5a5615SMarcel Ziswiler
531ba5a5615SMarcel Ziswiler	/* Colibri SD/MMC Card Detect */
532ba5a5615SMarcel Ziswiler	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
533ba5a5615SMarcel Ziswiler		fsl,pins = <
534ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x06000021	/* SODIMM  43 */
535ba5a5615SMarcel Ziswiler		>;
536ba5a5615SMarcel Ziswiler	};
537ba5a5615SMarcel Ziswiler
538ba5a5615SMarcel Ziswiler	pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
539ba5a5615SMarcel Ziswiler		fsl,pins = <
540ba5a5615SMarcel Ziswiler			IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x60		/* SODIMM  43 */
541ba5a5615SMarcel Ziswiler		>;
542ba5a5615SMarcel Ziswiler	};
543ba5a5615SMarcel Ziswiler
544ba5a5615SMarcel Ziswiler	/* Colibri SD/MMC Card */
545ba5a5615SMarcel Ziswiler	pinctrl_usdhc2: usdhc2grp {
546ba5a5615SMarcel Ziswiler		fsl,pins = <
547ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
548ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
549ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
550ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
551ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
552ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
553ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
554ba5a5615SMarcel Ziswiler		>;
555ba5a5615SMarcel Ziswiler	};
556ba5a5615SMarcel Ziswiler
557ba5a5615SMarcel Ziswiler	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
558ba5a5615SMarcel Ziswiler		fsl,pins = <
559ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
560ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
561ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
562ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
563ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
564ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
565ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
566ba5a5615SMarcel Ziswiler		>;
567ba5a5615SMarcel Ziswiler	};
568ba5a5615SMarcel Ziswiler
569ba5a5615SMarcel Ziswiler	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
570ba5a5615SMarcel Ziswiler		fsl,pins = <
571ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
572ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
573ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
574ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
575ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
576ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
577ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
578ba5a5615SMarcel Ziswiler		>;
579ba5a5615SMarcel Ziswiler	};
580ba5a5615SMarcel Ziswiler
581ba5a5615SMarcel Ziswiler	pinctrl_usdhc2_sleep: usdhc2slpgrp {
582ba5a5615SMarcel Ziswiler		fsl,pins = <
583ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23		0x60		/* SODIMM  47 */
584ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24		0x60		/* SODIMM 190 */
585ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60		/* SODIMM 192 */
586ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60		/* SODIMM  49 */
587ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60		/* SODIMM  51 */
588ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60		/* SODIMM  53 */
589ba5a5615SMarcel Ziswiler			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
590ba5a5615SMarcel Ziswiler		>;
591ba5a5615SMarcel Ziswiler	};
592ba5a5615SMarcel Ziswiler
593ba5a5615SMarcel Ziswiler	pinctrl_wifi: wifigrp {
594ba5a5615SMarcel Ziswiler		fsl,pins = <
595ba5a5615SMarcel Ziswiler			IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20
596ba5a5615SMarcel Ziswiler		>;
597ba5a5615SMarcel Ziswiler	};
598ba5a5615SMarcel Ziswiler};
599