1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/clock/imx8-lpcg.h>
8#include <dt-bindings/firmware/imx/rsrc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/pads-imx8qm.h>
12
13/ {
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	aliases {
19		mmc0 = &usdhc1;
20		mmc1 = &usdhc2;
21		mmc2 = &usdhc3;
22		serial0 = &lpuart0;
23		serial1 = &lpuart1;
24		serial2 = &lpuart2;
25		serial3 = &lpuart3;
26	};
27
28	cpus {
29		#address-cells = <2>;
30		#size-cells = <0>;
31
32		cpu-map {
33			cluster0 {
34				core0 {
35					cpu = <&A53_0>;
36				};
37				core1 {
38					cpu = <&A53_1>;
39				};
40				core2 {
41					cpu = <&A53_2>;
42				};
43				core3 {
44					cpu = <&A53_3>;
45				};
46			};
47
48			cluster1 {
49				core0 {
50					cpu = <&A72_0>;
51				};
52				core1 {
53					cpu = <&A72_1>;
54				};
55			};
56		};
57
58		A53_0: cpu@0 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a53";
61			reg = <0x0 0x0>;
62			enable-method = "psci";
63			i-cache-size = <0x8000>;
64			i-cache-line-size = <64>;
65			i-cache-sets = <256>;
66			d-cache-size = <0x8000>;
67			d-cache-line-size = <64>;
68			d-cache-sets = <128>;
69			next-level-cache = <&A53_L2>;
70		};
71
72		A53_1: cpu@1 {
73			device_type = "cpu";
74			compatible = "arm,cortex-a53";
75			reg = <0x0 0x1>;
76			enable-method = "psci";
77			i-cache-size = <0x8000>;
78			i-cache-line-size = <64>;
79			i-cache-sets = <256>;
80			d-cache-size = <0x8000>;
81			d-cache-line-size = <64>;
82			d-cache-sets = <128>;
83			next-level-cache = <&A53_L2>;
84		};
85
86		A53_2: cpu@2 {
87			device_type = "cpu";
88			compatible = "arm,cortex-a53";
89			reg = <0x0 0x2>;
90			enable-method = "psci";
91			i-cache-size = <0x8000>;
92			i-cache-line-size = <64>;
93			i-cache-sets = <256>;
94			d-cache-size = <0x8000>;
95			d-cache-line-size = <64>;
96			d-cache-sets = <128>;
97			next-level-cache = <&A53_L2>;
98		};
99
100		A53_3: cpu@3 {
101			device_type = "cpu";
102			compatible = "arm,cortex-a53";
103			reg = <0x0 0x3>;
104			enable-method = "psci";
105			i-cache-size = <0x8000>;
106			i-cache-line-size = <64>;
107			i-cache-sets = <256>;
108			d-cache-size = <0x8000>;
109			d-cache-line-size = <64>;
110			d-cache-sets = <128>;
111			next-level-cache = <&A53_L2>;
112		};
113
114		A72_0: cpu@100 {
115			device_type = "cpu";
116			compatible = "arm,cortex-a72";
117			reg = <0x0 0x100>;
118			enable-method = "psci";
119			i-cache-size = <0xC000>;
120			i-cache-line-size = <64>;
121			i-cache-sets = <256>;
122			d-cache-size = <0x8000>;
123			d-cache-line-size = <64>;
124			d-cache-sets = <256>;
125			next-level-cache = <&A72_L2>;
126		};
127
128		A72_1: cpu@101 {
129			device_type = "cpu";
130			compatible = "arm,cortex-a72";
131			reg = <0x0 0x101>;
132			enable-method = "psci";
133			next-level-cache = <&A72_L2>;
134		};
135
136		A53_L2: l2-cache0 {
137			compatible = "cache";
138			cache-level = <2>;
139			cache-size = <0x100000>;
140			cache-line-size = <64>;
141			cache-sets = <1024>;
142		};
143
144		A72_L2: l2-cache1 {
145			compatible = "cache";
146			cache-level = <2>;
147			cache-size = <0x100000>;
148			cache-line-size = <64>;
149			cache-sets = <1024>;
150		};
151	};
152
153	gic: interrupt-controller@51a00000 {
154		compatible = "arm,gic-v3";
155		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
156		      <0x0 0x51b00000 0 0xC0000>, /* GICR */
157		      <0x0 0x52000000 0 0x2000>,  /* GICC */
158		      <0x0 0x52010000 0 0x1000>,  /* GICH */
159		      <0x0 0x52020000 0 0x20000>; /* GICV */
160		#interrupt-cells = <3>;
161		interrupt-controller;
162		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
163		interrupt-parent = <&gic>;
164	};
165
166	pmu {
167		compatible = "arm,armv8-pmuv3";
168		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
169	};
170
171	psci {
172		compatible = "arm,psci-1.0";
173		method = "smc";
174	};
175
176	timer {
177		compatible = "arm,armv8-timer";
178		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
179			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
180			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
181			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
182	};
183
184	scu {
185		compatible = "fsl,imx-scu";
186		mbox-names = "tx0",
187			     "rx0",
188			     "gip3";
189		mboxes = <&lsio_mu1 0 0
190			  &lsio_mu1 1 0
191			  &lsio_mu1 3 3>;
192
193		pd: imx8qx-pd {
194			compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
195			#power-domain-cells = <1>;
196		};
197
198		clk: clock-controller {
199			compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
200			#clock-cells = <2>;
201		};
202
203		iomuxc: pinctrl {
204			compatible = "fsl,imx8qm-iomuxc";
205		};
206
207		rtc: rtc {
208			compatible = "fsl,imx8qxp-sc-rtc";
209		};
210	};
211
212	/* sorted in register address */
213	#include "imx8-ss-img.dtsi"
214	#include "imx8-ss-dma.dtsi"
215	#include "imx8-ss-conn.dtsi"
216	#include "imx8-ss-lsio.dtsi"
217};
218
219#include "imx8qm-ss-img.dtsi"
220#include "imx8qm-ss-dma.dtsi"
221#include "imx8qm-ss-conn.dtsi"
222#include "imx8qm-ss-lsio.dtsi"
223