1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7#include <dt-bindings/clock/imx8-lpcg.h>
8#include <dt-bindings/firmware/imx/rsrc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/pads-imx8qm.h>
12
13/ {
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	aliases {
19		mmc0 = &usdhc1;
20		mmc1 = &usdhc2;
21		mmc2 = &usdhc3;
22		serial0 = &lpuart0;
23	};
24
25	cpus {
26		#address-cells = <2>;
27		#size-cells = <0>;
28
29		cpu-map {
30			cluster0 {
31				core0 {
32					cpu = <&A53_0>;
33				};
34				core1 {
35					cpu = <&A53_1>;
36				};
37				core2 {
38					cpu = <&A53_2>;
39				};
40				core3 {
41					cpu = <&A53_3>;
42				};
43			};
44
45			cluster1 {
46				core0 {
47					cpu = <&A72_0>;
48				};
49				core1 {
50					cpu = <&A72_1>;
51				};
52			};
53		};
54
55		A53_0: cpu@0 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a53", "arm,armv8";
58			reg = <0x0 0x0>;
59			enable-method = "psci";
60			i-cache-size = <0x8000>;
61			i-cache-line-size = <64>;
62			i-cache-sets = <256>;
63			d-cache-size = <0x8000>;
64			d-cache-line-size = <64>;
65			d-cache-sets = <128>;
66			next-level-cache = <&A53_L2>;
67		};
68
69		A53_1: cpu@1 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a53", "arm,armv8";
72			reg = <0x0 0x1>;
73			enable-method = "psci";
74			i-cache-size = <0x8000>;
75			i-cache-line-size = <64>;
76			i-cache-sets = <256>;
77			d-cache-size = <0x8000>;
78			d-cache-line-size = <64>;
79			d-cache-sets = <128>;
80			next-level-cache = <&A53_L2>;
81		};
82
83		A53_2: cpu@2 {
84			device_type = "cpu";
85			compatible = "arm,cortex-a53", "arm,armv8";
86			reg = <0x0 0x2>;
87			enable-method = "psci";
88			i-cache-size = <0x8000>;
89			i-cache-line-size = <64>;
90			i-cache-sets = <256>;
91			d-cache-size = <0x8000>;
92			d-cache-line-size = <64>;
93			d-cache-sets = <128>;
94			next-level-cache = <&A53_L2>;
95		};
96
97		A53_3: cpu@3 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a53", "arm,armv8";
100			reg = <0x0 0x3>;
101			enable-method = "psci";
102			i-cache-size = <0x8000>;
103			i-cache-line-size = <64>;
104			i-cache-sets = <256>;
105			d-cache-size = <0x8000>;
106			d-cache-line-size = <64>;
107			d-cache-sets = <128>;
108			next-level-cache = <&A53_L2>;
109		};
110
111		A72_0: cpu@100 {
112			device_type = "cpu";
113			compatible = "arm,cortex-a72", "arm,armv8";
114			reg = <0x0 0x100>;
115			enable-method = "psci";
116			i-cache-size = <0xC000>;
117			i-cache-line-size = <64>;
118			i-cache-sets = <256>;
119			d-cache-size = <0x8000>;
120			d-cache-line-size = <64>;
121			d-cache-sets = <256>;
122			next-level-cache = <&A72_L2>;
123		};
124
125		A72_1: cpu@101 {
126			device_type = "cpu";
127			compatible = "arm,cortex-a72", "arm,armv8";
128			reg = <0x0 0x101>;
129			enable-method = "psci";
130			next-level-cache = <&A72_L2>;
131		};
132
133		A53_L2: l2-cache0 {
134			compatible = "cache";
135			cache-level = <2>;
136			cache-size = <0x100000>;
137			cache-line-size = <64>;
138			cache-sets = <1024>;
139		};
140
141		A72_L2: l2-cache1 {
142			compatible = "cache";
143			cache-level = <2>;
144			cache-size = <0x100000>;
145			cache-line-size = <64>;
146			cache-sets = <1024>;
147		};
148	};
149
150	gic: interrupt-controller@51a00000 {
151		compatible = "arm,gic-v3";
152		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
153		      <0x0 0x51b00000 0 0xC0000>, /* GICR */
154		      <0x0 0x52000000 0 0x2000>,  /* GICC */
155		      <0x0 0x52010000 0 0x1000>,  /* GICH */
156		      <0x0 0x52020000 0 0x20000>; /* GICV */
157		#interrupt-cells = <3>;
158		interrupt-controller;
159		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
160		interrupt-parent = <&gic>;
161	};
162
163	pmu {
164		compatible = "arm,armv8-pmuv3";
165		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
166	};
167
168	psci {
169		compatible = "arm,psci-1.0";
170		method = "smc";
171	};
172
173	timer {
174		compatible = "arm,armv8-timer";
175		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
176			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
177			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
178			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
179	};
180
181	scu {
182		compatible = "fsl,imx-scu";
183		mbox-names = "tx0",
184			     "rx0",
185			     "gip3";
186		mboxes = <&lsio_mu1 0 0
187			  &lsio_mu1 1 0
188			  &lsio_mu1 3 3>;
189
190		pd: imx8qx-pd {
191			compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
192			#power-domain-cells = <1>;
193		};
194
195		clk: clock-controller {
196			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
197			#clock-cells = <2>;
198		};
199
200		iomuxc: pinctrl {
201			compatible = "fsl,imx8qm-iomuxc";
202		};
203
204	};
205
206	/* sorted in register address */
207	#include "imx8-ss-img.dtsi"
208	#include "imx8-ss-dma.dtsi"
209	#include "imx8-ss-conn.dtsi"
210	#include "imx8-ss-lsio.dtsi"
211};
212
213#include "imx8qm-ss-img.dtsi"
214#include "imx8qm-ss-dma.dtsi"
215#include "imx8qm-ss-conn.dtsi"
216#include "imx8qm-ss-lsio.dtsi"
217