1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018-2019 NXP
4 *	Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7/dts-v1/;
8
9#include "imx8qm.dtsi"
10
11/ {
12	model = "Freescale i.MX8QM MEK";
13	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
14
15	chosen {
16		stdout-path = &lpuart0;
17	};
18
19	cpus {
20		/delete-node/ cpu-map;
21		/delete-node/ cpu@100;
22		/delete-node/ cpu@101;
23	};
24
25	thermal-zones {
26		/delete-node/ cpu1-thermal;
27	};
28
29	memory@80000000 {
30		device_type = "memory";
31		reg = <0x00000000 0x80000000 0 0x40000000>;
32	};
33
34	reg_usdhc2_vmmc: usdhc2-vmmc {
35		compatible = "regulator-fixed";
36		regulator-name = "SD1_SPWR";
37		regulator-min-microvolt = <3000000>;
38		regulator-max-microvolt = <3000000>;
39		gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
40		enable-active-high;
41	};
42};
43
44&lpuart0 {
45	pinctrl-names = "default";
46	pinctrl-0 = <&pinctrl_lpuart0>;
47	status = "okay";
48};
49
50&fec1 {
51	pinctrl-names = "default";
52	pinctrl-0 = <&pinctrl_fec1>;
53	phy-mode = "rgmii-id";
54	phy-handle = <&ethphy0>;
55	fsl,magic-packet;
56	status = "okay";
57
58	mdio {
59		#address-cells = <1>;
60		#size-cells = <0>;
61
62		ethphy0: ethernet-phy@0 {
63			compatible = "ethernet-phy-ieee802.3-c22";
64			reg = <0>;
65		};
66
67		ethphy1: ethernet-phy@1 {
68			compatible = "ethernet-phy-ieee802.3-c22";
69			reg = <1>;
70		};
71	};
72};
73
74&usdhc1 {
75	pinctrl-names = "default";
76	pinctrl-0 = <&pinctrl_usdhc1>;
77	bus-width = <8>;
78	no-sd;
79	no-sdio;
80	non-removable;
81	status = "okay";
82};
83
84&usdhc2 {
85	pinctrl-names = "default";
86	pinctrl-0 = <&pinctrl_usdhc2>;
87	bus-width = <4>;
88	vmmc-supply = <&reg_usdhc2_vmmc>;
89	cd-gpios = <&lsio_gpio5 22 GPIO_ACTIVE_LOW>;
90	wp-gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>;
91	status = "okay";
92};
93
94&iomuxc {
95	pinctrl_fec1: fec1grp {
96		fsl,pins = <
97			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020
98			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
99			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
100			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
101			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
102			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
103			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
104			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
105			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
106			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
107			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
108			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
109			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
110			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
111		>;
112	};
113
114	pinctrl_lpuart0: lpuart0grp {
115		fsl,pins = <
116			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
117			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020
118		>;
119	};
120
121	pinctrl_usdhc1: usdhc1grp {
122		fsl,pins = <
123			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
124			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
125			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
126			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
127			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
128			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
129			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
130			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
131			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
132			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
133			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
134		>;
135	};
136
137	pinctrl_usdhc2: usdhc2grp {
138		fsl,pins = <
139			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
140			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
141			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
142			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
143			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
144			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
145			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
146		>;
147	};
148};
149