1*307fd14dSDong Aisheng// SPDX-License-Identifier: GPL-2.0+ 2*307fd14dSDong Aisheng/* 3*307fd14dSDong Aisheng * Copyright 2018-2019 NXP 4*307fd14dSDong Aisheng * Dong Aisheng <aisheng.dong@nxp.com> 5*307fd14dSDong Aisheng */ 6*307fd14dSDong Aisheng 7*307fd14dSDong Aisheng/dts-v1/; 8*307fd14dSDong Aisheng 9*307fd14dSDong Aisheng#include "imx8qm.dtsi" 10*307fd14dSDong Aisheng 11*307fd14dSDong Aisheng/ { 12*307fd14dSDong Aisheng model = "Freescale i.MX8QM MEK"; 13*307fd14dSDong Aisheng compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; 14*307fd14dSDong Aisheng 15*307fd14dSDong Aisheng chosen { 16*307fd14dSDong Aisheng stdout-path = &lpuart0; 17*307fd14dSDong Aisheng }; 18*307fd14dSDong Aisheng 19*307fd14dSDong Aisheng cpus { 20*307fd14dSDong Aisheng /delete-node/ cpu-map; 21*307fd14dSDong Aisheng /delete-node/ cpu@100; 22*307fd14dSDong Aisheng /delete-node/ cpu@101; 23*307fd14dSDong Aisheng }; 24*307fd14dSDong Aisheng 25*307fd14dSDong Aisheng memory@80000000 { 26*307fd14dSDong Aisheng device_type = "memory"; 27*307fd14dSDong Aisheng reg = <0x00000000 0x80000000 0 0x40000000>; 28*307fd14dSDong Aisheng }; 29*307fd14dSDong Aisheng 30*307fd14dSDong Aisheng reg_usdhc2_vmmc: usdhc2-vmmc { 31*307fd14dSDong Aisheng compatible = "regulator-fixed"; 32*307fd14dSDong Aisheng regulator-name = "SD1_SPWR"; 33*307fd14dSDong Aisheng regulator-min-microvolt = <3000000>; 34*307fd14dSDong Aisheng regulator-max-microvolt = <3000000>; 35*307fd14dSDong Aisheng gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 36*307fd14dSDong Aisheng enable-active-high; 37*307fd14dSDong Aisheng }; 38*307fd14dSDong Aisheng}; 39*307fd14dSDong Aisheng 40*307fd14dSDong Aisheng&lpuart0 { 41*307fd14dSDong Aisheng pinctrl-names = "default"; 42*307fd14dSDong Aisheng pinctrl-0 = <&pinctrl_lpuart0>; 43*307fd14dSDong Aisheng status = "okay"; 44*307fd14dSDong Aisheng}; 45*307fd14dSDong Aisheng 46*307fd14dSDong Aisheng&fec1 { 47*307fd14dSDong Aisheng pinctrl-names = "default"; 48*307fd14dSDong Aisheng pinctrl-0 = <&pinctrl_fec1>; 49*307fd14dSDong Aisheng phy-mode = "rgmii-id"; 50*307fd14dSDong Aisheng phy-handle = <ðphy0>; 51*307fd14dSDong Aisheng fsl,magic-packet; 52*307fd14dSDong Aisheng status = "okay"; 53*307fd14dSDong Aisheng 54*307fd14dSDong Aisheng mdio { 55*307fd14dSDong Aisheng #address-cells = <1>; 56*307fd14dSDong Aisheng #size-cells = <0>; 57*307fd14dSDong Aisheng 58*307fd14dSDong Aisheng ethphy0: ethernet-phy@0 { 59*307fd14dSDong Aisheng compatible = "ethernet-phy-ieee802.3-c22"; 60*307fd14dSDong Aisheng reg = <0>; 61*307fd14dSDong Aisheng }; 62*307fd14dSDong Aisheng 63*307fd14dSDong Aisheng ethphy1: ethernet-phy@1 { 64*307fd14dSDong Aisheng compatible = "ethernet-phy-ieee802.3-c22"; 65*307fd14dSDong Aisheng reg = <1>; 66*307fd14dSDong Aisheng }; 67*307fd14dSDong Aisheng }; 68*307fd14dSDong Aisheng}; 69*307fd14dSDong Aisheng 70*307fd14dSDong Aisheng&usdhc1 { 71*307fd14dSDong Aisheng pinctrl-names = "default"; 72*307fd14dSDong Aisheng pinctrl-0 = <&pinctrl_usdhc1>; 73*307fd14dSDong Aisheng bus-width = <8>; 74*307fd14dSDong Aisheng no-sd; 75*307fd14dSDong Aisheng no-sdio; 76*307fd14dSDong Aisheng non-removable; 77*307fd14dSDong Aisheng status = "okay"; 78*307fd14dSDong Aisheng}; 79*307fd14dSDong Aisheng 80*307fd14dSDong Aisheng&usdhc2 { 81*307fd14dSDong Aisheng pinctrl-names = "default"; 82*307fd14dSDong Aisheng pinctrl-0 = <&pinctrl_usdhc2>; 83*307fd14dSDong Aisheng bus-width = <4>; 84*307fd14dSDong Aisheng vmmc-supply = <®_usdhc2_vmmc>; 85*307fd14dSDong Aisheng cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; 86*307fd14dSDong Aisheng wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; 87*307fd14dSDong Aisheng status = "okay"; 88*307fd14dSDong Aisheng}; 89*307fd14dSDong Aisheng 90*307fd14dSDong Aisheng&iomuxc { 91*307fd14dSDong Aisheng pinctrl_fec1: fec1grp { 92*307fd14dSDong Aisheng fsl,pins = < 93*307fd14dSDong Aisheng IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 94*307fd14dSDong Aisheng IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 95*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 96*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 97*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 98*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 99*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 100*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 101*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 102*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 103*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 104*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 105*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 106*307fd14dSDong Aisheng IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 107*307fd14dSDong Aisheng >; 108*307fd14dSDong Aisheng }; 109*307fd14dSDong Aisheng 110*307fd14dSDong Aisheng pinctrl_lpuart0: lpuart0grp { 111*307fd14dSDong Aisheng fsl,pins = < 112*307fd14dSDong Aisheng IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 113*307fd14dSDong Aisheng IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 114*307fd14dSDong Aisheng >; 115*307fd14dSDong Aisheng }; 116*307fd14dSDong Aisheng 117*307fd14dSDong Aisheng pinctrl_usdhc1: usdhc1grp { 118*307fd14dSDong Aisheng fsl,pins = < 119*307fd14dSDong Aisheng IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 120*307fd14dSDong Aisheng IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 121*307fd14dSDong Aisheng IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 122*307fd14dSDong Aisheng IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 123*307fd14dSDong Aisheng IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 124*307fd14dSDong Aisheng IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 125*307fd14dSDong Aisheng IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 126*307fd14dSDong Aisheng IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 127*307fd14dSDong Aisheng IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 128*307fd14dSDong Aisheng IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 129*307fd14dSDong Aisheng IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 130*307fd14dSDong Aisheng >; 131*307fd14dSDong Aisheng }; 132*307fd14dSDong Aisheng 133*307fd14dSDong Aisheng pinctrl_usdhc2: usdhc2grp { 134*307fd14dSDong Aisheng fsl,pins = < 135*307fd14dSDong Aisheng IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 136*307fd14dSDong Aisheng IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 137*307fd14dSDong Aisheng IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 138*307fd14dSDong Aisheng IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 139*307fd14dSDong Aisheng IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 140*307fd14dSDong Aisheng IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 141*307fd14dSDong Aisheng IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 142*307fd14dSDong Aisheng >; 143*307fd14dSDong Aisheng }; 144*307fd14dSDong Aisheng}; 145