1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include "imx8mq-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gpc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 serial0 = &uart1; 33 serial1 = &uart2; 34 serial2 = &uart3; 35 serial3 = &uart4; 36 spi0 = &ecspi1; 37 spi1 = &ecspi2; 38 spi2 = &ecspi3; 39 }; 40 41 ckil: clock-ckil { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <32768>; 45 clock-output-names = "ckil"; 46 }; 47 48 osc_25m: clock-osc-25m { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <25000000>; 52 clock-output-names = "osc_25m"; 53 }; 54 55 osc_27m: clock-osc-27m { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <27000000>; 59 clock-output-names = "osc_27m"; 60 }; 61 62 clk_ext1: clock-ext1 { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <133000000>; 66 clock-output-names = "clk_ext1"; 67 }; 68 69 clk_ext2: clock-ext2 { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <133000000>; 73 clock-output-names = "clk_ext2"; 74 }; 75 76 clk_ext3: clock-ext3 { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <133000000>; 80 clock-output-names = "clk_ext3"; 81 }; 82 83 clk_ext4: clock-ext4 { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency= <133000000>; 87 clock-output-names = "clk_ext4"; 88 }; 89 90 cpus { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 94 A53_0: cpu@0 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x0>; 98 clock-latency = <61036>; /* two CLK32 periods */ 99 clocks = <&clk IMX8MQ_CLK_ARM>; 100 enable-method = "psci"; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 nvmem-cells = <&cpu_speed_grade>; 105 nvmem-cell-names = "speed_grade"; 106 }; 107 108 A53_1: cpu@1 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x1>; 112 clock-latency = <61036>; /* two CLK32 periods */ 113 clocks = <&clk IMX8MQ_CLK_ARM>; 114 enable-method = "psci"; 115 next-level-cache = <&A53_L2>; 116 operating-points-v2 = <&a53_opp_table>; 117 #cooling-cells = <2>; 118 }; 119 120 A53_2: cpu@2 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x2>; 124 clock-latency = <61036>; /* two CLK32 periods */ 125 clocks = <&clk IMX8MQ_CLK_ARM>; 126 enable-method = "psci"; 127 next-level-cache = <&A53_L2>; 128 operating-points-v2 = <&a53_opp_table>; 129 #cooling-cells = <2>; 130 }; 131 132 A53_3: cpu@3 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53"; 135 reg = <0x3>; 136 clock-latency = <61036>; /* two CLK32 periods */ 137 clocks = <&clk IMX8MQ_CLK_ARM>; 138 enable-method = "psci"; 139 next-level-cache = <&A53_L2>; 140 operating-points-v2 = <&a53_opp_table>; 141 #cooling-cells = <2>; 142 }; 143 144 A53_L2: l2-cache0 { 145 compatible = "cache"; 146 }; 147 }; 148 149 a53_opp_table: opp-table { 150 compatible = "operating-points-v2"; 151 opp-shared; 152 153 opp-800000000 { 154 opp-hz = /bits/ 64 <800000000>; 155 opp-microvolt = <900000>; 156 /* Industrial only */ 157 opp-supported-hw = <0xf>, <0x4>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 162 opp-1000000000 { 163 opp-hz = /bits/ 64 <1000000000>; 164 opp-microvolt = <900000>; 165 /* Consumer only */ 166 opp-supported-hw = <0xe>, <0x3>; 167 clock-latency-ns = <150000>; 168 opp-suspend; 169 }; 170 171 opp-1300000000 { 172 opp-hz = /bits/ 64 <1300000000>; 173 opp-microvolt = <1000000>; 174 opp-supported-hw = <0xc>, <0x4>; 175 clock-latency-ns = <150000>; 176 opp-suspend; 177 }; 178 179 opp-1500000000 { 180 opp-hz = /bits/ 64 <1500000000>; 181 opp-microvolt = <1000000>; 182 opp-supported-hw = <0x8>, <0x3>; 183 clock-latency-ns = <150000>; 184 opp-suspend; 185 }; 186 }; 187 188 pmu { 189 compatible = "arm,cortex-a53-pmu"; 190 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 191 interrupt-parent = <&gic>; 192 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 193 }; 194 195 psci { 196 compatible = "arm,psci-1.0"; 197 method = "smc"; 198 }; 199 200 thermal-zones { 201 cpu_thermal: cpu-thermal { 202 polling-delay-passive = <250>; 203 polling-delay = <2000>; 204 thermal-sensors = <&tmu 0>; 205 206 trips { 207 cpu_alert: cpu-alert { 208 temperature = <80000>; 209 hysteresis = <2000>; 210 type = "passive"; 211 }; 212 213 cpu-crit { 214 temperature = <90000>; 215 hysteresis = <2000>; 216 type = "critical"; 217 }; 218 }; 219 220 cooling-maps { 221 map0 { 222 trip = <&cpu_alert>; 223 cooling-device = 224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 228 }; 229 }; 230 }; 231 232 gpu-thermal { 233 polling-delay-passive = <250>; 234 polling-delay = <2000>; 235 thermal-sensors = <&tmu 1>; 236 237 trips { 238 gpu_alert: gpu-alert { 239 temperature = <80000>; 240 hysteresis = <2000>; 241 type = "passive"; 242 }; 243 244 gpu-crit { 245 temperature = <90000>; 246 hysteresis = <2000>; 247 type = "critical"; 248 }; 249 }; 250 251 cooling-maps { 252 map0 { 253 trip = <&gpu_alert>; 254 cooling-device = 255 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 256 }; 257 }; 258 }; 259 260 vpu-thermal { 261 polling-delay-passive = <250>; 262 polling-delay = <2000>; 263 thermal-sensors = <&tmu 2>; 264 265 trips { 266 vpu-crit { 267 temperature = <90000>; 268 hysteresis = <2000>; 269 type = "critical"; 270 }; 271 }; 272 }; 273 }; 274 275 timer { 276 compatible = "arm,armv8-timer"; 277 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 278 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 279 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 280 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 281 interrupt-parent = <&gic>; 282 arm,no-tick-in-suspend; 283 }; 284 285 soc@0 { 286 compatible = "simple-bus"; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 ranges = <0x0 0x0 0x0 0x3e000000>; 290 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 291 292 bus@30000000 { /* AIPS1 */ 293 compatible = "fsl,aips-bus", "simple-bus"; 294 reg = <0x30000000 0x400000>; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 ranges = <0x30000000 0x30000000 0x400000>; 298 299 sai1: sai@30010000 { 300 #sound-dai-cells = <0>; 301 compatible = "fsl,imx8mq-sai"; 302 reg = <0x30010000 0x10000>; 303 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 305 <&clk IMX8MQ_CLK_SAI1_ROOT>, 306 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 307 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 308 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 309 dma-names = "rx", "tx"; 310 status = "disabled"; 311 }; 312 313 sai6: sai@30030000 { 314 #sound-dai-cells = <0>; 315 compatible = "fsl,imx8mq-sai"; 316 reg = <0x30030000 0x10000>; 317 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 319 <&clk IMX8MQ_CLK_SAI6_ROOT>, 320 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 321 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 322 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 323 dma-names = "rx", "tx"; 324 status = "disabled"; 325 }; 326 327 sai5: sai@30040000 { 328 #sound-dai-cells = <0>; 329 compatible = "fsl,imx8mq-sai"; 330 reg = <0x30040000 0x10000>; 331 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 333 <&clk IMX8MQ_CLK_SAI5_ROOT>, 334 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 335 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 336 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 }; 340 341 sai4: sai@30050000 { 342 #sound-dai-cells = <0>; 343 compatible = "fsl,imx8mq-sai"; 344 reg = <0x30050000 0x10000>; 345 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 347 <&clk IMX8MQ_CLK_SAI4_ROOT>, 348 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 349 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 350 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 351 dma-names = "rx", "tx"; 352 status = "disabled"; 353 }; 354 355 gpio1: gpio@30200000 { 356 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 357 reg = <0x30200000 0x10000>; 358 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 gpio-ranges = <&iomuxc 0 10 30>; 366 }; 367 368 gpio2: gpio@30210000 { 369 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 370 reg = <0x30210000 0x10000>; 371 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 374 gpio-controller; 375 #gpio-cells = <2>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 gpio-ranges = <&iomuxc 0 40 21>; 379 }; 380 381 gpio3: gpio@30220000 { 382 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 383 reg = <0x30220000 0x10000>; 384 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 387 gpio-controller; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 gpio-ranges = <&iomuxc 0 61 26>; 392 }; 393 394 gpio4: gpio@30230000 { 395 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 396 reg = <0x30230000 0x10000>; 397 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 400 gpio-controller; 401 #gpio-cells = <2>; 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 gpio-ranges = <&iomuxc 0 87 32>; 405 }; 406 407 gpio5: gpio@30240000 { 408 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 409 reg = <0x30240000 0x10000>; 410 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 413 gpio-controller; 414 #gpio-cells = <2>; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 gpio-ranges = <&iomuxc 0 119 30>; 418 }; 419 420 tmu: tmu@30260000 { 421 compatible = "fsl,imx8mq-tmu"; 422 reg = <0x30260000 0x10000>; 423 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 425 little-endian; 426 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 427 fsl,tmu-calibration = <0x00000000 0x00000023 428 0x00000001 0x00000029 429 0x00000002 0x0000002f 430 0x00000003 0x00000035 431 0x00000004 0x0000003d 432 0x00000005 0x00000043 433 0x00000006 0x0000004b 434 0x00000007 0x00000051 435 0x00000008 0x00000057 436 0x00000009 0x0000005f 437 0x0000000a 0x00000067 438 0x0000000b 0x0000006f 439 440 0x00010000 0x0000001b 441 0x00010001 0x00000023 442 0x00010002 0x0000002b 443 0x00010003 0x00000033 444 0x00010004 0x0000003b 445 0x00010005 0x00000043 446 0x00010006 0x0000004b 447 0x00010007 0x00000055 448 0x00010008 0x0000005d 449 0x00010009 0x00000067 450 0x0001000a 0x00000070 451 452 0x00020000 0x00000017 453 0x00020001 0x00000023 454 0x00020002 0x0000002d 455 0x00020003 0x00000037 456 0x00020004 0x00000041 457 0x00020005 0x0000004b 458 0x00020006 0x00000057 459 0x00020007 0x00000063 460 0x00020008 0x0000006f 461 462 0x00030000 0x00000015 463 0x00030001 0x00000021 464 0x00030002 0x0000002d 465 0x00030003 0x00000039 466 0x00030004 0x00000045 467 0x00030005 0x00000053 468 0x00030006 0x0000005f 469 0x00030007 0x00000071>; 470 #thermal-sensor-cells = <1>; 471 }; 472 473 wdog1: watchdog@30280000 { 474 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 475 reg = <0x30280000 0x10000>; 476 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 478 status = "disabled"; 479 }; 480 481 wdog2: watchdog@30290000 { 482 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 483 reg = <0x30290000 0x10000>; 484 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 486 status = "disabled"; 487 }; 488 489 wdog3: watchdog@302a0000 { 490 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 491 reg = <0x302a0000 0x10000>; 492 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 494 status = "disabled"; 495 }; 496 497 sdma2: sdma@302c0000 { 498 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 499 reg = <0x302c0000 0x10000>; 500 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 502 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 503 clock-names = "ipg", "ahb"; 504 #dma-cells = <3>; 505 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 506 }; 507 508 lcdif: lcd-controller@30320000 { 509 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; 510 reg = <0x30320000 0x10000>; 511 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 513 clock-names = "pix"; 514 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 515 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 516 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 517 <&clk IMX8MQ_VIDEO_PLL1>; 518 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 519 <&clk IMX8MQ_VIDEO_PLL1>, 520 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 521 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 522 status = "disabled"; 523 }; 524 525 iomuxc: pinctrl@30330000 { 526 compatible = "fsl,imx8mq-iomuxc"; 527 reg = <0x30330000 0x10000>; 528 }; 529 530 iomuxc_gpr: syscon@30340000 { 531 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", 532 "syscon", "simple-mfd"; 533 reg = <0x30340000 0x10000>; 534 535 mux: mux-controller { 536 compatible = "mmio-mux"; 537 #mux-control-cells = <1>; 538 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 539 }; 540 }; 541 542 ocotp: ocotp-ctrl@30350000 { 543 compatible = "fsl,imx8mq-ocotp", "syscon"; 544 reg = <0x30350000 0x10000>; 545 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 546 #address-cells = <1>; 547 #size-cells = <1>; 548 549 cpu_speed_grade: speed-grade@10 { 550 reg = <0x10 4>; 551 }; 552 }; 553 554 anatop: syscon@30360000 { 555 compatible = "fsl,imx8mq-anatop", "syscon"; 556 reg = <0x30360000 0x10000>; 557 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 558 }; 559 560 snvs: snvs@30370000 { 561 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 562 reg = <0x30370000 0x10000>; 563 564 snvs_rtc: snvs-rtc-lp{ 565 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 566 regmap =<&snvs>; 567 offset = <0x34>; 568 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 571 clock-names = "snvs-rtc"; 572 }; 573 574 snvs_pwrkey: snvs-powerkey { 575 compatible = "fsl,sec-v4.0-pwrkey"; 576 regmap = <&snvs>; 577 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 579 clock-names = "snvs-pwrkey"; 580 linux,keycode = <KEY_POWER>; 581 wakeup-source; 582 status = "disabled"; 583 }; 584 }; 585 586 clk: clock-controller@30380000 { 587 compatible = "fsl,imx8mq-ccm"; 588 reg = <0x30380000 0x10000>; 589 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 591 #clock-cells = <1>; 592 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 593 <&clk_ext1>, <&clk_ext2>, 594 <&clk_ext3>, <&clk_ext4>; 595 clock-names = "ckil", "osc_25m", "osc_27m", 596 "clk_ext1", "clk_ext2", 597 "clk_ext3", "clk_ext4"; 598 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, 599 <&clk IMX8MQ_CLK_A53_CORE>, 600 <&clk IMX8MQ_CLK_NOC>; 601 assigned-clock-rates = <0>, <0>, 602 <800000000>; 603 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, 604 <&clk IMX8MQ_ARM_PLL_OUT>; 605 }; 606 607 src: reset-controller@30390000 { 608 compatible = "fsl,imx8mq-src", "syscon"; 609 reg = <0x30390000 0x10000>; 610 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 611 #reset-cells = <1>; 612 }; 613 614 gpc: gpc@303a0000 { 615 compatible = "fsl,imx8mq-gpc"; 616 reg = <0x303a0000 0x10000>; 617 interrupt-parent = <&gic>; 618 interrupt-controller; 619 #interrupt-cells = <3>; 620 621 pgc { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 625 pgc_mipi: power-domain@0 { 626 #power-domain-cells = <0>; 627 reg = <IMX8M_POWER_DOMAIN_MIPI>; 628 }; 629 630 /* 631 * As per comment in ATF source code: 632 * 633 * PCIE1 and PCIE2 share the 634 * same reset signal, if we 635 * power down PCIE2, PCIE1 636 * will be held in reset too. 637 * 638 * So instead of creating two 639 * separate power domains for 640 * PCIE1 and PCIE2 we create a 641 * link between both and use 642 * it as a shared PCIE power 643 * domain. 644 */ 645 pgc_pcie: power-domain@1 { 646 #power-domain-cells = <0>; 647 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 648 power-domains = <&pgc_pcie2>; 649 }; 650 651 pgc_otg1: power-domain@2 { 652 #power-domain-cells = <0>; 653 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 654 }; 655 656 pgc_otg2: power-domain@3 { 657 #power-domain-cells = <0>; 658 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 659 }; 660 661 pgc_ddr1: power-domain@4 { 662 #power-domain-cells = <0>; 663 reg = <IMX8M_POWER_DOMAIN_DDR1>; 664 }; 665 666 pgc_gpu: power-domain@5 { 667 #power-domain-cells = <0>; 668 reg = <IMX8M_POWER_DOMAIN_GPU>; 669 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 670 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 671 <&clk IMX8MQ_CLK_GPU_AXI>, 672 <&clk IMX8MQ_CLK_GPU_AHB>; 673 }; 674 675 pgc_vpu: power-domain@6 { 676 #power-domain-cells = <0>; 677 reg = <IMX8M_POWER_DOMAIN_VPU>; 678 }; 679 680 pgc_disp: power-domain@7 { 681 #power-domain-cells = <0>; 682 reg = <IMX8M_POWER_DOMAIN_DISP>; 683 }; 684 685 pgc_mipi_csi1: power-domain@8 { 686 #power-domain-cells = <0>; 687 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 688 }; 689 690 pgc_mipi_csi2: power-domain@9 { 691 #power-domain-cells = <0>; 692 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 693 }; 694 695 pgc_pcie2: power-domain@a { 696 #power-domain-cells = <0>; 697 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 698 }; 699 }; 700 }; 701 }; 702 703 bus@30400000 { /* AIPS2 */ 704 compatible = "fsl,aips-bus", "simple-bus"; 705 reg = <0x30400000 0x400000>; 706 #address-cells = <1>; 707 #size-cells = <1>; 708 ranges = <0x30400000 0x30400000 0x400000>; 709 710 pwm1: pwm@30660000 { 711 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 712 reg = <0x30660000 0x10000>; 713 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 715 <&clk IMX8MQ_CLK_PWM1_ROOT>; 716 clock-names = "ipg", "per"; 717 #pwm-cells = <2>; 718 status = "disabled"; 719 }; 720 721 pwm2: pwm@30670000 { 722 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 723 reg = <0x30670000 0x10000>; 724 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 726 <&clk IMX8MQ_CLK_PWM2_ROOT>; 727 clock-names = "ipg", "per"; 728 #pwm-cells = <2>; 729 status = "disabled"; 730 }; 731 732 pwm3: pwm@30680000 { 733 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 734 reg = <0x30680000 0x10000>; 735 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 737 <&clk IMX8MQ_CLK_PWM3_ROOT>; 738 clock-names = "ipg", "per"; 739 #pwm-cells = <2>; 740 status = "disabled"; 741 }; 742 743 pwm4: pwm@30690000 { 744 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 745 reg = <0x30690000 0x10000>; 746 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 748 <&clk IMX8MQ_CLK_PWM4_ROOT>; 749 clock-names = "ipg", "per"; 750 #pwm-cells = <2>; 751 status = "disabled"; 752 }; 753 754 system_counter: timer@306a0000 { 755 compatible = "nxp,sysctr-timer"; 756 reg = <0x306a0000 0x20000>; 757 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&osc_25m>; 759 clock-names = "per"; 760 }; 761 }; 762 763 bus@30800000 { /* AIPS3 */ 764 compatible = "fsl,aips-bus", "simple-bus"; 765 reg = <0x30800000 0x400000>; 766 #address-cells = <1>; 767 #size-cells = <1>; 768 ranges = <0x30800000 0x30800000 0x400000>, 769 <0x08000000 0x08000000 0x10000000>; 770 771 ecspi1: spi@30820000 { 772 #address-cells = <1>; 773 #size-cells = <0>; 774 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 775 reg = <0x30820000 0x10000>; 776 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 778 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 779 clock-names = "ipg", "per"; 780 status = "disabled"; 781 }; 782 783 ecspi2: spi@30830000 { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 787 reg = <0x30830000 0x10000>; 788 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 790 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 791 clock-names = "ipg", "per"; 792 status = "disabled"; 793 }; 794 795 ecspi3: spi@30840000 { 796 #address-cells = <1>; 797 #size-cells = <0>; 798 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 799 reg = <0x30840000 0x10000>; 800 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 802 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 803 clock-names = "ipg", "per"; 804 status = "disabled"; 805 }; 806 807 uart1: serial@30860000 { 808 compatible = "fsl,imx8mq-uart", 809 "fsl,imx6q-uart"; 810 reg = <0x30860000 0x10000>; 811 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 813 <&clk IMX8MQ_CLK_UART1_ROOT>; 814 clock-names = "ipg", "per"; 815 status = "disabled"; 816 }; 817 818 uart3: serial@30880000 { 819 compatible = "fsl,imx8mq-uart", 820 "fsl,imx6q-uart"; 821 reg = <0x30880000 0x10000>; 822 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 824 <&clk IMX8MQ_CLK_UART3_ROOT>; 825 clock-names = "ipg", "per"; 826 status = "disabled"; 827 }; 828 829 uart2: serial@30890000 { 830 compatible = "fsl,imx8mq-uart", 831 "fsl,imx6q-uart"; 832 reg = <0x30890000 0x10000>; 833 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 835 <&clk IMX8MQ_CLK_UART2_ROOT>; 836 clock-names = "ipg", "per"; 837 status = "disabled"; 838 }; 839 840 sai2: sai@308b0000 { 841 #sound-dai-cells = <0>; 842 compatible = "fsl,imx8mq-sai"; 843 reg = <0x308b0000 0x10000>; 844 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 846 <&clk IMX8MQ_CLK_SAI2_ROOT>, 847 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 848 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 849 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 850 dma-names = "rx", "tx"; 851 status = "disabled"; 852 }; 853 854 sai3: sai@308c0000 { 855 #sound-dai-cells = <0>; 856 compatible = "fsl,imx8mq-sai"; 857 reg = <0x308c0000 0x10000>; 858 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 860 <&clk IMX8MQ_CLK_SAI3_ROOT>, 861 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 862 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 863 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 864 dma-names = "rx", "tx"; 865 status = "disabled"; 866 }; 867 868 crypto: crypto@30900000 { 869 compatible = "fsl,sec-v4.0"; 870 #address-cells = <1>; 871 #size-cells = <1>; 872 reg = <0x30900000 0x40000>; 873 ranges = <0 0x30900000 0x40000>; 874 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&clk IMX8MQ_CLK_AHB>, 876 <&clk IMX8MQ_CLK_IPG_ROOT>; 877 clock-names = "aclk", "ipg"; 878 879 sec_jr0: jr@1000 { 880 compatible = "fsl,sec-v4.0-job-ring"; 881 reg = <0x1000 0x1000>; 882 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 883 }; 884 885 sec_jr1: jr@2000 { 886 compatible = "fsl,sec-v4.0-job-ring"; 887 reg = <0x2000 0x1000>; 888 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 889 }; 890 891 sec_jr2: jr@3000 { 892 compatible = "fsl,sec-v4.0-job-ring"; 893 reg = <0x3000 0x1000>; 894 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 895 }; 896 }; 897 898 dphy: dphy@30a00300 { 899 compatible = "fsl,imx8mq-mipi-dphy"; 900 reg = <0x30a00300 0x100>; 901 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 902 clock-names = "phy_ref"; 903 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 904 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; 905 assigned-clock-rates = <24000000>; 906 #phy-cells = <0>; 907 power-domains = <&pgc_mipi>; 908 status = "disabled"; 909 }; 910 911 i2c1: i2c@30a20000 { 912 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 913 reg = <0x30a20000 0x10000>; 914 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 status = "disabled"; 919 }; 920 921 i2c2: i2c@30a30000 { 922 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 923 reg = <0x30a30000 0x10000>; 924 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 status = "disabled"; 929 }; 930 931 i2c3: i2c@30a40000 { 932 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 933 reg = <0x30a40000 0x10000>; 934 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 status = "disabled"; 939 }; 940 941 i2c4: i2c@30a50000 { 942 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 943 reg = <0x30a50000 0x10000>; 944 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 status = "disabled"; 949 }; 950 951 uart4: serial@30a60000 { 952 compatible = "fsl,imx8mq-uart", 953 "fsl,imx6q-uart"; 954 reg = <0x30a60000 0x10000>; 955 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 957 <&clk IMX8MQ_CLK_UART4_ROOT>; 958 clock-names = "ipg", "per"; 959 status = "disabled"; 960 }; 961 962 usdhc1: mmc@30b40000 { 963 compatible = "fsl,imx8mq-usdhc", 964 "fsl,imx7d-usdhc"; 965 reg = <0x30b40000 0x10000>; 966 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 968 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 969 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 970 clock-names = "ipg", "ahb", "per"; 971 fsl,tuning-start-tap = <20>; 972 fsl,tuning-step = <2>; 973 bus-width = <4>; 974 status = "disabled"; 975 }; 976 977 usdhc2: mmc@30b50000 { 978 compatible = "fsl,imx8mq-usdhc", 979 "fsl,imx7d-usdhc"; 980 reg = <0x30b50000 0x10000>; 981 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 983 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 984 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 985 clock-names = "ipg", "ahb", "per"; 986 fsl,tuning-start-tap = <20>; 987 fsl,tuning-step = <2>; 988 bus-width = <4>; 989 status = "disabled"; 990 }; 991 992 qspi0: spi@30bb0000 { 993 #address-cells = <1>; 994 #size-cells = <0>; 995 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 996 reg = <0x30bb0000 0x10000>, 997 <0x08000000 0x10000000>; 998 reg-names = "QuadSPI", "QuadSPI-memory"; 999 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 1001 <&clk IMX8MQ_CLK_QSPI_ROOT>; 1002 clock-names = "qspi_en", "qspi"; 1003 status = "disabled"; 1004 }; 1005 1006 sdma1: sdma@30bd0000 { 1007 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 1008 reg = <0x30bd0000 0x10000>; 1009 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1011 <&clk IMX8MQ_CLK_AHB>; 1012 clock-names = "ipg", "ahb"; 1013 #dma-cells = <3>; 1014 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1015 }; 1016 1017 fec1: ethernet@30be0000 { 1018 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1019 reg = <0x30be0000 0x10000>; 1020 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1024 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1025 <&clk IMX8MQ_CLK_ENET_TIMER>, 1026 <&clk IMX8MQ_CLK_ENET_REF>, 1027 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1028 clock-names = "ipg", "ahb", "ptp", 1029 "enet_clk_ref", "enet_out"; 1030 fsl,num-tx-queues = <3>; 1031 fsl,num-rx-queues = <3>; 1032 status = "disabled"; 1033 }; 1034 }; 1035 1036 bus@32c00000 { /* AIPS4 */ 1037 compatible = "fsl,aips-bus", "simple-bus"; 1038 reg = <0x32c00000 0x400000>; 1039 #address-cells = <1>; 1040 #size-cells = <1>; 1041 ranges = <0x32c00000 0x32c00000 0x400000>; 1042 1043 irqsteer: interrupt-controller@32e2d000 { 1044 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1045 reg = <0x32e2d000 0x1000>; 1046 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1047 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1048 clock-names = "ipg"; 1049 fsl,channel = <0>; 1050 fsl,num-irqs = <64>; 1051 interrupt-controller; 1052 #interrupt-cells = <1>; 1053 }; 1054 }; 1055 1056 gpu: gpu@38000000 { 1057 compatible = "vivante,gc"; 1058 reg = <0x38000000 0x40000>; 1059 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1061 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1062 <&clk IMX8MQ_CLK_GPU_AXI>, 1063 <&clk IMX8MQ_CLK_GPU_AHB>; 1064 clock-names = "core", "shader", "bus", "reg"; 1065 #cooling-cells = <2>; 1066 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1067 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1068 <&clk IMX8MQ_CLK_GPU_AXI>, 1069 <&clk IMX8MQ_CLK_GPU_AHB>, 1070 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1071 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1072 <&clk IMX8MQ_GPU_PLL_OUT>, 1073 <&clk IMX8MQ_GPU_PLL_OUT>, 1074 <&clk IMX8MQ_GPU_PLL_OUT>, 1075 <&clk IMX8MQ_GPU_PLL>; 1076 assigned-clock-rates = <800000000>, <800000000>, 1077 <800000000>, <800000000>, <0>; 1078 power-domains = <&pgc_gpu>; 1079 }; 1080 1081 usb_dwc3_0: usb@38100000 { 1082 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1083 reg = <0x38100000 0x10000>; 1084 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1085 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1086 <&clk IMX8MQ_CLK_32K>; 1087 clock-names = "bus_early", "ref", "suspend"; 1088 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1089 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1090 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1091 <&clk IMX8MQ_SYS1_PLL_100M>; 1092 assigned-clock-rates = <500000000>, <100000000>; 1093 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1094 phys = <&usb3_phy0>, <&usb3_phy0>; 1095 phy-names = "usb2-phy", "usb3-phy"; 1096 power-domains = <&pgc_otg1>; 1097 usb3-resume-missing-cas; 1098 status = "disabled"; 1099 }; 1100 1101 usb3_phy0: usb-phy@381f0040 { 1102 compatible = "fsl,imx8mq-usb-phy"; 1103 reg = <0x381f0040 0x40>; 1104 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1105 clock-names = "phy"; 1106 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1107 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1108 assigned-clock-rates = <100000000>; 1109 #phy-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 usb_dwc3_1: usb@38200000 { 1114 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1115 reg = <0x38200000 0x10000>; 1116 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1117 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1118 <&clk IMX8MQ_CLK_32K>; 1119 clock-names = "bus_early", "ref", "suspend"; 1120 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1121 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1122 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1123 <&clk IMX8MQ_SYS1_PLL_100M>; 1124 assigned-clock-rates = <500000000>, <100000000>; 1125 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1126 phys = <&usb3_phy1>, <&usb3_phy1>; 1127 phy-names = "usb2-phy", "usb3-phy"; 1128 power-domains = <&pgc_otg2>; 1129 usb3-resume-missing-cas; 1130 status = "disabled"; 1131 }; 1132 1133 usb3_phy1: usb-phy@382f0040 { 1134 compatible = "fsl,imx8mq-usb-phy"; 1135 reg = <0x382f0040 0x40>; 1136 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1137 clock-names = "phy"; 1138 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1139 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1140 assigned-clock-rates = <100000000>; 1141 #phy-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 pcie0: pcie@33800000 { 1146 compatible = "fsl,imx8mq-pcie"; 1147 reg = <0x33800000 0x400000>, 1148 <0x1ff00000 0x80000>; 1149 reg-names = "dbi", "config"; 1150 #address-cells = <3>; 1151 #size-cells = <2>; 1152 device_type = "pci"; 1153 bus-range = <0x00 0xff>; 1154 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ 1155 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1156 num-lanes = <1>; 1157 num-viewport = <4>; 1158 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1159 interrupt-names = "msi"; 1160 #interrupt-cells = <1>; 1161 interrupt-map-mask = <0 0 0 0x7>; 1162 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1163 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1164 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1165 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1166 fsl,max-link-speed = <2>; 1167 power-domains = <&pgc_pcie>; 1168 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1169 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1170 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1171 reset-names = "pciephy", "apps", "turnoff"; 1172 status = "disabled"; 1173 }; 1174 1175 pcie1: pcie@33c00000 { 1176 compatible = "fsl,imx8mq-pcie"; 1177 reg = <0x33c00000 0x400000>, 1178 <0x27f00000 0x80000>; 1179 reg-names = "dbi", "config"; 1180 #address-cells = <3>; 1181 #size-cells = <2>; 1182 device_type = "pci"; 1183 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ 1184 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1185 num-lanes = <1>; 1186 num-viewport = <4>; 1187 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1188 interrupt-names = "msi"; 1189 #interrupt-cells = <1>; 1190 interrupt-map-mask = <0 0 0 0x7>; 1191 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1192 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1193 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1194 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1195 fsl,max-link-speed = <2>; 1196 power-domains = <&pgc_pcie>; 1197 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1198 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1199 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1200 reset-names = "pciephy", "apps", "turnoff"; 1201 status = "disabled"; 1202 }; 1203 1204 gic: interrupt-controller@38800000 { 1205 compatible = "arm,gic-v3"; 1206 reg = <0x38800000 0x10000>, /* GIC Dist */ 1207 <0x38880000 0xc0000>, /* GICR */ 1208 <0x31000000 0x2000>, /* GICC */ 1209 <0x31010000 0x2000>, /* GICV */ 1210 <0x31020000 0x2000>; /* GICH */ 1211 #interrupt-cells = <3>; 1212 interrupt-controller; 1213 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1214 interrupt-parent = <&gic>; 1215 }; 1216 1217 ddrc: memory-controller@3d400000 { 1218 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1219 reg = <0x3d400000 0x400000>; 1220 clock-names = "core", "pll", "alt", "apb"; 1221 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1222 <&clk IMX8MQ_DRAM_PLL_OUT>, 1223 <&clk IMX8MQ_CLK_DRAM_ALT>, 1224 <&clk IMX8MQ_CLK_DRAM_APB>; 1225 }; 1226 1227 ddr-pmu@3d800000 { 1228 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1229 reg = <0x3d800000 0x400000>; 1230 interrupt-parent = <&gic>; 1231 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1232 }; 1233 }; 1234}; 1235